2 * Device Tree Source for the r8a7792 SoC
4 * Copyright (C) 2016 Cogent Embedded Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/clock/r8a7792-clock.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/r8a7792-sysc.h>
17 compatible = "renesas,r8a7792";
42 enable-method = "renesas,apmu";
46 compatible = "arm,cortex-a15";
48 clock-frequency = <1000000000>;
50 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
51 next-level-cache = <&L2_CA15>;
56 compatible = "arm,cortex-a15";
58 clock-frequency = <1000000000>;
59 power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
60 next-level-cache = <&L2_CA15>;
63 L2_CA15: cache-controller-0 {
67 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
72 compatible = "simple-bus";
73 interrupt-parent = <&gic>;
80 compatible = "renesas,r8a7792-apmu", "renesas,apmu";
81 reg = <0 0xe6152000 0 0x188>;
85 gic: interrupt-controller@f1001000 {
86 compatible = "arm,gic-400";
87 #interrupt-cells = <3>;
89 reg = <0 0xf1001000 0 0x1000>,
90 <0 0xf1002000 0 0x2000>,
91 <0 0xf1004000 0 0x2000>,
92 <0 0xf1006000 0 0x2000>;
93 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
94 IRQ_TYPE_LEVEL_HIGH)>;
95 clocks = <&mstp4_clks R8A7792_CLK_INTC_SYS>;
97 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
100 irqc: interrupt-controller@e61c0000 {
101 compatible = "renesas,irqc-r8a7792", "renesas,irqc";
102 #interrupt-cells = <2>;
103 interrupt-controller;
104 reg = <0 0xe61c0000 0 0x200>;
105 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
109 clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
110 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
114 compatible = "arm,armv7-timer";
115 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
116 IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
118 IRQ_TYPE_LEVEL_LOW)>,
119 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
120 IRQ_TYPE_LEVEL_LOW)>,
121 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
122 IRQ_TYPE_LEVEL_LOW)>;
125 rst: reset-controller@e6160000 {
126 compatible = "renesas,r8a7792-rst";
127 reg = <0 0xe6160000 0 0x0100>;
130 prr: chipid@ff000044 {
131 compatible = "renesas,prr";
132 reg = <0 0xff000044 0 4>;
135 sysc: system-controller@e6180000 {
136 compatible = "renesas,r8a7792-sysc";
137 reg = <0 0xe6180000 0 0x0200>;
138 #power-domain-cells = <1>;
141 pfc: pin-controller@e6060000 {
142 compatible = "renesas,pfc-r8a7792";
143 reg = <0 0xe6060000 0 0x144>;
146 gpio0: gpio@e6050000 {
147 compatible = "renesas,gpio-r8a7792",
149 reg = <0 0xe6050000 0 0x50>;
150 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
153 gpio-ranges = <&pfc 0 0 29>;
154 #interrupt-cells = <2>;
155 interrupt-controller;
156 clocks = <&mstp9_clks R8A7792_CLK_GPIO0>;
157 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
160 gpio1: gpio@e6051000 {
161 compatible = "renesas,gpio-r8a7792",
163 reg = <0 0xe6051000 0 0x50>;
164 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
167 gpio-ranges = <&pfc 0 32 23>;
168 #interrupt-cells = <2>;
169 interrupt-controller;
170 clocks = <&mstp9_clks R8A7792_CLK_GPIO1>;
171 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
174 gpio2: gpio@e6052000 {
175 compatible = "renesas,gpio-r8a7792",
177 reg = <0 0xe6052000 0 0x50>;
178 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
181 gpio-ranges = <&pfc 0 64 32>;
182 #interrupt-cells = <2>;
183 interrupt-controller;
184 clocks = <&mstp9_clks R8A7792_CLK_GPIO2>;
185 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
188 gpio3: gpio@e6053000 {
189 compatible = "renesas,gpio-r8a7792",
191 reg = <0 0xe6053000 0 0x50>;
192 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
195 gpio-ranges = <&pfc 0 96 28>;
196 #interrupt-cells = <2>;
197 interrupt-controller;
198 clocks = <&mstp9_clks R8A7792_CLK_GPIO3>;
199 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
202 gpio4: gpio@e6054000 {
203 compatible = "renesas,gpio-r8a7792",
205 reg = <0 0xe6054000 0 0x50>;
206 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
209 gpio-ranges = <&pfc 0 128 17>;
210 #interrupt-cells = <2>;
211 interrupt-controller;
212 clocks = <&mstp9_clks R8A7792_CLK_GPIO4>;
213 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
216 gpio5: gpio@e6055000 {
217 compatible = "renesas,gpio-r8a7792",
219 reg = <0 0xe6055000 0 0x50>;
220 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
223 gpio-ranges = <&pfc 0 160 17>;
224 #interrupt-cells = <2>;
225 interrupt-controller;
226 clocks = <&mstp9_clks R8A7792_CLK_GPIO5>;
227 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
230 gpio6: gpio@e6055100 {
231 compatible = "renesas,gpio-r8a7792",
233 reg = <0 0xe6055100 0 0x50>;
234 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
237 gpio-ranges = <&pfc 0 192 17>;
238 #interrupt-cells = <2>;
239 interrupt-controller;
240 clocks = <&mstp9_clks R8A7792_CLK_GPIO6>;
241 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
244 gpio7: gpio@e6055200 {
245 compatible = "renesas,gpio-r8a7792",
247 reg = <0 0xe6055200 0 0x50>;
248 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
251 gpio-ranges = <&pfc 0 224 17>;
252 #interrupt-cells = <2>;
253 interrupt-controller;
254 clocks = <&mstp9_clks R8A7792_CLK_GPIO7>;
255 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
258 gpio8: gpio@e6055300 {
259 compatible = "renesas,gpio-r8a7792",
261 reg = <0 0xe6055300 0 0x50>;
262 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
265 gpio-ranges = <&pfc 0 256 17>;
266 #interrupt-cells = <2>;
267 interrupt-controller;
268 clocks = <&mstp9_clks R8A7792_CLK_GPIO8>;
269 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
272 gpio9: gpio@e6055400 {
273 compatible = "renesas,gpio-r8a7792",
275 reg = <0 0xe6055400 0 0x50>;
276 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
279 gpio-ranges = <&pfc 0 288 17>;
280 #interrupt-cells = <2>;
281 interrupt-controller;
282 clocks = <&mstp9_clks R8A7792_CLK_GPIO9>;
283 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
286 gpio10: gpio@e6055500 {
287 compatible = "renesas,gpio-r8a7792",
289 reg = <0 0xe6055500 0 0x50>;
290 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
293 gpio-ranges = <&pfc 0 320 32>;
294 #interrupt-cells = <2>;
295 interrupt-controller;
296 clocks = <&mstp9_clks R8A7792_CLK_GPIO10>;
297 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
300 gpio11: gpio@e6055600 {
301 compatible = "renesas,gpio-r8a7792",
303 reg = <0 0xe6055600 0 0x50>;
304 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
307 gpio-ranges = <&pfc 0 352 30>;
308 #interrupt-cells = <2>;
309 interrupt-controller;
310 clocks = <&mstp9_clks R8A7792_CLK_GPIO11>;
311 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
314 dmac0: dma-controller@e6700000 {
315 compatible = "renesas,dmac-r8a7792",
317 reg = <0 0xe6700000 0 0x20000>;
318 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
319 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
320 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
329 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
330 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
331 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
332 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
333 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
334 interrupt-names = "error",
335 "ch0", "ch1", "ch2", "ch3",
336 "ch4", "ch5", "ch6", "ch7",
337 "ch8", "ch9", "ch10", "ch11",
338 "ch12", "ch13", "ch14";
339 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
341 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
346 dmac1: dma-controller@e6720000 {
347 compatible = "renesas,dmac-r8a7792",
349 reg = <0 0xe6720000 0 0x20000>;
350 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
355 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
360 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
361 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
362 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
363 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
364 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
365 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
366 interrupt-names = "error",
367 "ch0", "ch1", "ch2", "ch3",
368 "ch4", "ch5", "ch6", "ch7",
369 "ch8", "ch9", "ch10", "ch11",
370 "ch12", "ch13", "ch14";
371 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
373 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
378 scif0: serial@e6e60000 {
379 compatible = "renesas,scif-r8a7792",
380 "renesas,rcar-gen2-scif", "renesas,scif";
381 reg = <0 0xe6e60000 0 64>;
382 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
385 clock-names = "fck", "brg_int", "scif_clk";
386 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
387 <&dmac1 0x29>, <&dmac1 0x2a>;
388 dma-names = "tx", "rx", "tx", "rx";
389 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
393 scif1: serial@e6e68000 {
394 compatible = "renesas,scif-r8a7792",
395 "renesas,rcar-gen2-scif", "renesas,scif";
396 reg = <0 0xe6e68000 0 64>;
397 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
400 clock-names = "fck", "brg_int", "scif_clk";
401 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
402 <&dmac1 0x2d>, <&dmac1 0x2e>;
403 dma-names = "tx", "rx", "tx", "rx";
404 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
408 scif2: serial@e6e58000 {
409 compatible = "renesas,scif-r8a7792",
410 "renesas,rcar-gen2-scif", "renesas,scif";
411 reg = <0 0xe6e58000 0 64>;
412 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
415 clock-names = "fck", "brg_int", "scif_clk";
416 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
417 <&dmac1 0x2b>, <&dmac1 0x2c>;
418 dma-names = "tx", "rx", "tx", "rx";
419 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
423 scif3: serial@e6ea8000 {
424 compatible = "renesas,scif-r8a7792",
425 "renesas,rcar-gen2-scif", "renesas,scif";
426 reg = <0 0xe6ea8000 0 64>;
427 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
430 clock-names = "fck", "brg_int", "scif_clk";
431 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
432 <&dmac1 0x2f>, <&dmac1 0x30>;
433 dma-names = "tx", "rx", "tx", "rx";
434 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
438 hscif0: serial@e62c0000 {
439 compatible = "renesas,hscif-r8a7792",
440 "renesas,rcar-gen2-hscif", "renesas,hscif";
441 reg = <0 0xe62c0000 0 96>;
442 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
445 clock-names = "fck", "brg_int", "scif_clk";
446 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
447 <&dmac1 0x39>, <&dmac1 0x3a>;
448 dma-names = "tx", "rx", "tx", "rx";
449 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
453 hscif1: serial@e62c8000 {
454 compatible = "renesas,hscif-r8a7792",
455 "renesas,rcar-gen2-hscif", "renesas,hscif";
456 reg = <0 0xe62c8000 0 96>;
457 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
460 clock-names = "fck", "brg_int", "scif_clk";
461 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
462 <&dmac1 0x4d>, <&dmac1 0x4e>;
463 dma-names = "tx", "rx", "tx", "rx";
464 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
469 compatible = "renesas,sdhi-r8a7792";
470 reg = <0 0xee100000 0 0x328>;
471 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
472 dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
473 <&dmac1 0xcd>, <&dmac1 0xce>;
474 dma-names = "tx", "rx", "tx", "rx";
475 clocks = <&mstp3_clks R8A7792_CLK_SDHI0>;
476 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
480 jpu: jpeg-codec@fe980000 {
481 compatible = "renesas,jpu-r8a7792",
482 "renesas,rcar-gen2-jpu";
483 reg = <0 0xfe980000 0 0x10300>;
484 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&mstp1_clks R8A7792_CLK_JPU>;
486 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
489 avb: ethernet@e6800000 {
490 compatible = "renesas,etheravb-r8a7792",
491 "renesas,etheravb-rcar-gen2";
492 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
493 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>;
495 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
496 #address-cells = <1>;
501 /* I2C doesn't need pinmux */
503 compatible = "renesas,i2c-r8a7792",
504 "renesas,rcar-gen2-i2c";
505 reg = <0 0xe6508000 0 0x40>;
506 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&mstp9_clks R8A7792_CLK_I2C0>;
508 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
509 i2c-scl-internal-delay-ns = <6>;
510 #address-cells = <1>;
516 compatible = "renesas,i2c-r8a7792",
517 "renesas,rcar-gen2-i2c";
518 reg = <0 0xe6518000 0 0x40>;
519 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&mstp9_clks R8A7792_CLK_I2C1>;
521 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
522 i2c-scl-internal-delay-ns = <6>;
523 #address-cells = <1>;
529 compatible = "renesas,i2c-r8a7792",
530 "renesas,rcar-gen2-i2c";
531 reg = <0 0xe6530000 0 0x40>;
532 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&mstp9_clks R8A7792_CLK_I2C2>;
534 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
535 i2c-scl-internal-delay-ns = <6>;
536 #address-cells = <1>;
542 compatible = "renesas,i2c-r8a7792",
543 "renesas,rcar-gen2-i2c";
544 reg = <0 0xe6540000 0 0x40>;
545 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&mstp9_clks R8A7792_CLK_I2C3>;
547 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
548 i2c-scl-internal-delay-ns = <6>;
549 #address-cells = <1>;
555 compatible = "renesas,i2c-r8a7792",
556 "renesas,rcar-gen2-i2c";
557 reg = <0 0xe6520000 0 0x40>;
558 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&mstp9_clks R8A7792_CLK_I2C4>;
560 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
561 i2c-scl-internal-delay-ns = <6>;
562 #address-cells = <1>;
568 compatible = "renesas,i2c-r8a7792",
569 "renesas,rcar-gen2-i2c";
570 reg = <0 0xe6528000 0 0x40>;
571 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&mstp9_clks R8A7792_CLK_I2C5>;
573 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
574 i2c-scl-internal-delay-ns = <110>;
575 #address-cells = <1>;
581 compatible = "renesas,qspi-r8a7792", "renesas,qspi";
582 reg = <0 0xe6b10000 0 0x2c>;
583 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>;
585 dmas = <&dmac0 0x17>, <&dmac0 0x18>,
586 <&dmac1 0x17>, <&dmac1 0x18>;
587 dma-names = "tx", "rx", "tx", "rx";
588 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
590 #address-cells = <1>;
595 msiof0: spi@e6e20000 {
596 compatible = "renesas,msiof-r8a7792",
597 "renesas,rcar-gen2-msiof";
598 reg = <0 0xe6e20000 0 0x0064>;
599 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>;
601 dmas = <&dmac0 0x51>, <&dmac0 0x52>,
602 <&dmac1 0x51>, <&dmac1 0x52>;
603 dma-names = "tx", "rx", "tx", "rx";
604 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
605 #address-cells = <1>;
610 msiof1: spi@e6e10000 {
611 compatible = "renesas,msiof-r8a7792",
612 "renesas,rcar-gen2-msiof";
613 reg = <0 0xe6e10000 0 0x0064>;
614 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>;
616 dmas = <&dmac0 0x55>, <&dmac0 0x56>,
617 <&dmac1 0x55>, <&dmac1 0x56>;
618 dma-names = "tx", "rx", "tx", "rx";
619 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
620 #address-cells = <1>;
625 du: display@feb00000 {
626 compatible = "renesas,du-r8a7792";
627 reg = <0 0xfeb00000 0 0x40000>;
629 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&mstp7_clks R8A7792_CLK_DU0>,
632 <&mstp7_clks R8A7792_CLK_DU1>;
633 clock-names = "du.0", "du.1";
637 #address-cells = <1>;
642 du_out_rgb0: endpoint {
647 du_out_rgb1: endpoint {
654 compatible = "renesas,can-r8a7792",
655 "renesas,rcar-gen2-can";
656 reg = <0 0xe6e80000 0 0x1000>;
657 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&mstp9_clks R8A7792_CLK_CAN0>,
659 <&rcan_clk>, <&can_clk>;
660 clock-names = "clkp1", "clkp2", "can_clk";
661 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
666 compatible = "renesas,can-r8a7792",
667 "renesas,rcar-gen2-can";
668 reg = <0 0xe6e88000 0 0x1000>;
669 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&mstp9_clks R8A7792_CLK_CAN1>,
671 <&rcan_clk>, <&can_clk>;
672 clock-names = "clkp1", "clkp2", "can_clk";
673 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
677 vin0: video@e6ef0000 {
678 compatible = "renesas,vin-r8a7792",
679 "renesas,rcar-gen2-vin";
680 reg = <0 0xe6ef0000 0 0x1000>;
681 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&mstp8_clks R8A7792_CLK_VIN0>;
683 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
687 vin1: video@e6ef1000 {
688 compatible = "renesas,vin-r8a7792",
689 "renesas,rcar-gen2-vin";
690 reg = <0 0xe6ef1000 0 0x1000>;
691 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
692 clocks = <&mstp8_clks R8A7792_CLK_VIN1>;
693 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
697 vin2: video@e6ef2000 {
698 compatible = "renesas,vin-r8a7792",
699 "renesas,rcar-gen2-vin";
700 reg = <0 0xe6ef2000 0 0x1000>;
701 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
702 clocks = <&mstp8_clks R8A7792_CLK_VIN2>;
703 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
707 vin3: video@e6ef3000 {
708 compatible = "renesas,vin-r8a7792",
709 "renesas,rcar-gen2-vin";
710 reg = <0 0xe6ef3000 0 0x1000>;
711 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&mstp8_clks R8A7792_CLK_VIN3>;
713 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
717 vin4: video@e6ef4000 {
718 compatible = "renesas,vin-r8a7792",
719 "renesas,rcar-gen2-vin";
720 reg = <0 0xe6ef4000 0 0x1000>;
721 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&mstp8_clks R8A7792_CLK_VIN4>;
723 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
727 vin5: video@e6ef5000 {
728 compatible = "renesas,vin-r8a7792",
729 "renesas,rcar-gen2-vin";
730 reg = <0 0xe6ef5000 0 0x1000>;
731 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&mstp8_clks R8A7792_CLK_VIN5>;
733 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
738 compatible = "renesas,vsp1";
739 reg = <0 0xfe928000 0 0x8000>;
740 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>;
742 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
746 compatible = "renesas,vsp1";
747 reg = <0 0xfe930000 0 0x8000>;
748 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>;
750 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
754 compatible = "renesas,vsp1";
755 reg = <0 0xfe938000 0 0x8000>;
756 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>;
758 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
761 /* Special CPG clocks */
762 cpg_clocks: cpg_clocks@e6150000 {
763 compatible = "renesas,r8a7792-cpg-clocks",
764 "renesas,rcar-gen2-cpg-clocks";
765 reg = <0 0xe6150000 0 0x1000>;
766 clocks = <&extal_clk>;
768 clock-output-names = "main", "pll0", "pll1", "pll3",
770 #power-domain-cells = <0>;
773 /* Fixed factor clocks */
774 pll1_div2_clk: pll1_div2 {
775 compatible = "fixed-factor-clock";
776 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
782 compatible = "fixed-factor-clock";
783 clocks = <&cpg_clocks R8A7792_CLK_PLL0>;
789 compatible = "fixed-factor-clock";
790 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
796 compatible = "fixed-factor-clock";
797 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
803 compatible = "fixed-factor-clock";
804 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
810 compatible = "fixed-factor-clock";
811 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
817 compatible = "fixed-factor-clock";
818 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
824 compatible = "fixed-factor-clock";
825 clocks = <&pll1_div2_clk>;
831 compatible = "fixed-factor-clock";
832 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
838 compatible = "fixed-factor-clock";
839 clocks = <&pll1_div2_clk>;
845 compatible = "fixed-factor-clock";
846 clocks = <&pll1_div2_clk>;
852 compatible = "fixed-factor-clock";
853 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
860 mstp0_clks: mstp0_clks@e6150130 {
861 compatible = "renesas,r8a7792-mstp-clocks",
862 "renesas,cpg-mstp-clocks";
863 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
866 clock-indices = <R8A7792_CLK_MSIOF0>;
867 clock-output-names = "msiof0";
869 mstp1_clks: mstp1_clks@e6150134 {
870 compatible = "renesas,r8a7792-mstp-clocks",
871 "renesas,cpg-mstp-clocks";
872 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
873 clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
877 R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0
880 clock-output-names = "jpu", "vsp1du1", "vsp1du0",
883 mstp2_clks: mstp2_clks@e6150138 {
884 compatible = "renesas,r8a7792-mstp-clocks",
885 "renesas,cpg-mstp-clocks";
886 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
887 clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>;
891 R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
893 clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0";
895 mstp3_clks: mstp3_clks@e615013c {
896 compatible = "renesas,r8a7792-mstp-clocks",
897 "renesas,cpg-mstp-clocks";
898 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
901 renesas,clock-indices = <R8A7792_CLK_SDHI0>;
902 clock-output-names = "sdhi0";
904 mstp4_clks: mstp4_clks@e6150140 {
905 compatible = "renesas,r8a7792-mstp-clocks",
906 "renesas,cpg-mstp-clocks";
907 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
908 clocks = <&cp_clk>, <&zs_clk>;
911 R8A7792_CLK_IRQC R8A7792_CLK_INTC_SYS
913 clock-output-names = "irqc", "intc-sys";
915 mstp7_clks: mstp7_clks@e615014c {
916 compatible = "renesas,r8a7792-mstp-clocks",
917 "renesas,cpg-mstp-clocks";
918 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
919 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
920 <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>;
923 R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
924 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
925 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
926 R8A7792_CLK_DU1 R8A7792_CLK_DU0
928 clock-output-names = "hscif1", "hscif0", "scif3",
929 "scif2", "scif1", "scif0",
932 mstp8_clks: mstp8_clks@e6150990 {
933 compatible = "renesas,r8a7792-mstp-clocks",
934 "renesas,cpg-mstp-clocks";
935 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
936 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
937 <&zg_clk>, <&zg_clk>, <&hp_clk>;
940 R8A7792_CLK_VIN5 R8A7792_CLK_VIN4
941 R8A7792_CLK_VIN3 R8A7792_CLK_VIN2
942 R8A7792_CLK_VIN1 R8A7792_CLK_VIN0
945 clock-output-names = "vin5", "vin4", "vin3", "vin2",
946 "vin1", "vin0", "etheravb";
948 mstp9_clks: mstp9_clks@e6150994 {
949 compatible = "renesas,r8a7792-mstp-clocks",
950 "renesas,cpg-mstp-clocks";
951 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
952 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
953 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
954 <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
955 <&cpg_clocks R8A7792_CLK_QSPI>,
956 <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>,
957 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
960 R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6
961 R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4
962 R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2
963 R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
964 R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
965 R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
967 R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8
968 R8A7792_CLK_I2C5 R8A7792_CLK_I2C4
969 R8A7792_CLK_I2C3 R8A7792_CLK_I2C2
970 R8A7792_CLK_I2C1 R8A7792_CLK_I2C0
973 "gpio7", "gpio6", "gpio5", "gpio4",
974 "gpio3", "gpio2", "gpio1", "gpio0",
975 "gpio11", "gpio10", "can1", "can0",
976 "qspi_mod", "gpio9", "gpio8",
977 "i2c5", "i2c4", "i2c3", "i2c2",
982 /* External root clock */
984 compatible = "fixed-clock";
986 /* This value must be overridden by the board. */
987 clock-frequency = <0>;
990 /* External SCIF clock */
992 compatible = "fixed-clock";
994 /* This value must be overridden by the board. */
995 clock-frequency = <0>;
998 /* External CAN clock */
1000 compatible = "fixed-clock";
1002 /* This value must be overridden by the board. */
1003 clock-frequency = <0>;