2 * Device Tree Source for Renesas r8a7779
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Simon Horman
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r8a7779-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/power/r8a7779-sysc.h>
18 compatible = "renesas,r8a7779";
19 interrupt-parent = <&gic>;
29 compatible = "arm,cortex-a9";
31 clock-frequency = <1000000000>;
35 compatible = "arm,cortex-a9";
37 clock-frequency = <1000000000>;
38 power-domains = <&sysc R8A7779_PD_ARM1>;
42 compatible = "arm,cortex-a9";
44 clock-frequency = <1000000000>;
45 power-domains = <&sysc R8A7779_PD_ARM2>;
49 compatible = "arm,cortex-a9";
51 clock-frequency = <1000000000>;
52 power-domains = <&sysc R8A7779_PD_ARM3>;
62 gic: interrupt-controller@f0001000 {
63 compatible = "arm,cortex-a9-gic";
64 #interrupt-cells = <3>;
66 reg = <0xf0001000 0x1000>,
71 compatible = "arm,cortex-a9-twd-timer";
72 reg = <0xf0000600 0x20>;
73 interrupts = <GIC_PPI 13
74 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
75 clocks = <&cpg_clocks R8A7779_CLK_ZS>;
78 gpio0: gpio@ffc40000 {
79 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
80 reg = <0xffc40000 0x2c>;
81 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
84 gpio-ranges = <&pfc 0 0 32>;
85 #interrupt-cells = <2>;
89 gpio1: gpio@ffc41000 {
90 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
91 reg = <0xffc41000 0x2c>;
92 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
95 gpio-ranges = <&pfc 0 32 32>;
96 #interrupt-cells = <2>;
100 gpio2: gpio@ffc42000 {
101 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
102 reg = <0xffc42000 0x2c>;
103 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
106 gpio-ranges = <&pfc 0 64 32>;
107 #interrupt-cells = <2>;
108 interrupt-controller;
111 gpio3: gpio@ffc43000 {
112 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
113 reg = <0xffc43000 0x2c>;
114 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
117 gpio-ranges = <&pfc 0 96 32>;
118 #interrupt-cells = <2>;
119 interrupt-controller;
122 gpio4: gpio@ffc44000 {
123 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
124 reg = <0xffc44000 0x2c>;
125 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
128 gpio-ranges = <&pfc 0 128 32>;
129 #interrupt-cells = <2>;
130 interrupt-controller;
133 gpio5: gpio@ffc45000 {
134 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
135 reg = <0xffc45000 0x2c>;
136 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
139 gpio-ranges = <&pfc 0 160 32>;
140 #interrupt-cells = <2>;
141 interrupt-controller;
144 gpio6: gpio@ffc46000 {
145 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
146 reg = <0xffc46000 0x2c>;
147 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
150 gpio-ranges = <&pfc 0 192 9>;
151 #interrupt-cells = <2>;
152 interrupt-controller;
155 irqpin0: interrupt-controller@fe78001c {
156 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
157 #interrupt-cells = <2>;
159 interrupt-controller;
160 reg = <0xfe78001c 4>,
166 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
167 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
168 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
169 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
170 sense-bitfield-width = <2>;
174 #address-cells = <1>;
176 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
177 reg = <0xffc70000 0x1000>;
178 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
180 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
185 #address-cells = <1>;
187 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
188 reg = <0xffc71000 0x1000>;
189 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
191 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
196 #address-cells = <1>;
198 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
199 reg = <0xffc72000 0x1000>;
200 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
202 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
207 #address-cells = <1>;
209 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c";
210 reg = <0xffc73000 0x1000>;
211 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
213 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
217 scif0: serial@ffe40000 {
218 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
220 reg = <0xffe40000 0x100>;
221 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
223 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
224 clock-names = "fck", "brg_int", "scif_clk";
225 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
229 scif1: serial@ffe41000 {
230 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
232 reg = <0xffe41000 0x100>;
233 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
235 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
236 clock-names = "fck", "brg_int", "scif_clk";
237 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
241 scif2: serial@ffe42000 {
242 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
244 reg = <0xffe42000 0x100>;
245 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
247 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
248 clock-names = "fck", "brg_int", "scif_clk";
249 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
253 scif3: serial@ffe43000 {
254 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
256 reg = <0xffe43000 0x100>;
257 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
259 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
260 clock-names = "fck", "brg_int", "scif_clk";
261 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
265 scif4: serial@ffe44000 {
266 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
268 reg = <0xffe44000 0x100>;
269 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
271 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
272 clock-names = "fck", "brg_int", "scif_clk";
273 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
277 scif5: serial@ffe45000 {
278 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
280 reg = <0xffe45000 0x100>;
281 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
283 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
284 clock-names = "fck", "brg_int", "scif_clk";
285 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
289 pfc: pin-controller@fffc0000 {
290 compatible = "renesas,pfc-r8a7779";
291 reg = <0xfffc0000 0x23c>;
295 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
296 reg = <0xffc48000 0x38>;
299 tmu0: timer@ffd80000 {
300 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
301 reg = <0xffd80000 0x30>;
302 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
307 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
309 #renesas,channels = <3>;
314 tmu1: timer@ffd81000 {
315 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
316 reg = <0xffd81000 0x30>;
317 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
322 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
324 #renesas,channels = <3>;
329 tmu2: timer@ffd82000 {
330 compatible = "renesas,tmu-r8a7779", "renesas,tmu";
331 reg = <0xffd82000 0x30>;
332 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
337 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
339 #renesas,channels = <3>;
344 sata: sata@fc600000 {
345 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
346 reg = <0xfc600000 0x2000>;
347 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&mstp1_clks R8A7779_CLK_SATA>;
349 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
354 compatible = "renesas,sdhi-r8a7779";
355 reg = <0xffe4c000 0x100>;
356 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
358 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
363 compatible = "renesas,sdhi-r8a7779";
364 reg = <0xffe4d000 0x100>;
365 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
367 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
372 compatible = "renesas,sdhi-r8a7779";
373 reg = <0xffe4e000 0x100>;
374 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
376 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
381 compatible = "renesas,sdhi-r8a7779";
382 reg = <0xffe4f000 0x100>;
383 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
385 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
389 hspi0: spi@fffc7000 {
390 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
391 reg = <0xfffc7000 0x18>;
392 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
393 #address-cells = <1>;
395 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
396 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
400 hspi1: spi@fffc8000 {
401 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
402 reg = <0xfffc8000 0x18>;
403 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
404 #address-cells = <1>;
406 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
407 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
411 hspi2: spi@fffc6000 {
412 compatible = "renesas,hspi-r8a7779", "renesas,hspi";
413 reg = <0xfffc6000 0x18>;
414 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
415 #address-cells = <1>;
417 clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
418 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
422 du: display@fff80000 {
423 compatible = "renesas,du-r8a7779";
424 reg = <0xfff80000 0x40000>;
425 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&mstp1_clks R8A7779_CLK_DU>;
427 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
431 #address-cells = <1>;
436 du_out_rgb0: endpoint {
441 du_out_rgb1: endpoint {
448 #address-cells = <1>;
452 /* External root clock */
454 compatible = "fixed-clock";
456 /* This value must be overriden by the board. */
457 clock-frequency = <0>;
460 /* External SCIF clock */
462 compatible = "fixed-clock";
464 /* This value must be overridden by the board. */
465 clock-frequency = <0>;
468 /* Special CPG clocks */
469 cpg_clocks: clocks@ffc80000 {
470 compatible = "renesas,r8a7779-cpg-clocks";
471 reg = <0xffc80000 0x30>;
472 clocks = <&extal_clk>;
474 clock-output-names = "plla", "z", "zs", "s",
475 "s1", "p", "b", "out";
476 #power-domain-cells = <0>;
479 /* Fixed factor clocks */
481 compatible = "fixed-factor-clock";
482 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
488 compatible = "fixed-factor-clock";
489 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
495 compatible = "fixed-factor-clock";
496 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
502 compatible = "fixed-factor-clock";
503 clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
510 mstp0_clks: clocks@ffc80030 {
511 compatible = "renesas,r8a7779-mstp-clocks",
512 "renesas,cpg-mstp-clocks";
513 reg = <0xffc80030 4>;
514 clocks = <&cpg_clocks R8A7779_CLK_S>,
515 <&cpg_clocks R8A7779_CLK_P>,
516 <&cpg_clocks R8A7779_CLK_P>,
517 <&cpg_clocks R8A7779_CLK_P>,
518 <&cpg_clocks R8A7779_CLK_S>,
519 <&cpg_clocks R8A7779_CLK_S>,
520 <&cpg_clocks R8A7779_CLK_P>,
521 <&cpg_clocks R8A7779_CLK_P>,
522 <&cpg_clocks R8A7779_CLK_P>,
523 <&cpg_clocks R8A7779_CLK_P>,
524 <&cpg_clocks R8A7779_CLK_P>,
525 <&cpg_clocks R8A7779_CLK_P>,
526 <&cpg_clocks R8A7779_CLK_P>,
527 <&cpg_clocks R8A7779_CLK_P>,
528 <&cpg_clocks R8A7779_CLK_P>,
529 <&cpg_clocks R8A7779_CLK_P>;
532 R8A7779_CLK_HSPI R8A7779_CLK_TMU2
533 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
534 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
535 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
536 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
537 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
538 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
539 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
542 "hspi", "tmu2", "tmu1", "tmu0", "hscif1",
543 "hscif0", "scif5", "scif4", "scif3", "scif2",
544 "scif1", "scif0", "i2c3", "i2c2", "i2c1",
547 mstp1_clks: clocks@ffc80034 {
548 compatible = "renesas,r8a7779-mstp-clocks",
549 "renesas,cpg-mstp-clocks";
550 reg = <0xffc80034 4>, <0xffc80044 4>;
551 clocks = <&cpg_clocks R8A7779_CLK_P>,
552 <&cpg_clocks R8A7779_CLK_P>,
553 <&cpg_clocks R8A7779_CLK_S>,
554 <&cpg_clocks R8A7779_CLK_S>,
555 <&cpg_clocks R8A7779_CLK_S>,
556 <&cpg_clocks R8A7779_CLK_S>,
557 <&cpg_clocks R8A7779_CLK_P>,
558 <&cpg_clocks R8A7779_CLK_P>,
559 <&cpg_clocks R8A7779_CLK_P>,
560 <&cpg_clocks R8A7779_CLK_S>;
563 R8A7779_CLK_USB01 R8A7779_CLK_USB2
564 R8A7779_CLK_DU R8A7779_CLK_VIN2
565 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
566 R8A7779_CLK_ETHER R8A7779_CLK_SATA
567 R8A7779_CLK_PCIE R8A7779_CLK_VIN3
576 mstp3_clks: clocks@ffc8003c {
577 compatible = "renesas,r8a7779-mstp-clocks",
578 "renesas,cpg-mstp-clocks";
579 reg = <0xffc8003c 4>;
580 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
581 <&s4_clk>, <&s4_clk>;
584 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
585 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
586 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
589 "sdhi3", "sdhi2", "sdhi1", "sdhi0",
594 prr: chipid@ff000044 {
595 compatible = "renesas,prr";
596 reg = <0xff000044 4>;
599 rst: reset-controller@ffcc0000 {
600 compatible = "renesas,r8a7779-reset-wdt";
601 reg = <0xffcc0000 0x48>;
604 sysc: system-controller@ffd85000 {
605 compatible = "renesas,r8a7779-sysc";
606 reg = <0xffd85000 0x0200>;
607 #power-domain-cells = <1>;