2 * Device Tree Source for the r8a73a4 SoC
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r8a73a4-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 compatible = "renesas,r8a73a4";
18 interrupt-parent = <&gic>;
28 compatible = "arm,cortex-a15";
30 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
31 clock-frequency = <1500000000>;
32 power-domains = <&pd_a2sl>;
33 next-level-cache = <&L2_CA15>;
36 L2_CA15: cache-controller-0 {
38 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
39 power-domains = <&pd_a3sm>;
44 L2_CA7: cache-controller-1 {
46 clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
47 power-domains = <&pd_a3km>;
54 compatible = "arm,coresight-etm3x";
55 power-domains = <&pd_d4>;
59 compatible = "arm,armv7-timer";
60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
66 dbsc1: memory-controller@e6790000 {
67 compatible = "renesas,dbsc-r8a73a4";
68 reg = <0 0xe6790000 0 0x10000>;
69 power-domains = <&pd_a3bc>;
72 dbsc2: memory-controller@e67a0000 {
73 compatible = "renesas,dbsc-r8a73a4";
74 reg = <0 0xe67a0000 0 0x10000>;
75 power-domains = <&pd_a3bc>;
78 dmac: dma-multiplexer {
79 compatible = "renesas,shdma-mux";
87 dma0: dma-controller@e6700020 {
88 compatible = "renesas,shdma-r8a73a4";
89 reg = <0 0xe6700020 0 0x89e0>;
90 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
91 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
92 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
93 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
94 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
95 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
96 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
97 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
98 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
99 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
100 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
101 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
102 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
103 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
104 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
105 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
106 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
107 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
108 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
109 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
110 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
111 interrupt-names = "error",
112 "ch0", "ch1", "ch2", "ch3",
113 "ch4", "ch5", "ch6", "ch7",
114 "ch8", "ch9", "ch10", "ch11",
115 "ch12", "ch13", "ch14", "ch15",
116 "ch16", "ch17", "ch18", "ch19";
117 clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
118 power-domains = <&pd_a3sp>;
123 #address-cells = <1>;
125 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
126 reg = <0 0xe60b0000 0 0x428>;
127 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
129 power-domains = <&pd_a3sp>;
134 cmt1: timer@e6130000 {
135 compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
136 reg = <0 0xe6130000 0 0x1004>;
137 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
140 power-domains = <&pd_c5>;
144 irqc0: interrupt-controller@e61c0000 {
145 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
146 #interrupt-cells = <2>;
147 interrupt-controller;
148 reg = <0 0xe61c0000 0 0x200>;
149 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
182 power-domains = <&pd_c4>;
185 irqc1: interrupt-controller@e61c0200 {
186 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
187 #interrupt-cells = <2>;
188 interrupt-controller;
189 reg = <0 0xe61c0200 0 0x200>;
190 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
217 power-domains = <&pd_c4>;
220 pfc: pin-controller@e6050000 {
221 compatible = "renesas,pfc-r8a73a4";
222 reg = <0 0xe6050000 0 0x9000>;
226 <&pfc 0 0 31>, <&pfc 32 32 9>,
227 <&pfc 64 64 22>, <&pfc 96 96 31>,
228 <&pfc 128 128 7>, <&pfc 160 160 19>,
229 <&pfc 192 192 31>, <&pfc 224 224 27>,
230 <&pfc 256 256 28>, <&pfc 288 288 21>,
232 interrupts-extended =
233 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
234 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
235 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
236 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
237 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
238 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
239 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
240 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
241 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
242 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
243 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
244 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
245 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
246 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
247 <&irqc1 24 0>, <&irqc1 25 0>;
248 power-domains = <&pd_c5>;
252 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
253 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
254 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
255 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
257 power-domains = <&pd_c5>;
261 #address-cells = <1>;
263 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
264 reg = <0 0xe6500000 0 0x428>;
265 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
267 power-domains = <&pd_a3sp>;
272 #address-cells = <1>;
274 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
275 reg = <0 0xe6510000 0 0x428>;
276 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
278 power-domains = <&pd_a3sp>;
283 #address-cells = <1>;
285 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
286 reg = <0 0xe6520000 0 0x428>;
287 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
289 power-domains = <&pd_a3sp>;
294 #address-cells = <1>;
296 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
297 reg = <0 0xe6530000 0 0x428>;
298 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
300 power-domains = <&pd_a3sp>;
305 #address-cells = <1>;
307 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
308 reg = <0 0xe6540000 0 0x428>;
309 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
311 power-domains = <&pd_a3sp>;
316 #address-cells = <1>;
318 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
319 reg = <0 0xe6550000 0 0x428>;
320 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
322 power-domains = <&pd_a3sp>;
327 #address-cells = <1>;
329 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
330 reg = <0 0xe6560000 0 0x428>;
331 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
333 power-domains = <&pd_a3sp>;
338 #address-cells = <1>;
340 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
341 reg = <0 0xe6570000 0 0x428>;
342 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
344 power-domains = <&pd_a3sp>;
348 scifb0: serial@e6c20000 {
349 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
350 reg = <0 0xe6c20000 0 0x100>;
351 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
354 power-domains = <&pd_a3sp>;
358 scifb1: serial@e6c30000 {
359 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
360 reg = <0 0xe6c30000 0 0x100>;
361 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
364 power-domains = <&pd_a3sp>;
368 scifa0: serial@e6c40000 {
369 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
370 reg = <0 0xe6c40000 0 0x100>;
371 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
374 power-domains = <&pd_a3sp>;
378 scifa1: serial@e6c50000 {
379 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
380 reg = <0 0xe6c50000 0 0x100>;
381 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
384 power-domains = <&pd_a3sp>;
388 scifb2: serial@e6ce0000 {
389 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
390 reg = <0 0xe6ce0000 0 0x100>;
391 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
394 power-domains = <&pd_a3sp>;
398 scifb3: serial@e6cf0000 {
399 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
400 reg = <0 0xe6cf0000 0 0x100>;
401 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
404 power-domains = <&pd_c4>;
409 compatible = "renesas,sdhi-r8a73a4";
410 reg = <0 0xee100000 0 0x100>;
411 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
413 power-domains = <&pd_a3sp>;
419 compatible = "renesas,sdhi-r8a73a4";
420 reg = <0 0xee120000 0 0x100>;
421 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
423 power-domains = <&pd_a3sp>;
429 compatible = "renesas,sdhi-r8a73a4";
430 reg = <0 0xee140000 0 0x100>;
431 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
433 power-domains = <&pd_a3sp>;
438 mmcif0: mmc@ee200000 {
439 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
440 reg = <0 0xee200000 0 0x80>;
441 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
443 power-domains = <&pd_a3sp>;
448 mmcif1: mmc@ee220000 {
449 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
450 reg = <0 0xee220000 0 0x80>;
451 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
453 power-domains = <&pd_a3sp>;
458 gic: interrupt-controller@f1001000 {
459 compatible = "arm,gic-400";
460 #interrupt-cells = <3>;
461 #address-cells = <0>;
462 interrupt-controller;
463 reg = <0 0xf1001000 0 0x1000>,
464 <0 0xf1002000 0 0x2000>,
465 <0 0xf1004000 0 0x2000>,
466 <0 0xf1006000 0 0x2000>;
467 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
468 clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
470 power-domains = <&pd_c4>;
474 compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
476 #address-cells = <1>;
478 ranges = <0 0 0 0x20000000>;
479 reg = <0 0xfec10000 0 0x400>;
481 power-domains = <&pd_c4>;
485 #address-cells = <2>;
489 /* External root clocks */
491 compatible = "fixed-clock";
493 clock-frequency = <32768>;
496 compatible = "fixed-clock";
498 clock-frequency = <25000000>;
501 compatible = "fixed-clock";
503 clock-frequency = <48000000>;
506 compatible = "fixed-clock";
508 /* This value must be overridden by the board. */
509 clock-frequency = <0>;
512 compatible = "fixed-clock";
514 /* This value must be overridden by the board. */
515 clock-frequency = <0>;
518 /* Special CPG clocks */
519 cpg_clocks: cpg_clocks@e6150000 {
520 compatible = "renesas,r8a73a4-cpg-clocks";
521 reg = <0 0xe6150000 0 0x10000>;
522 clocks = <&extal1_clk>, <&extal2_clk>;
524 clock-output-names = "main", "pll0", "pll1", "pll2",
525 "pll2s", "pll2h", "z", "z2",
526 "i", "m3", "b", "m1", "m2",
530 /* Variable factor clocks (DIV6) */
531 zb_clk: zb_clk@e6150010 {
532 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
533 reg = <0 0xe6150010 0 4>;
534 clocks = <&pll1_div2_clk>, <0>,
535 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
537 clock-output-names = "zb";
539 sdhi0_clk: sdhi0ck@e6150074 {
540 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
541 reg = <0 0xe6150074 0 4>;
542 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
546 sdhi1_clk: sdhi1ck@e6150078 {
547 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
548 reg = <0 0xe6150078 0 4>;
549 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
553 sdhi2_clk: sdhi2ck@e615007c {
554 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
555 reg = <0 0xe615007c 0 4>;
556 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
560 mmc0_clk: mmc0@e6150240 {
561 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
562 reg = <0 0xe6150240 0 4>;
563 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
567 mmc1_clk: mmc1@e6150244 {
568 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
569 reg = <0 0xe6150244 0 4>;
570 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
574 vclk1_clk: vclk1@e6150008 {
575 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
576 reg = <0 0xe6150008 0 4>;
577 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
578 <0>, <&extal2_clk>, <&main_div2_clk>,
579 <&extalr_clk>, <0>, <0>;
582 vclk2_clk: vclk2@e615000c {
583 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
584 reg = <0 0xe615000c 0 4>;
585 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
586 <0>, <&extal2_clk>, <&main_div2_clk>,
587 <&extalr_clk>, <0>, <0>;
590 vclk3_clk: vclk3@e615001c {
591 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
592 reg = <0 0xe615001c 0 4>;
593 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
594 <0>, <&extal2_clk>, <&main_div2_clk>,
595 <&extalr_clk>, <0>, <0>;
598 vclk4_clk: vclk4@e6150014 {
599 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
600 reg = <0 0xe6150014 0 4>;
601 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
602 <0>, <&extal2_clk>, <&main_div2_clk>,
603 <&extalr_clk>, <0>, <0>;
606 vclk5_clk: vclk5@e6150034 {
607 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
608 reg = <0 0xe6150034 0 4>;
609 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
610 <0>, <&extal2_clk>, <&main_div2_clk>,
611 <&extalr_clk>, <0>, <0>;
614 fsia_clk: fsia@e6150018 {
615 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
616 reg = <0 0xe6150018 0 4>;
617 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
621 fsib_clk: fsib@e6150090 {
622 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
623 reg = <0 0xe6150090 0 4>;
624 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
628 mp_clk: mp@e6150080 {
629 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
630 reg = <0 0xe6150080 0 4>;
631 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
632 <&extal2_clk>, <&extal2_clk>;
635 m4_clk: m4@e6150098 {
636 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
637 reg = <0 0xe6150098 0 4>;
638 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
641 hsi_clk: hsi@e615026c {
642 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
643 reg = <0 0xe615026c 0 4>;
644 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
645 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
648 spuv_clk: spuv@e6150094 {
649 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
650 reg = <0 0xe6150094 0 4>;
651 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
652 <&extal2_clk>, <&extal2_clk>;
656 /* Fixed factor clocks */
657 main_div2_clk: main_div2 {
658 compatible = "fixed-factor-clock";
659 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
664 pll0_div2_clk: pll0_div2 {
665 compatible = "fixed-factor-clock";
666 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
671 pll1_div2_clk: pll1_div2 {
672 compatible = "fixed-factor-clock";
673 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
678 extal1_div2_clk: extal1_div2 {
679 compatible = "fixed-factor-clock";
680 clocks = <&extal1_clk>;
687 mstp2_clks: mstp2_clks@e6150138 {
688 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
689 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
690 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
691 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
694 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
695 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
696 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
700 "scifa0", "scifa1", "scifb0", "scifb1",
701 "scifb2", "scifb3", "dmac";
703 mstp3_clks: mstp3_clks@e615013c {
704 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
705 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
706 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
707 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
708 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
709 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
710 R8A73A4_CLK_HP>, <&cpg_clocks
711 R8A73A4_CLK_HP>, <&extalr_clk>;
714 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
715 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
716 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
717 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
718 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
722 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
723 "mmcif0", "iic6", "iic7", "iic0", "iic1",
726 mstp4_clks: mstp4_clks@e6150140 {
727 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
728 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
729 clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
731 <&cpg_clocks R8A73A4_CLK_HP>,
732 <&cpg_clocks R8A73A4_CLK_HP>;
735 R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS
736 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
740 "irqc", "intc-sys", "iic5", "iic4", "iic3";
742 mstp5_clks: mstp5_clks@e6150144 {
743 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
744 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
745 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
748 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
755 prr: chipid@ff000044 {
756 compatible = "renesas,prr";
757 reg = <0 0xff000044 0 4>;
760 sysc: system-controller@e6180000 {
761 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
762 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
766 #address-cells = <1>;
768 #power-domain-cells = <0>;
772 #address-cells = <1>;
774 #power-domain-cells = <0>;
778 #power-domain-cells = <0>;
783 #power-domain-cells = <0>;
788 #address-cells = <1>;
790 #power-domain-cells = <0>;
794 #power-domain-cells = <0>;
800 #address-cells = <1>;
802 #power-domain-cells = <0>;
806 #power-domain-cells = <0>;
812 #address-cells = <1>;
814 #power-domain-cells = <0>;
818 #power-domain-cells = <0>;
825 #power-domain-cells = <0>;
830 #power-domain-cells = <0>;
835 #power-domain-cells = <0>;
840 #address-cells = <1>;
842 #power-domain-cells = <0>;
846 #power-domain-cells = <0>;
852 #power-domain-cells = <0>;
857 #power-domain-cells = <0>;
862 #address-cells = <1>;
864 #power-domain-cells = <0>;
868 #power-domain-cells = <0>;
873 #power-domain-cells = <0>;
879 #power-domain-cells = <0>;
884 #address-cells = <1>;
886 #power-domain-cells = <0>;
890 #power-domain-cells = <0>;
895 #power-domain-cells = <0>;