2 * Device Tree Source for the r8a73a4 SoC
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r8a73a4-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 compatible = "renesas,r8a73a4";
18 interrupt-parent = <&gic>;
28 compatible = "arm,cortex-a15";
30 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
31 clock-frequency = <1500000000>;
32 power-domains = <&pd_a2sl>;
33 next-level-cache = <&L2_CA15>;
36 L2_CA15: cache-controller-0 {
38 clocks = <&cpg_clocks R8A73A4_CLK_Z>;
39 power-domains = <&pd_a3sm>;
44 L2_CA7: cache-controller-1 {
46 clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
47 power-domains = <&pd_a3km>;
54 compatible = "arm,coresight-etm3x";
55 power-domains = <&pd_d4>;
59 compatible = "arm,armv7-timer";
60 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
61 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
66 dbsc1: memory-controller@e6790000 {
67 compatible = "renesas,dbsc-r8a73a4";
68 reg = <0 0xe6790000 0 0x10000>;
69 power-domains = <&pd_a3bc>;
72 dbsc2: memory-controller@e67a0000 {
73 compatible = "renesas,dbsc-r8a73a4";
74 reg = <0 0xe67a0000 0 0x10000>;
75 power-domains = <&pd_a3bc>;
78 dmac: dma-multiplexer {
79 compatible = "renesas,shdma-mux";
87 dma0: dma-controller@e6700020 {
88 compatible = "renesas,shdma-r8a73a4";
89 reg = <0 0xe6700020 0 0x89e0>;
90 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
91 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
92 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
93 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
94 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
95 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
96 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
97 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
98 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
99 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
100 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
101 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
102 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
103 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
104 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
105 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
106 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
107 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
108 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
109 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
110 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
111 interrupt-names = "error",
112 "ch0", "ch1", "ch2", "ch3",
113 "ch4", "ch5", "ch6", "ch7",
114 "ch8", "ch9", "ch10", "ch11",
115 "ch12", "ch13", "ch14", "ch15",
116 "ch16", "ch17", "ch18", "ch19";
117 clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
118 power-domains = <&pd_a3sp>;
123 #address-cells = <1>;
125 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
126 reg = <0 0xe60b0000 0 0x428>;
127 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
129 power-domains = <&pd_a3sp>;
134 cmt1: timer@e6130000 {
135 compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
136 reg = <0 0xe6130000 0 0x1004>;
137 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
140 power-domains = <&pd_c5>;
142 renesas,channels-mask = <0xff>;
147 irqc0: interrupt-controller@e61c0000 {
148 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
149 #interrupt-cells = <2>;
150 interrupt-controller;
151 reg = <0 0xe61c0000 0 0x200>;
152 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
185 power-domains = <&pd_c4>;
188 irqc1: interrupt-controller@e61c0200 {
189 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
190 #interrupt-cells = <2>;
191 interrupt-controller;
192 reg = <0 0xe61c0200 0 0x200>;
193 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
220 power-domains = <&pd_c4>;
223 pfc: pin-controller@e6050000 {
224 compatible = "renesas,pfc-r8a73a4";
225 reg = <0 0xe6050000 0 0x9000>;
229 <&pfc 0 0 31>, <&pfc 32 32 9>,
230 <&pfc 64 64 22>, <&pfc 96 96 31>,
231 <&pfc 128 128 7>, <&pfc 160 160 19>,
232 <&pfc 192 192 31>, <&pfc 224 224 27>,
233 <&pfc 256 256 28>, <&pfc 288 288 21>,
235 interrupts-extended =
236 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
237 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
238 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
239 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
240 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
241 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
242 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
243 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
244 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
245 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
246 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
247 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
248 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
249 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
250 <&irqc1 24 0>, <&irqc1 25 0>;
251 power-domains = <&pd_c5>;
255 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
256 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
257 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
258 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
260 power-domains = <&pd_c5>;
264 #address-cells = <1>;
266 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
267 reg = <0 0xe6500000 0 0x428>;
268 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
270 power-domains = <&pd_a3sp>;
275 #address-cells = <1>;
277 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
278 reg = <0 0xe6510000 0 0x428>;
279 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
281 power-domains = <&pd_a3sp>;
286 #address-cells = <1>;
288 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
289 reg = <0 0xe6520000 0 0x428>;
290 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
292 power-domains = <&pd_a3sp>;
297 #address-cells = <1>;
299 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
300 reg = <0 0xe6530000 0 0x428>;
301 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
303 power-domains = <&pd_a3sp>;
308 #address-cells = <1>;
310 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
311 reg = <0 0xe6540000 0 0x428>;
312 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
314 power-domains = <&pd_a3sp>;
319 #address-cells = <1>;
321 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
322 reg = <0 0xe6550000 0 0x428>;
323 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
325 power-domains = <&pd_a3sp>;
330 #address-cells = <1>;
332 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
333 reg = <0 0xe6560000 0 0x428>;
334 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
336 power-domains = <&pd_a3sp>;
341 #address-cells = <1>;
343 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
344 reg = <0 0xe6570000 0 0x428>;
345 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
346 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
347 power-domains = <&pd_a3sp>;
351 scifb0: serial@e6c20000 {
352 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
353 reg = <0 0xe6c20000 0 0x100>;
354 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
357 power-domains = <&pd_a3sp>;
361 scifb1: serial@e6c30000 {
362 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
363 reg = <0 0xe6c30000 0 0x100>;
364 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
367 power-domains = <&pd_a3sp>;
371 scifa0: serial@e6c40000 {
372 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
373 reg = <0 0xe6c40000 0 0x100>;
374 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
377 power-domains = <&pd_a3sp>;
381 scifa1: serial@e6c50000 {
382 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
383 reg = <0 0xe6c50000 0 0x100>;
384 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
387 power-domains = <&pd_a3sp>;
391 scifb2: serial@e6ce0000 {
392 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
393 reg = <0 0xe6ce0000 0 0x100>;
394 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
397 power-domains = <&pd_a3sp>;
401 scifb3: serial@e6cf0000 {
402 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
403 reg = <0 0xe6cf0000 0 0x100>;
404 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
407 power-domains = <&pd_c4>;
412 compatible = "renesas,sdhi-r8a73a4";
413 reg = <0 0xee100000 0 0x100>;
414 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
416 power-domains = <&pd_a3sp>;
422 compatible = "renesas,sdhi-r8a73a4";
423 reg = <0 0xee120000 0 0x100>;
424 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
426 power-domains = <&pd_a3sp>;
432 compatible = "renesas,sdhi-r8a73a4";
433 reg = <0 0xee140000 0 0x100>;
434 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
436 power-domains = <&pd_a3sp>;
441 mmcif0: mmc@ee200000 {
442 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
443 reg = <0 0xee200000 0 0x80>;
444 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
446 power-domains = <&pd_a3sp>;
451 mmcif1: mmc@ee220000 {
452 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
453 reg = <0 0xee220000 0 0x80>;
454 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
456 power-domains = <&pd_a3sp>;
461 gic: interrupt-controller@f1001000 {
462 compatible = "arm,gic-400";
463 #interrupt-cells = <3>;
464 #address-cells = <0>;
465 interrupt-controller;
466 reg = <0 0xf1001000 0 0x1000>,
467 <0 0xf1002000 0 0x2000>,
468 <0 0xf1004000 0 0x2000>,
469 <0 0xf1006000 0 0x2000>;
470 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
471 clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>;
473 power-domains = <&pd_c4>;
477 compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
479 #address-cells = <1>;
481 ranges = <0 0 0 0x20000000>;
482 reg = <0 0xfec10000 0 0x400>;
484 power-domains = <&pd_c4>;
488 #address-cells = <2>;
492 /* External root clocks */
494 compatible = "fixed-clock";
496 clock-frequency = <32768>;
499 compatible = "fixed-clock";
501 clock-frequency = <25000000>;
504 compatible = "fixed-clock";
506 clock-frequency = <48000000>;
509 compatible = "fixed-clock";
511 /* This value must be overridden by the board. */
512 clock-frequency = <0>;
515 compatible = "fixed-clock";
517 /* This value must be overridden by the board. */
518 clock-frequency = <0>;
521 /* Special CPG clocks */
522 cpg_clocks: cpg_clocks@e6150000 {
523 compatible = "renesas,r8a73a4-cpg-clocks";
524 reg = <0 0xe6150000 0 0x10000>;
525 clocks = <&extal1_clk>, <&extal2_clk>;
527 clock-output-names = "main", "pll0", "pll1", "pll2",
528 "pll2s", "pll2h", "z", "z2",
529 "i", "m3", "b", "m1", "m2",
533 /* Variable factor clocks (DIV6) */
534 zb_clk: zb_clk@e6150010 {
535 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
536 reg = <0 0xe6150010 0 4>;
537 clocks = <&pll1_div2_clk>, <0>,
538 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
540 clock-output-names = "zb";
542 sdhi0_clk: sdhi0ck@e6150074 {
543 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
544 reg = <0 0xe6150074 0 4>;
545 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
549 sdhi1_clk: sdhi1ck@e6150078 {
550 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
551 reg = <0 0xe6150078 0 4>;
552 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
556 sdhi2_clk: sdhi2ck@e615007c {
557 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
558 reg = <0 0xe615007c 0 4>;
559 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
563 mmc0_clk: mmc0@e6150240 {
564 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
565 reg = <0 0xe6150240 0 4>;
566 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
570 mmc1_clk: mmc1@e6150244 {
571 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
572 reg = <0 0xe6150244 0 4>;
573 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
577 vclk1_clk: vclk1@e6150008 {
578 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
579 reg = <0 0xe6150008 0 4>;
580 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
581 <0>, <&extal2_clk>, <&main_div2_clk>,
582 <&extalr_clk>, <0>, <0>;
585 vclk2_clk: vclk2@e615000c {
586 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
587 reg = <0 0xe615000c 0 4>;
588 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
589 <0>, <&extal2_clk>, <&main_div2_clk>,
590 <&extalr_clk>, <0>, <0>;
593 vclk3_clk: vclk3@e615001c {
594 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
595 reg = <0 0xe615001c 0 4>;
596 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
597 <0>, <&extal2_clk>, <&main_div2_clk>,
598 <&extalr_clk>, <0>, <0>;
601 vclk4_clk: vclk4@e6150014 {
602 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
603 reg = <0 0xe6150014 0 4>;
604 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
605 <0>, <&extal2_clk>, <&main_div2_clk>,
606 <&extalr_clk>, <0>, <0>;
609 vclk5_clk: vclk5@e6150034 {
610 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
611 reg = <0 0xe6150034 0 4>;
612 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
613 <0>, <&extal2_clk>, <&main_div2_clk>,
614 <&extalr_clk>, <0>, <0>;
617 fsia_clk: fsia@e6150018 {
618 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
619 reg = <0 0xe6150018 0 4>;
620 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
624 fsib_clk: fsib@e6150090 {
625 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
626 reg = <0 0xe6150090 0 4>;
627 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
631 mp_clk: mp@e6150080 {
632 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
633 reg = <0 0xe6150080 0 4>;
634 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
635 <&extal2_clk>, <&extal2_clk>;
638 m4_clk: m4@e6150098 {
639 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
640 reg = <0 0xe6150098 0 4>;
641 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
644 hsi_clk: hsi@e615026c {
645 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
646 reg = <0 0xe615026c 0 4>;
647 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
648 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
651 spuv_clk: spuv@e6150094 {
652 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
653 reg = <0 0xe6150094 0 4>;
654 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
655 <&extal2_clk>, <&extal2_clk>;
659 /* Fixed factor clocks */
660 main_div2_clk: main_div2 {
661 compatible = "fixed-factor-clock";
662 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
667 pll0_div2_clk: pll0_div2 {
668 compatible = "fixed-factor-clock";
669 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
674 pll1_div2_clk: pll1_div2 {
675 compatible = "fixed-factor-clock";
676 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
681 extal1_div2_clk: extal1_div2 {
682 compatible = "fixed-factor-clock";
683 clocks = <&extal1_clk>;
690 mstp2_clks: mstp2_clks@e6150138 {
691 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
692 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
693 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
694 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
697 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
698 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
699 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
703 "scifa0", "scifa1", "scifb0", "scifb1",
704 "scifb2", "scifb3", "dmac";
706 mstp3_clks: mstp3_clks@e615013c {
707 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
708 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
709 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
710 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
711 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
712 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
713 R8A73A4_CLK_HP>, <&cpg_clocks
714 R8A73A4_CLK_HP>, <&extalr_clk>;
717 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
718 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
719 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
720 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
721 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
725 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
726 "mmcif0", "iic6", "iic7", "iic0", "iic1",
729 mstp4_clks: mstp4_clks@e6150140 {
730 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
731 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
732 clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>,
734 <&cpg_clocks R8A73A4_CLK_HP>,
735 <&cpg_clocks R8A73A4_CLK_HP>;
738 R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS
739 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
743 "irqc", "intc-sys", "iic5", "iic4", "iic3";
745 mstp5_clks: mstp5_clks@e6150144 {
746 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
747 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
748 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
751 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
758 prr: chipid@ff000044 {
759 compatible = "renesas,prr";
760 reg = <0 0xff000044 0 4>;
763 sysc: system-controller@e6180000 {
764 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
765 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>;
769 #address-cells = <1>;
771 #power-domain-cells = <0>;
775 #address-cells = <1>;
777 #power-domain-cells = <0>;
781 #power-domain-cells = <0>;
786 #power-domain-cells = <0>;
791 #address-cells = <1>;
793 #power-domain-cells = <0>;
797 #power-domain-cells = <0>;
803 #address-cells = <1>;
805 #power-domain-cells = <0>;
809 #power-domain-cells = <0>;
815 #address-cells = <1>;
817 #power-domain-cells = <0>;
821 #power-domain-cells = <0>;
828 #power-domain-cells = <0>;
833 #power-domain-cells = <0>;
838 #power-domain-cells = <0>;
843 #address-cells = <1>;
845 #power-domain-cells = <0>;
849 #power-domain-cells = <0>;
855 #power-domain-cells = <0>;
860 #power-domain-cells = <0>;
865 #address-cells = <1>;
867 #power-domain-cells = <0>;
871 #power-domain-cells = <0>;
876 #power-domain-cells = <0>;
882 #power-domain-cells = <0>;
887 #address-cells = <1>;
889 #power-domain-cells = <0>;
893 #power-domain-cells = <0>;
898 #power-domain-cells = <0>;