1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the RZA2MEVB board
5 * Copyright (C) 2018 Renesas Electronics
10 #include "r7s9210.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
16 compatible = "renesas,rza2mevb", "renesas,r7s9210";
23 bootargs = "ignore_loglevel";
24 stdout-path = "serial0:115200n8";
28 device_type = "memory";
29 reg = <0x40000000 0x00800000>; /* HyperRAM */
38 compatible = "gpio-leds";
41 gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
44 gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>;
51 clock-frequency = <24000000>; /* 24MHz */
56 clock-frequency = <32768>;
62 pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
63 <RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
67 pinmux = <RZA2_PINMUX(PORTE, 0, 7)>, /* REF50CK0 */
68 <RZA2_PINMUX(PORT6, 1, 7)>, /* RMMI0_TXDEN */
69 <RZA2_PINMUX(PORT6, 2, 7)>, /* RMII0_TXD0 */
70 <RZA2_PINMUX(PORT6, 3, 7)>, /* RMII0_TXD1 */
71 <RZA2_PINMUX(PORTE, 4, 7)>, /* RMII0_CRSDV */
72 <RZA2_PINMUX(PORTE, 1, 7)>, /* RMII0_RXD0 */
73 <RZA2_PINMUX(PORTE, 2, 7)>, /* RMII0_RXD1 */
74 <RZA2_PINMUX(PORTE, 3, 7)>, /* RMII0_RXER */
75 <RZA2_PINMUX(PORTE, 5, 1)>, /* ET0_MDC */
76 <RZA2_PINMUX(PORTE, 6, 1)>, /* ET0_MDIO */
77 <RZA2_PINMUX(PORTL, 0, 5)>; /* IRQ4 */
81 pinmux = <RZA2_PINMUX(PORTK, 3, 7)>, /* REF50CK1 */
82 <RZA2_PINMUX(PORTK, 0, 7)>, /* RMMI1_TXDEN */
83 <RZA2_PINMUX(PORTK, 1, 7)>, /* RMII1_TXD0 */
84 <RZA2_PINMUX(PORTK, 2, 7)>, /* RMII1_TXD1 */
85 <RZA2_PINMUX(PORT3, 2, 7)>, /* RMII1_CRSDV */
86 <RZA2_PINMUX(PORTK, 4, 7)>, /* RMII1_RXD0 */
87 <RZA2_PINMUX(PORT3, 5, 7)>, /* RMII1_RXD1 */
88 <RZA2_PINMUX(PORT3, 1, 7)>, /* RMII1_RXER */
89 <RZA2_PINMUX(PORT3, 3, 1)>, /* ET1_MDC */
90 <RZA2_PINMUX(PORT3, 4, 1)>, /* ET1_MDIO */
91 <RZA2_PINMUX(PORTL, 1, 5)>; /* IRQ5 */
95 pinmux = <RZA2_PINMUX(PORT5, 0, 3)>, /* SD0_CD */
96 <RZA2_PINMUX(PORT5, 1, 3)>; /* SD0_WP */
100 pinmux = <RZA2_PINMUX(PORT5, 4, 3)>, /* SD1_CD */
101 <RZA2_PINMUX(PORT5, 5, 3)>; /* SD1_WP */
105 /* High resolution System tick timers */
116 pinctrl-names = "default";
117 pinctrl-0 = <&scif4_pins>;
123 pinctrl-names = "default";
124 pinctrl-0 = <ð0_pins>;
126 renesas,no-ether-link;
127 phy-handle = <&phy0>;
128 phy0: ethernet-phy@0 {
134 pinctrl-names = "default";
135 pinctrl-0 = <ð1_pins>;
137 renesas,no-ether-link;
138 phy-handle = <&phy1>;
139 phy1: ethernet-phy@1 {
145 pinctrl-names = "default";
146 pinctrl-0 = <&sdhi0_pins>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&sdhi1_pins>;