2 * Device Tree Source for the r7s72100 SoC
4 * Copyright (C) 2013-14 Renesas Solutions Corp.
5 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r7s72100-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 compatible = "renesas,r7s72100";
18 interrupt-parent = <&gic>;
42 compatible = "fixed-clock";
43 /* If clk present, value must be set by board */
44 clock-frequency = <0>;
49 compatible = "fixed-clock";
50 /* If clk present, value must be set by board */
51 clock-frequency = <0>;
56 compatible = "fixed-clock";
57 /* If clk present, value must be set by board to 32678 */
58 clock-frequency = <0>;
63 compatible = "fixed-clock";
64 /* If clk present, value must be set by board to 4000000 */
65 clock-frequency = <0>;
68 /* Fixed factor clocks */
71 compatible = "fixed-factor-clock";
72 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
78 compatible = "fixed-factor-clock";
79 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
85 compatible = "fixed-factor-clock";
86 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
91 /* Special CPG clocks */
92 cpg_clocks: cpg_clocks@fcfe0000 {
94 compatible = "renesas,r7s72100-cpg-clocks",
95 "renesas,rz-cpg-clocks";
96 reg = <0xfcfe0000 0x18>;
97 clocks = <&extal_clk>, <&usb_x1_clk>;
98 clock-output-names = "pll", "i", "g";
99 #power-domain-cells = <0>;
103 mstp3_clks: mstp3_clks@fcfe0420 {
105 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
106 reg = <0xfcfe0420 4>;
108 clock-indices = <R7S72100_CLK_MTU2>;
109 clock-output-names = "mtu2";
112 mstp4_clks: mstp4_clks@fcfe0424 {
114 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
115 reg = <0xfcfe0424 4>;
116 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
117 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
119 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
120 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
122 clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
125 mstp5_clks: mstp5_clks@fcfe0428 {
127 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
128 reg = <0xfcfe0428 4>;
129 clocks = <&p0_clk>, <&p0_clk>;
130 clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
131 clock-output-names = "ostm0", "ostm1";
134 mstp6_clks: mstp6_clks@fcfe042c {
136 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
137 reg = <0xfcfe042c 4>;
139 clock-indices = <R7S72100_CLK_RTC>;
140 clock-output-names = "rtc";
143 mstp7_clks: mstp7_clks@fcfe0430 {
145 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
146 reg = <0xfcfe0430 4>;
147 clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
148 clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
149 clock-output-names = "ether", "usb0", "usb1";
152 mstp8_clks: mstp8_clks@fcfe0434 {
154 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
155 reg = <0xfcfe0434 4>;
157 clock-indices = <R7S72100_CLK_MMCIF>;
158 clock-output-names = "mmcif";
161 mstp9_clks: mstp9_clks@fcfe0438 {
163 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
164 reg = <0xfcfe0438 4>;
165 clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
167 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
169 clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
172 mstp10_clks: mstp10_clks@fcfe043c {
174 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
175 reg = <0xfcfe043c 4>;
176 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
179 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
182 clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
184 mstp12_clks: mstp12_clks@fcfe0444 {
186 compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
187 reg = <0xfcfe0444 4>;
188 clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
190 R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
191 R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
193 clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
198 #address-cells = <1>;
203 compatible = "arm,cortex-a9";
205 clock-frequency = <400000000>;
206 next-level-cache = <&L2>;
210 scif0: serial@e8007000 {
211 compatible = "renesas,scif-r7s72100", "renesas,scif";
212 reg = <0xe8007000 64>;
213 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
219 power-domains = <&cpg_clocks>;
223 scif1: serial@e8007800 {
224 compatible = "renesas,scif-r7s72100", "renesas,scif";
225 reg = <0xe8007800 64>;
226 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
232 power-domains = <&cpg_clocks>;
236 scif2: serial@e8008000 {
237 compatible = "renesas,scif-r7s72100", "renesas,scif";
238 reg = <0xe8008000 64>;
239 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
245 power-domains = <&cpg_clocks>;
249 scif3: serial@e8008800 {
250 compatible = "renesas,scif-r7s72100", "renesas,scif";
251 reg = <0xe8008800 64>;
252 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
258 power-domains = <&cpg_clocks>;
262 scif4: serial@e8009000 {
263 compatible = "renesas,scif-r7s72100", "renesas,scif";
264 reg = <0xe8009000 64>;
265 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
271 power-domains = <&cpg_clocks>;
275 scif5: serial@e8009800 {
276 compatible = "renesas,scif-r7s72100", "renesas,scif";
277 reg = <0xe8009800 64>;
278 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
284 power-domains = <&cpg_clocks>;
288 scif6: serial@e800a000 {
289 compatible = "renesas,scif-r7s72100", "renesas,scif";
290 reg = <0xe800a000 64>;
291 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
297 power-domains = <&cpg_clocks>;
301 scif7: serial@e800a800 {
302 compatible = "renesas,scif-r7s72100", "renesas,scif";
303 reg = <0xe800a800 64>;
304 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
310 power-domains = <&cpg_clocks>;
315 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
316 reg = <0xe800c800 0x24>;
317 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
320 interrupt-names = "error", "rx", "tx";
321 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
322 power-domains = <&cpg_clocks>;
324 #address-cells = <1>;
330 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
331 reg = <0xe800d000 0x24>;
332 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
335 interrupt-names = "error", "rx", "tx";
336 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
337 power-domains = <&cpg_clocks>;
339 #address-cells = <1>;
345 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
346 reg = <0xe800d800 0x24>;
347 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-names = "error", "rx", "tx";
351 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
352 power-domains = <&cpg_clocks>;
354 #address-cells = <1>;
360 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
361 reg = <0xe800e000 0x24>;
362 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
365 interrupt-names = "error", "rx", "tx";
366 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
367 power-domains = <&cpg_clocks>;
369 #address-cells = <1>;
375 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
376 reg = <0xe800e800 0x24>;
377 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
380 interrupt-names = "error", "rx", "tx";
381 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
382 power-domains = <&cpg_clocks>;
384 #address-cells = <1>;
389 gic: interrupt-controller@e8201000 {
390 compatible = "arm,pl390";
391 #interrupt-cells = <3>;
392 #address-cells = <0>;
393 interrupt-controller;
394 reg = <0xe8201000 0x1000>,
398 L2: cache-controller@3ffff000 {
399 compatible = "arm,pl310-cache";
400 reg = <0x3ffff000 0x1000>;
401 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
402 arm,early-bresp-disable;
403 arm,full-line-zero-disable;
408 wdt: watchdog@fcfe0000 {
409 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
410 reg = <0xfcfe0000 0x6>;
411 interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
416 #address-cells = <1>;
418 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
419 reg = <0xfcfee000 0x44>;
420 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
422 <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
423 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
429 clock-frequency = <100000>;
430 power-domains = <&cpg_clocks>;
435 #address-cells = <1>;
437 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
438 reg = <0xfcfee400 0x44>;
439 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
441 <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
442 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
448 clock-frequency = <100000>;
449 power-domains = <&cpg_clocks>;
454 #address-cells = <1>;
456 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
457 reg = <0xfcfee800 0x44>;
458 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
460 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
461 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
467 clock-frequency = <100000>;
468 power-domains = <&cpg_clocks>;
473 #address-cells = <1>;
475 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
476 reg = <0xfcfeec00 0x44>;
477 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
479 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
480 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
486 clock-frequency = <100000>;
487 power-domains = <&cpg_clocks>;
491 mtu2: timer@fcff0000 {
492 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
493 reg = <0xfcff0000 0x400>;
494 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
495 interrupt-names = "tgi0a";
496 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
498 power-domains = <&cpg_clocks>;
502 ether: ethernet@e8203000 {
503 compatible = "renesas,ether-r7s72100";
504 reg = <0xe8203000 0x800>,
506 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
508 power-domains = <&cpg_clocks>;
510 #address-cells = <1>;
515 mmcif: mmc@e804c800 {
516 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
517 reg = <0xe804c800 0x80>;
518 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
519 GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
520 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
522 power-domains = <&cpg_clocks>;
529 compatible = "renesas,sdhi-r7s72100";
530 reg = <0xe804e000 0x100>;
531 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
532 GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
533 GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
536 <&mstp12_clks R7S72100_CLK_SDHI01>;
537 clock-names = "core", "cd";
538 power-domains = <&cpg_clocks>;
545 compatible = "renesas,sdhi-r7s72100";
546 reg = <0xe804e800 0x100>;
547 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
548 GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
549 GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
552 <&mstp12_clks R7S72100_CLK_SDHI11>;
553 clock-names = "core", "cd";
554 power-domains = <&cpg_clocks>;
560 ostm0: timer@fcfec000 {
561 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
562 reg = <0xfcfec000 0x30>;
563 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
564 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
565 power-domains = <&cpg_clocks>;
569 ostm1: timer@fcfec400 {
570 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
571 reg = <0xfcfec400 0x30>;
572 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
573 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
574 power-domains = <&cpg_clocks>;
579 compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
580 reg = <0xfcff1000 0x2e>;
581 interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING
582 GIC_SPI 277 IRQ_TYPE_EDGE_RISING
583 GIC_SPI 278 IRQ_TYPE_EDGE_RISING>;
584 interrupt-names = "alarm", "period", "carry";
585 clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
586 <&rtc_x3_clk>, <&extal_clk>;
587 clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
588 power-domains = <&cpg_clocks>;