arch/arm/boot/dts/r7s72100.dtsi

   1 /*
   2  * Device Tree Source for the r7s72100 SoC
   3  *
   4  * Copyright (C) 2013-14 Renesas Solutions Corp.
   5  * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r7s72100-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r7s72100";
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         aliases {
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26                 spi0 = &spi0;
  27                 spi1 = &spi1;
  28                 spi2 = &spi2;
  29                 spi3 = &spi3;
  30                 spi4 = &spi4;
  31         };
  32
  33         /* Fixed factor clocks */
  34         b_clk: b {
  35                 #clock-cells = <0>;
  36                 compatible = "fixed-factor-clock";
  37                 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  38                 clock-mult = <1>;
  39                 clock-div = <3>;
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a9";
  49                         reg = <0>;
  50                         clock-frequency = <400000000>;
  51                         clocks = <&cpg_clocks R7S72100_CLK_I>;
  52                         next-level-cache = <&L2>;
  53                 };
  54         };
  55
  56         /* External clocks */
  57         extal_clk: extal {
  58                 #clock-cells = <0>;
  59                 compatible = "fixed-clock";
  60                 /* If clk present, value must be set by board */
  61                 clock-frequency = <0>;
  62         };
  63
  64         p0_clk: p0 {
  65                 #clock-cells = <0>;
  66                 compatible = "fixed-factor-clock";
  67                 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  68                 clock-mult = <1>;
  69                 clock-div = <12>;
  70         };
  71
  72         p1_clk: p1 {
  73                 #clock-cells = <0>;
  74                 compatible = "fixed-factor-clock";
  75                 clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  76                 clock-mult = <1>;
  77                 clock-div = <6>;
  78         };
  79
  80         rtc_x1_clk: rtc_x1 {
  81                 #clock-cells = <0>;
  82                 compatible = "fixed-clock";
  83                 /* If clk present, value must be set by board to 32678 */
  84                 clock-frequency = <0>;
  85         };
  86
  87         rtc_x3_clk: rtc_x3 {
  88                 #clock-cells = <0>;
  89                 compatible = "fixed-clock";
  90                 /* If clk present, value must be set by board to 4000000 */
  91                 clock-frequency = <0>;
  92         };
  93
  94         soc {
  95                 compatible = "simple-bus";
  96                 interrupt-parent = <&gic>;
  97
  98                 #address-cells = <1>;
  99                 #size-cells = <1>;
 100                 ranges;
 101
 102                 L2: cache-controller@3ffff000 {
 103                         compatible = "arm,pl310-cache";
 104                         reg = <0x3ffff000 0x1000>;
 105                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 106                         arm,early-bresp-disable;
 107                         arm,full-line-zero-disable;
 108                         cache-unified;
 109                         cache-level = <2>;
 110                 };
 111
 112                 scif0: serial@e8007000 {
 113                         compatible = "renesas,scif-r7s72100", "renesas,scif";
 114                         reg = <0xe8007000 64>;
 115                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 116                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 117                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 118                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 119                         clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
 120                         clock-names = "fck";
 121                         power-domains = <&cpg_clocks>;
 122                         status = "disabled";
 123                 };
 124
 125                 scif1: serial@e8007800 {
 126                         compatible = "renesas,scif-r7s72100", "renesas,scif";
 127                         reg = <0xe8007800 64>;
 128                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
 129                                      <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
 130                                      <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 131                                      <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 132                         clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
 133                         clock-names = "fck";
 134                         power-domains = <&cpg_clocks>;
 135                         status = "disabled";
 136                 };
 137
 138                 scif2: serial@e8008000 {
 139                         compatible = "renesas,scif-r7s72100", "renesas,scif";
 140                         reg = <0xe8008000 64>;
 141                         interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 142                                      <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 143                                      <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
 144                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 145                         clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
 146                         clock-names = "fck";
 147                         power-domains = <&cpg_clocks>;
 148                         status = "disabled";
 149                 };
 150
 151                 scif3: serial@e8008800 {
 152                         compatible = "renesas,scif-r7s72100", "renesas,scif";
 153                         reg = <0xe8008800 64>;
 154                         interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 155                                      <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 156                                      <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
 157                                      <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 158                         clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
 159                         clock-names = "fck";
 160                         power-domains = <&cpg_clocks>;
 161                         status = "disabled";
 162                 };
 163
 164                 scif4: serial@e8009000 {
 165                         compatible = "renesas,scif-r7s72100", "renesas,scif";
 166                         reg = <0xe8009000 64>;
 167                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
 168                                      <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 169                                      <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 170                                      <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 171                         clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
 172                         clock-names = "fck";
 173                         power-domains = <&cpg_clocks>;
 174                         status = "disabled";
 175                 };
 176
 177                 scif5: serial@e8009800 {
 178                         compatible = "renesas,scif-r7s72100", "renesas,scif";
 179                         reg = <0xe8009800 64>;
 180                         interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 181                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 182                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 183                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 184                         clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
 185                         clock-names = "fck";
 186                         power-domains = <&cpg_clocks>;
 187                         status = "disabled";
 188                 };
 189
 190                 scif6: serial@e800a000 {
 191                         compatible = "renesas,scif-r7s72100", "renesas,scif";
 192                         reg = <0xe800a000 64>;
 193                         interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 194                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 195                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
 196                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
 197                         clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
 198                         clock-names = "fck";
 199                         power-domains = <&cpg_clocks>;
 200                         status = "disabled";
 201                 };
 202
 203                 scif7: serial@e800a800 {
 204                         compatible = "renesas,scif-r7s72100", "renesas,scif";
 205                         reg = <0xe800a800 64>;
 206                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 207                                      <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 208                                      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
 209                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
 210                         clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
 211                         clock-names = "fck";
 212                         power-domains = <&cpg_clocks>;
 213                         status = "disabled";
 214                 };
 215
 216                 spi0: spi@e800c800 {
 217                         compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 218                         reg = <0xe800c800 0x24>;
 219                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 220                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 221                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 222                         interrupt-names = "error", "rx", "tx";
 223                         clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
 224                         power-domains = <&cpg_clocks>;
 225                         num-cs = <1>;
 226                         #address-cells = <1>;
 227                         #size-cells = <0>;
 228                         status = "disabled";
 229                 };
 230
 231                 spi1: spi@e800d000 {
 232                         compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 233                         reg = <0xe800d000 0x24>;
 234                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 235                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 236                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 237                         interrupt-names = "error", "rx", "tx";
 238                         clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
 239                         power-domains = <&cpg_clocks>;
 240                         num-cs = <1>;
 241                         #address-cells = <1>;
 242                         #size-cells = <0>;
 243                         status = "disabled";
 244                 };
 245
 246                 spi2: spi@e800d800 {
 247                         compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 248                         reg = <0xe800d800 0x24>;
 249                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 250                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 251                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 252                         interrupt-names = "error", "rx", "tx";
 253                         clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
 254                         power-domains = <&cpg_clocks>;
 255                         num-cs = <1>;
 256                         #address-cells = <1>;
 257                         #size-cells = <0>;
 258                         status = "disabled";
 259                 };
 260
 261                 spi3: spi@e800e000 {
 262                         compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 263                         reg = <0xe800e000 0x24>;
 264                         interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 265                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 266                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 267                         interrupt-names = "error", "rx", "tx";
 268                         clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
 269                         power-domains = <&cpg_clocks>;
 270                         num-cs = <1>;
 271                         #address-cells = <1>;
 272                         #size-cells = <0>;
 273                         status = "disabled";
 274                 };
 275
 276                 spi4: spi@e800e800 {
 277                         compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 278                         reg = <0xe800e800 0x24>;
 279                         interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 280                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 281                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 282                         interrupt-names = "error", "rx", "tx";
 283                         clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
 284                         power-domains = <&cpg_clocks>;
 285                         num-cs = <1>;
 286                         #address-cells = <1>;
 287                         #size-cells = <0>;
 288                         status = "disabled";
 289                 };
 290
 291                 usbhs0: usb@e8010000 {
 292                         compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
 293                         reg = <0xe8010000 0x1a0>;
 294                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 295                         clocks = <&mstp7_clks R7S72100_CLK_USB0>;
 296                         renesas,buswait = <4>;
 297                         power-domains = <&cpg_clocks>;
 298                         status = "disabled";
 299                 };
 300
 301                 usbhs1: usb@e8207000 {
 302                         compatible = "renesas,usbhs-r7s72100", "renesas,rza1-usbhs";
 303                         reg = <0xe8207000 0x1a0>;
 304                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 305                         clocks = <&mstp7_clks R7S72100_CLK_USB1>;
 306                         renesas,buswait = <4>;
 307                         power-domains = <&cpg_clocks>;
 308                         status = "disabled";
 309                 };
 310
 311                 mmcif: mmc@e804c800 {
 312                         compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
 313                         reg = <0xe804c800 0x80>;
 314                         interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
 315                                       GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
 316                                       GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 317                         clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
 318                         power-domains = <&cpg_clocks>;
 319                         reg-io-width = <4>;
 320                         bus-width = <8>;
 321                         status = "disabled";
 322                 };
 323
 324                 sdhi0: sd@e804e000 {
 325                         compatible = "renesas,sdhi-r7s72100";
 326                         reg = <0xe804e000 0x100>;
 327                         interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
 328                                       GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
 329                                       GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 330
 331                         clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
 332                                  <&mstp12_clks R7S72100_CLK_SDHI01>;
 333                         clock-names = "core", "cd";
 334                         power-domains = <&cpg_clocks>;
 335                         cap-sd-highspeed;
 336                         cap-sdio-irq;
 337                         status = "disabled";
 338                 };
 339
 340                 sdhi1: sd@e804e800 {
 341                         compatible = "renesas,sdhi-r7s72100";
 342                         reg = <0xe804e800 0x100>;
 343                         interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
 344                                       GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
 345                                       GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
 346
 347                         clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
 348                                  <&mstp12_clks R7S72100_CLK_SDHI11>;
 349                         clock-names = "core", "cd";
 350                         power-domains = <&cpg_clocks>;
 351                         cap-sd-highspeed;
 352                         cap-sdio-irq;
 353                         status = "disabled";
 354                 };
 355
 356                 gic: interrupt-controller@e8201000 {
 357                         compatible = "arm,pl390";
 358                         #interrupt-cells = <3>;
 359                         #address-cells = <0>;
 360                         interrupt-controller;
 361                         reg = <0xe8201000 0x1000>,
 362                                 <0xe8202000 0x1000>;
 363                 };
 364
 365                 ether: ethernet@e8203000 {
 366                         compatible = "renesas,ether-r7s72100";
 367                         reg = <0xe8203000 0x800>,
 368                               <0xe8204800 0x200>;
 369                         interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
 370                         clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
 371                         power-domains = <&cpg_clocks>;
 372                         phy-mode = "mii";
 373                         #address-cells = <1>;
 374                         #size-cells = <0>;
 375                         status = "disabled";
 376                 };
 377
 378                 wdt: watchdog@fcfe0000 {
 379                         compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
 380                         reg = <0xfcfe0000 0x6>;
 381                         interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
 382                         clocks = <&p0_clk>;
 383                 };
 384
 385                 /* Special CPG clocks */
 386                 cpg_clocks: cpg_clocks@fcfe0000 {
 387                         #clock-cells = <1>;
 388                         compatible = "renesas,r7s72100-cpg-clocks",
 389                                      "renesas,rz-cpg-clocks";
 390                         reg = <0xfcfe0000 0x18>;
 391                         clocks = <&extal_clk>, <&usb_x1_clk>;
 392                         clock-output-names = "pll", "i", "g";
 393                         #power-domain-cells = <0>;
 394                 };
 395
 396                 /* MSTP clocks */
 397                 mstp3_clks: mstp3_clks@fcfe0420 {
 398                         #clock-cells = <1>;
 399                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 400                         reg = <0xfcfe0420 4>;
 401                         clocks = <&p0_clk>;
 402                         clock-indices = <R7S72100_CLK_MTU2>;
 403                         clock-output-names = "mtu2";
 404                 };
 405
 406                 mstp4_clks: mstp4_clks@fcfe0424 {
 407                         #clock-cells = <1>;
 408                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 409                         reg = <0xfcfe0424 4>;
 410                         clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
 411                                  <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
 412                         clock-indices = <
 413                                 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
 414                                 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
 415                         >;
 416                         clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
 417                 };
 418
 419                 mstp5_clks: mstp5_clks@fcfe0428 {
 420                         #clock-cells = <1>;
 421                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 422                         reg = <0xfcfe0428 4>;
 423                         clocks = <&p0_clk>, <&p0_clk>;
 424                         clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
 425                         clock-output-names = "ostm0", "ostm1";
 426                 };
 427
 428                 mstp6_clks: mstp6_clks@fcfe042c {
 429                         #clock-cells = <1>;
 430                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 431                         reg = <0xfcfe042c 4>;
 432                         clocks = <&p0_clk>;
 433                         clock-indices = <R7S72100_CLK_RTC>;
 434                         clock-output-names = "rtc";
 435                 };
 436
 437                 mstp7_clks: mstp7_clks@fcfe0430 {
 438                         #clock-cells = <1>;
 439                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 440                         reg = <0xfcfe0430 4>;
 441                         clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
 442                         clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
 443                         clock-output-names = "ether", "usb0", "usb1";
 444                 };
 445
 446                 mstp8_clks: mstp8_clks@fcfe0434 {
 447                         #clock-cells = <1>;
 448                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 449                         reg = <0xfcfe0434 4>;
 450                         clocks = <&p1_clk>;
 451                         clock-indices = <R7S72100_CLK_MMCIF>;
 452                         clock-output-names = "mmcif";
 453                 };
 454
 455                 mstp9_clks: mstp9_clks@fcfe0438 {
 456                         #clock-cells = <1>;
 457                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 458                         reg = <0xfcfe0438 4>;
 459                         clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
 460                         clock-indices = <
 461                                 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
 462                         >;
 463                         clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
 464                 };
 465
 466                 mstp10_clks: mstp10_clks@fcfe043c {
 467                         #clock-cells = <1>;
 468                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 469                         reg = <0xfcfe043c 4>;
 470                         clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
 471                                  <&p1_clk>;
 472                         clock-indices = <
 473                                 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
 474                                 R7S72100_CLK_SPI4
 475                         >;
 476                         clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
 477                 };
 478                 mstp12_clks: mstp12_clks@fcfe0444 {
 479                         #clock-cells = <1>;
 480                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 481                         reg = <0xfcfe0444 4>;
 482                         clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
 483                         clock-indices = <
 484                                 R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
 485                                 R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
 486                         >;
 487                         clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
 488                 };
 489
 490                 pinctrl: pin-controller@fcfe3000 {
 491                         compatible = "renesas,r7s72100-ports";
 492
 493                         reg = <0xfcfe3000 0x4230>;
 494
 495                         port0: gpio-0 {
 496                                 gpio-controller;
 497                                 #gpio-cells = <2>;
 498                                 gpio-ranges = <&pinctrl 0 0 6>;
 499                         };
 500
 501                         port1: gpio-1 {
 502                                 gpio-controller;
 503                                 #gpio-cells = <2>;
 504                                 gpio-ranges = <&pinctrl 0 16 16>;
 505                         };
 506
 507                         port2: gpio-2 {
 508                                 gpio-controller;
 509                                 #gpio-cells = <2>;
 510                                 gpio-ranges = <&pinctrl 0 32 16>;
 511                         };
 512
 513                         port3: gpio-3 {
 514                                 gpio-controller;
 515                                 #gpio-cells = <2>;
 516                                 gpio-ranges = <&pinctrl 0 48 16>;
 517                         };
 518
 519                         port4: gpio-4 {
 520                                 gpio-controller;
 521                                 #gpio-cells = <2>;
 522                                 gpio-ranges = <&pinctrl 0 64 16>;
 523                         };
 524
 525                         port5: gpio-5 {
 526                                 gpio-controller;
 527                                 #gpio-cells = <2>;
 528                                 gpio-ranges = <&pinctrl 0 80 11>;
 529                         };
 530
 531                         port6: gpio-6 {
 532                                 gpio-controller;
 533                                 #gpio-cells = <2>;
 534                                 gpio-ranges = <&pinctrl 0 96 16>;
 535                         };
 536
 537                         port7: gpio-7 {
 538                                 gpio-controller;
 539                                 #gpio-cells = <2>;
 540                                 gpio-ranges = <&pinctrl 0 112 16>;
 541                         };
 542
 543                         port8: gpio-8 {
 544                                 gpio-controller;
 545                                 #gpio-cells = <2>;
 546                                 gpio-ranges = <&pinctrl 0 128 16>;
 547                         };
 548
 549                         port9: gpio-9 {
 550                                 gpio-controller;
 551                                 #gpio-cells = <2>;
 552                                 gpio-ranges = <&pinctrl 0 144 8>;
 553                         };
 554
 555                         port10: gpio-10 {
 556                                 gpio-controller;
 557                                 #gpio-cells = <2>;
 558                                 gpio-ranges = <&pinctrl 0 160 16>;
 559                         };
 560
 561                         port11: gpio-11 {
 562                                 gpio-controller;
 563                                 #gpio-cells = <2>;
 564                                 gpio-ranges = <&pinctrl 0 176 16>;
 565                         };
 566                 };
 567
 568                 ostm0: timer@fcfec000 {
 569                         compatible = "renesas,r7s72100-ostm", "renesas,ostm";
 570                         reg = <0xfcfec000 0x30>;
 571                         interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
 572                         clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
 573                         power-domains = <&cpg_clocks>;
 574                         status = "disabled";
 575                 };
 576
 577                 ostm1: timer@fcfec400 {
 578                         compatible = "renesas,r7s72100-ostm", "renesas,ostm";
 579                         reg = <0xfcfec400 0x30>;
 580                         interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
 581                         clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
 582                         power-domains = <&cpg_clocks>;
 583                         status = "disabled";
 584                 };
 585
 586                 i2c0: i2c@fcfee000 {
 587                         #address-cells = <1>;
 588                         #size-cells = <0>;
 589                         compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 590                         reg = <0xfcfee000 0x44>;
 591                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 592                                      <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
 593                                      <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
 594                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 595                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 596                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 597                                      <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 598                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 599                         clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
 600                         clock-frequency = <100000>;
 601                         power-domains = <&cpg_clocks>;
 602                         status = "disabled";
 603                 };
 604
 605                 i2c1: i2c@fcfee400 {
 606                         #address-cells = <1>;
 607                         #size-cells = <0>;
 608                         compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 609                         reg = <0xfcfee400 0x44>;
 610                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 611                                      <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
 612                                      <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
 613                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 614                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 615                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 616                                      <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 617                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 618                         clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
 619                         clock-frequency = <100000>;
 620                         power-domains = <&cpg_clocks>;
 621                         status = "disabled";
 622                 };
 623
 624                 i2c2: i2c@fcfee800 {
 625                         #address-cells = <1>;
 626                         #size-cells = <0>;
 627                         compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 628                         reg = <0xfcfee800 0x44>;
 629                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 630                                      <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
 631                                      <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
 632                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 633                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 634                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 635                                      <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 636                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 637                         clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
 638                         clock-frequency = <100000>;
 639                         power-domains = <&cpg_clocks>;
 640                         status = "disabled";
 641                 };
 642
 643                 i2c3: i2c@fcfeec00 {
 644                         #address-cells = <1>;
 645                         #size-cells = <0>;
 646                         compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 647                         reg = <0xfcfeec00 0x44>;
 648                         interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 649                                      <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
 650                                      <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
 651                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 652                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 653                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 654                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 655                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 656                         clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
 657                         clock-frequency = <100000>;
 658                         power-domains = <&cpg_clocks>;
 659                         status = "disabled";
 660                 };
 661
 662                 mtu2: timer@fcff0000 {
 663                         compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
 664                         reg = <0xfcff0000 0x400>;
 665                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 666                         interrupt-names = "tgi0a";
 667                         clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
 668                         clock-names = "fck";
 669                         power-domains = <&cpg_clocks>;
 670                         status = "disabled";
 671                 };
 672
 673                 rtc: rtc@fcff1000 {
 674                         compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
 675                         reg = <0xfcff1000 0x2e>;
 676                         interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING
 677                                       GIC_SPI 277 IRQ_TYPE_EDGE_RISING
 678                                       GIC_SPI 278 IRQ_TYPE_EDGE_RISING>;
 679                         interrupt-names = "alarm", "period", "carry";
 680                         clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
 681                                  <&rtc_x3_clk>, <&extal_clk>;
 682                         clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
 683                         power-domains = <&cpg_clocks>;
 684                         status = "disabled";
 685                 };
 686         };
 687
 688         usb_x1_clk: usb_x1 {
 689                 #clock-cells = <0>;
 690                 compatible = "fixed-clock";
 691                 /* If clk present, value must be set by board */
 692                 clock-frequency = <0>;
 693         };
 694 };