arch/arm/boot/dts/r7s72100.dtsi

   1 /*
   2  * Device Tree Source for the r7s72100 SoC
   3  *
   4  * Copyright (C) 2013-14 Renesas Solutions Corp.
   5  * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r7s72100-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r7s72100";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 spi0 = &spi0;
  28                 spi1 = &spi1;
  29                 spi2 = &spi2;
  30                 spi3 = &spi3;
  31                 spi4 = &spi4;
  32         };
  33
  34         clocks {
  35                 ranges;
  36                 #address-cells = <1>;
  37                 #size-cells = <1>;
  38
  39                 /* External clocks */
  40                 extal_clk: extal {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-clock";
  43                         /* If clk present, value must be set by board */
  44                         clock-frequency = <0>;
  45                 };
  46
  47                 usb_x1_clk: usb_x1 {
  48                         #clock-cells = <0>;
  49                         compatible = "fixed-clock";
  50                         /* If clk present, value must be set by board */
  51                         clock-frequency = <0>;
  52                 };
  53
  54                 /* Fixed factor clocks */
  55                 b_clk: b {
  56                         #clock-cells = <0>;
  57                         compatible = "fixed-factor-clock";
  58                         clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  59                         clock-mult = <1>;
  60                         clock-div = <3>;
  61                 };
  62                 p1_clk: p1 {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-factor-clock";
  65                         clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  66                         clock-mult = <1>;
  67                         clock-div = <6>;
  68                 };
  69                 p0_clk: p0 {
  70                         #clock-cells = <0>;
  71                         compatible = "fixed-factor-clock";
  72                         clocks = <&cpg_clocks R7S72100_CLK_PLL>;
  73                         clock-mult = <1>;
  74                         clock-div = <12>;
  75                 };
  76
  77                 /* Special CPG clocks */
  78                 cpg_clocks: cpg_clocks@fcfe0000 {
  79                         #clock-cells = <1>;
  80                         compatible = "renesas,r7s72100-cpg-clocks",
  81                                      "renesas,rz-cpg-clocks";
  82                         reg = <0xfcfe0000 0x18>;
  83                         clocks = <&extal_clk>, <&usb_x1_clk>;
  84                         clock-output-names = "pll", "i", "g";
  85                         #power-domain-cells = <0>;
  86                 };
  87
  88                 /* MSTP clocks */
  89                 mstp3_clks: mstp3_clks@fcfe0420 {
  90                         #clock-cells = <1>;
  91                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
  92                         reg = <0xfcfe0420 4>;
  93                         clocks = <&p0_clk>;
  94                         clock-indices = <R7S72100_CLK_MTU2>;
  95                         clock-output-names = "mtu2";
  96                 };
  97
  98                 mstp4_clks: mstp4_clks@fcfe0424 {
  99                         #clock-cells = <1>;
 100                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 101                         reg = <0xfcfe0424 4>;
 102                         clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
 103                                  <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
 104                         clock-indices = <
 105                                 R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
 106                                 R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
 107                         >;
 108                         clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
 109                 };
 110
 111                 mstp5_clks: mstp5_clks@fcfe0428 {
 112                         #clock-cells = <1>;
 113                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 114                         reg = <0xfcfe0428 4>;
 115                         clocks = <&p0_clk>, <&p0_clk>;
 116                         clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
 117                         clock-output-names = "ostm0", "ostm1";
 118                 };
 119
 120                 mstp6_clks: mstp6_clks@fcfe042c {
 121                         #clock-cells = <1>;
 122                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 123                         reg = <0xfcfe042c 4>;
 124                         clocks = <&p0_clk>;
 125                         clock-indices = <R7S72100_CLK_RTC>;
 126                         clock-output-names = "rtc";
 127                 };
 128
 129                 mstp7_clks: mstp7_clks@fcfe0430 {
 130                         #clock-cells = <1>;
 131                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 132                         reg = <0xfcfe0430 4>;
 133                         clocks = <&b_clk>;
 134                         clock-indices = <R7S72100_CLK_ETHER>;
 135                         clock-output-names = "ether";
 136                 };
 137
 138                 mstp8_clks: mstp8_clks@fcfe0434 {
 139                         #clock-cells = <1>;
 140                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 141                         reg = <0xfcfe0434 4>;
 142                         clocks = <&p1_clk>;
 143                         clock-indices = <R7S72100_CLK_MMCIF>;
 144                         clock-output-names = "mmcif";
 145                 };
 146
 147                 mstp9_clks: mstp9_clks@fcfe0438 {
 148                         #clock-cells = <1>;
 149                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 150                         reg = <0xfcfe0438 4>;
 151                         clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
 152                         clock-indices = <
 153                                 R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
 154                         >;
 155                         clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
 156                 };
 157
 158                 mstp10_clks: mstp10_clks@fcfe043c {
 159                         #clock-cells = <1>;
 160                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 161                         reg = <0xfcfe043c 4>;
 162                         clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
 163                                  <&p1_clk>;
 164                         clock-indices = <
 165                                 R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
 166                                 R7S72100_CLK_SPI4
 167                         >;
 168                         clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
 169                 };
 170                 mstp12_clks: mstp12_clks@fcfe0444 {
 171                         #clock-cells = <1>;
 172                         compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
 173                         reg = <0xfcfe0444 4>;
 174                         clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
 175                         clock-indices = <
 176                                 R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
 177                                 R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
 178                         >;
 179                         clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
 180                 };
 181         };
 182
 183         cpus {
 184                 #address-cells = <1>;
 185                 #size-cells = <0>;
 186
 187                 cpu@0 {
 188                         device_type = "cpu";
 189                         compatible = "arm,cortex-a9";
 190                         reg = <0>;
 191                         clock-frequency = <400000000>;
 192                 };
 193         };
 194
 195         scif0: serial@e8007000 {
 196                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 197                 reg = <0xe8007000 64>;
 198                 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 201                              <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 202                 clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
 203                 clock-names = "fck";
 204                 power-domains = <&cpg_clocks>;
 205                 status = "disabled";
 206         };
 207
 208         scif1: serial@e8007800 {
 209                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 210                 reg = <0xe8007800 64>;
 211                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
 213                              <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 214                              <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 215                 clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
 216                 clock-names = "fck";
 217                 power-domains = <&cpg_clocks>;
 218                 status = "disabled";
 219         };
 220
 221         scif2: serial@e8008000 {
 222                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 223                 reg = <0xe8008000 64>;
 224                 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 225                              <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 226                              <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
 227                              <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 228                 clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
 229                 clock-names = "fck";
 230                 power-domains = <&cpg_clocks>;
 231                 status = "disabled";
 232         };
 233
 234         scif3: serial@e8008800 {
 235                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 236                 reg = <0xe8008800 64>;
 237                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 239                              <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
 240                              <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 241                 clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
 242                 clock-names = "fck";
 243                 power-domains = <&cpg_clocks>;
 244                 status = "disabled";
 245         };
 246
 247         scif4: serial@e8009000 {
 248                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 249                 reg = <0xe8009000 64>;
 250                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
 251                              <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 252                              <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 253                              <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 254                 clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
 255                 clock-names = "fck";
 256                 power-domains = <&cpg_clocks>;
 257                 status = "disabled";
 258         };
 259
 260         scif5: serial@e8009800 {
 261                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 262                 reg = <0xe8009800 64>;
 263                 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 267                 clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
 268                 clock-names = "fck";
 269                 power-domains = <&cpg_clocks>;
 270                 status = "disabled";
 271         };
 272
 273         scif6: serial@e800a000 {
 274                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 275                 reg = <0xe800a000 64>;
 276                 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 277                              <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 278                              <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
 279                              <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
 280                 clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
 281                 clock-names = "fck";
 282                 power-domains = <&cpg_clocks>;
 283                 status = "disabled";
 284         };
 285
 286         scif7: serial@e800a800 {
 287                 compatible = "renesas,scif-r7s72100", "renesas,scif";
 288                 reg = <0xe800a800 64>;
 289                 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
 293                 clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
 294                 clock-names = "fck";
 295                 power-domains = <&cpg_clocks>;
 296                 status = "disabled";
 297         };
 298
 299         spi0: spi@e800c800 {
 300                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 301                 reg = <0xe800c800 0x24>;
 302                 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 303                              <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 304                              <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 305                 interrupt-names = "error", "rx", "tx";
 306                 clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
 307                 power-domains = <&cpg_clocks>;
 308                 num-cs = <1>;
 309                 #address-cells = <1>;
 310                 #size-cells = <0>;
 311                 status = "disabled";
 312         };
 313
 314         spi1: spi@e800d000 {
 315                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 316                 reg = <0xe800d000 0x24>;
 317                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 318                              <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 319                              <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 320                 interrupt-names = "error", "rx", "tx";
 321                 clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
 322                 power-domains = <&cpg_clocks>;
 323                 num-cs = <1>;
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326                 status = "disabled";
 327         };
 328
 329         spi2: spi@e800d800 {
 330                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 331                 reg = <0xe800d800 0x24>;
 332                 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 333                              <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 334                              <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 335                 interrupt-names = "error", "rx", "tx";
 336                 clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
 337                 power-domains = <&cpg_clocks>;
 338                 num-cs = <1>;
 339                 #address-cells = <1>;
 340                 #size-cells = <0>;
 341                 status = "disabled";
 342         };
 343
 344         spi3: spi@e800e000 {
 345                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 346                 reg = <0xe800e000 0x24>;
 347                 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 348                              <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 349                              <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 350                 interrupt-names = "error", "rx", "tx";
 351                 clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
 352                 power-domains = <&cpg_clocks>;
 353                 num-cs = <1>;
 354                 #address-cells = <1>;
 355                 #size-cells = <0>;
 356                 status = "disabled";
 357         };
 358
 359         spi4: spi@e800e800 {
 360                 compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
 361                 reg = <0xe800e800 0x24>;
 362                 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 363                              <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 364                              <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 365                 interrupt-names = "error", "rx", "tx";
 366                 clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
 367                 power-domains = <&cpg_clocks>;
 368                 num-cs = <1>;
 369                 #address-cells = <1>;
 370                 #size-cells = <0>;
 371                 status = "disabled";
 372         };
 373
 374         gic: interrupt-controller@e8201000 {
 375                 compatible = "arm,pl390";
 376                 #interrupt-cells = <3>;
 377                 #address-cells = <0>;
 378                 interrupt-controller;
 379                 reg = <0xe8201000 0x1000>,
 380                         <0xe8202000 0x1000>;
 381         };
 382
 383         wdt: watchdog@fcfe0000 {
 384                 compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
 385                 reg = <0xfcfe0000 0x6>;
 386                 interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
 387                 clocks = <&p0_clk>;
 388         };
 389
 390         i2c0: i2c@fcfee000 {
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 394                 reg = <0xfcfee000 0x44>;
 395                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 396                              <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
 397                              <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
 398                              <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 399                              <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 400                              <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 401                              <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 402                              <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 403                 clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
 404                 clock-frequency = <100000>;
 405                 power-domains = <&cpg_clocks>;
 406                 status = "disabled";
 407         };
 408
 409         i2c1: i2c@fcfee400 {
 410                 #address-cells = <1>;
 411                 #size-cells = <0>;
 412                 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 413                 reg = <0xfcfee400 0x44>;
 414                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 415                              <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
 416                              <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
 417                              <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 418                              <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 419                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 420                              <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 421                              <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
 422                 clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
 423                 clock-frequency = <100000>;
 424                 power-domains = <&cpg_clocks>;
 425                 status = "disabled";
 426         };
 427
 428         i2c2: i2c@fcfee800 {
 429                 #address-cells = <1>;
 430                 #size-cells = <0>;
 431                 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 432                 reg = <0xfcfee800 0x44>;
 433                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 434                              <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
 435                              <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
 436                              <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 437                              <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 438                              <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 439                              <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 440                              <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 441                 clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
 442                 clock-frequency = <100000>;
 443                 power-domains = <&cpg_clocks>;
 444                 status = "disabled";
 445         };
 446
 447         i2c3: i2c@fcfeec00 {
 448                 #address-cells = <1>;
 449                 #size-cells = <0>;
 450                 compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
 451                 reg = <0xfcfeec00 0x44>;
 452                 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 453                              <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
 454                              <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
 455                              <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 456                              <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 457                              <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 458                              <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 459                              <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 460                 clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
 461                 clock-frequency = <100000>;
 462                 power-domains = <&cpg_clocks>;
 463                 status = "disabled";
 464         };
 465
 466         mtu2: timer@fcff0000 {
 467                 compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
 468                 reg = <0xfcff0000 0x400>;
 469                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 470                 interrupt-names = "tgi0a";
 471                 clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
 472                 clock-names = "fck";
 473                 power-domains = <&cpg_clocks>;
 474                 status = "disabled";
 475         };
 476
 477         ether: ethernet@e8203000 {
 478                 compatible = "renesas,ether-r7s72100";
 479                 reg = <0xe8203000 0x800>,
 480                       <0xe8204800 0x200>;
 481                 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
 482                 clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
 483                 power-domains = <&cpg_clocks>;
 484                 phy-mode = "mii";
 485                 #address-cells = <1>;
 486                 #size-cells = <0>;
 487                 status = "disabled";
 488         };
 489
 490         mmcif: mmc@e804c800 {
 491                 compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
 492                 reg = <0xe804c800 0x80>;
 493                 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
 494                               GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
 495                               GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 496                 clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
 497                 power-domains = <&cpg_clocks>;
 498                 reg-io-width = <4>;
 499                 bus-width = <8>;
 500                 status = "disabled";
 501         };
 502
 503         sdhi0: sd@e804e000 {
 504                 compatible = "renesas,sdhi-r7s72100";
 505                 reg = <0xe804e000 0x100>;
 506                 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
 507                               GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
 508                               GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 509
 510                 clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
 511                          <&mstp12_clks R7S72100_CLK_SDHI01>;
 512                 clock-names = "core", "cd";
 513                 power-domains = <&cpg_clocks>;
 514                 cap-sd-highspeed;
 515                 cap-sdio-irq;
 516                 status = "disabled";
 517         };
 518
 519         sdhi1: sd@e804e800 {
 520                 compatible = "renesas,sdhi-r7s72100";
 521                 reg = <0xe804e800 0x100>;
 522                 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
 523                               GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
 524                               GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
 525
 526                 clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
 527                          <&mstp12_clks R7S72100_CLK_SDHI11>;
 528                 clock-names = "core", "cd";
 529                 power-domains = <&cpg_clocks>;
 530                 cap-sd-highspeed;
 531                 cap-sdio-irq;
 532                 status = "disabled";
 533         };
 534
 535         ostm0: timer@fcfec000 {
 536                 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
 537                 reg = <0xfcfec000 0x30>;
 538                 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
 539                 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
 540                 power-domains = <&cpg_clocks>;
 541                 status = "disabled";
 542         };
 543
 544         ostm1: timer@fcfec400 {
 545                 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
 546                 reg = <0xfcfec400 0x30>;
 547                 interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
 548                 clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
 549                 power-domains = <&cpg_clocks>;
 550                 status = "disabled";
 551         };
 552 };