1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the RZ/A1H RSK board
5 * Copyright (C) 2016 Renesas Electronics
9 #include "r7s72100.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
15 compatible = "renesas,rskrza1", "renesas,r7s72100";
22 bootargs = "ignore_loglevel";
23 stdout-path = "serial0:115200n8";
27 device_type = "memory";
28 reg = <0x08000000 0x02000000>;
37 compatible = "gpio-leds";
40 gpios = <&port7 1 GPIO_ACTIVE_LOW>;
44 gpios = <&io_expander1 0 GPIO_ACTIVE_LOW>;
48 gpios = <&io_expander1 1 GPIO_ACTIVE_LOW>;
52 gpios = <&io_expander1 2 GPIO_ACTIVE_LOW>;
58 clock-frequency = <13330000>;
62 pinctrl-names = "default";
63 pinctrl-0 = <&i2c3_pins>;
66 clock-frequency = <400000>;
68 io_expander1: gpio@20 {
69 compatible = "onnn,cat9554";
75 io_expander2: gpio@21 {
76 compatible = "onnn,cat9554";
83 compatible = "renesas,r1ex24016", "atmel,24c16";
90 clock-frequency = <48000000>;
94 clock-frequency = <32768>;
98 /* RIIC ch3 (Port Expander, EEPROM (MAC Addr), Audio Codec) */
100 pinmux = <RZA1_PINMUX(1, 6, 1)>, /* RIIC3SCL */
101 <RZA1_PINMUX(1, 7, 1)>; /* RIIC3SDA */
105 scif2_pins: serial2 {
106 pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */
107 <RZA1_PINMUX(3, 2, 4)>; /* RxD2 */
112 /* Ethernet on Ports 1,2,3,5 */
113 pinmux = <RZA1_PINMUX(1, 14, 4)>, /* ET_COL */
114 <RZA1_PINMUX(5, 9, 2)>, /* ET_MDC */
115 <RZA1_PINMUX(3, 3, 2)>, /* ET_MDIO */
116 <RZA1_PINMUX(3, 4, 2)>, /* ET_RXCLK */
117 <RZA1_PINMUX(3, 5, 2)>, /* ET_RXER */
118 <RZA1_PINMUX(3, 6, 2)>, /* ET_RXDV */
119 <RZA1_PINMUX(2, 0, 2)>, /* ET_TXCLK */
120 <RZA1_PINMUX(2, 1, 2)>, /* ET_TXER */
121 <RZA1_PINMUX(2, 2, 2)>, /* ET_TXEN */
122 <RZA1_PINMUX(2, 3, 2)>, /* ET_CRS */
123 <RZA1_PINMUX(2, 4, 2)>, /* ET_TXD0 */
124 <RZA1_PINMUX(2, 5, 2)>, /* ET_TXD1 */
125 <RZA1_PINMUX(2, 6, 2)>, /* ET_TXD2 */
126 <RZA1_PINMUX(2, 7, 2)>, /* ET_TXD3 */
127 <RZA1_PINMUX(2, 8, 2)>, /* ET_RXD0 */
128 <RZA1_PINMUX(2, 9, 2)>, /* ET_RXD1 */
129 <RZA1_PINMUX(2, 10, 2)>, /* ET_RXD2 */
130 <RZA1_PINMUX(2, 11, 2)>; /* ET_RXD3 */
133 /* SDHI ch1 on CN1 */
135 pinmux = <RZA1_PINMUX(3, 8, 7)>, /* SD_CD_1 */
136 <RZA1_PINMUX(3, 9, 7)>, /* SD_WP_1 */
137 <RZA1_PINMUX(3, 10, 7)>, /* SD_D1_1 */
138 <RZA1_PINMUX(3, 11, 7)>, /* SD_D0_1 */
139 <RZA1_PINMUX(3, 12, 7)>, /* SD_CLK_1 */
140 <RZA1_PINMUX(3, 13, 7)>, /* SD_CMD_1 */
141 <RZA1_PINMUX(3, 14, 7)>, /* SD_D3_1 */
142 <RZA1_PINMUX(3, 15, 7)>; /* SD_D2_1 */
151 pinctrl-names = "default";
152 pinctrl-0 = <ðer_pins>;
154 renesas,no-ether-link;
155 phy-handle = <&phy0>;
156 phy0: ethernet-phy@0 {
162 pinctrl-names = "default";
163 pinctrl-0 = <&sdhi1_pins>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&scif2_pins>;