3 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include "skeleton.dtsi"
11 model = "Qualcomm MSM8974";
12 compatible = "qcom,msm8974";
13 interrupt-parent = <&intc>;
21 reg = <0x08000000 0x5100000>;
26 reg = <0x0d100000 0x100000>;
31 reg = <0x0d200000 0xa00000>;
35 adsp_region: adsp@0dc00000 {
36 reg = <0x0dc00000 0x1900000>;
41 reg = <0x0f500000 0x500000>;
45 smem_region: smem@fa00000 {
46 reg = <0xfa00000 0x200000>;
51 reg = <0x0fc00000 0x160000>;
56 reg = <0x0fd60000 0x20000>;
61 reg = <0x0fd80000 0x180000>;
69 interrupts = <1 9 0xf04>;
72 compatible = "qcom,krait";
73 enable-method = "qcom,kpss-acc-v2";
76 next-level-cache = <&L2>;
79 cpu-idle-states = <&CPU_SPC>;
83 compatible = "qcom,krait";
84 enable-method = "qcom,kpss-acc-v2";
87 next-level-cache = <&L2>;
90 cpu-idle-states = <&CPU_SPC>;
94 compatible = "qcom,krait";
95 enable-method = "qcom,kpss-acc-v2";
98 next-level-cache = <&L2>;
101 cpu-idle-states = <&CPU_SPC>;
105 compatible = "qcom,krait";
106 enable-method = "qcom,kpss-acc-v2";
109 next-level-cache = <&L2>;
112 cpu-idle-states = <&CPU_SPC>;
116 compatible = "cache";
118 qcom,saw = <&saw_l2>;
123 compatible = "qcom,idle-state-spc",
125 entry-latency-us = <150>;
126 exit-latency-us = <200>;
127 min-residency-us = <2000>;
134 polling-delay-passive = <250>;
135 polling-delay = <1000>;
137 thermal-sensors = <&tsens 5>;
141 temperature = <75000>;
146 temperature = <110000>;
154 polling-delay-passive = <250>;
155 polling-delay = <1000>;
157 thermal-sensors = <&tsens 6>;
161 temperature = <75000>;
166 temperature = <110000>;
174 polling-delay-passive = <250>;
175 polling-delay = <1000>;
177 thermal-sensors = <&tsens 7>;
181 temperature = <75000>;
186 temperature = <110000>;
194 polling-delay-passive = <250>;
195 polling-delay = <1000>;
197 thermal-sensors = <&tsens 8>;
201 temperature = <75000>;
206 temperature = <110000>;
215 compatible = "qcom,krait-pmu";
216 interrupts = <1 7 0xf04>;
221 compatible = "fixed-clock";
223 clock-frequency = <19200000>;
226 sleep_clk: sleep_clk {
227 compatible = "fixed-clock";
229 clock-frequency = <32768>;
234 compatible = "arm,armv7-timer";
235 interrupts = <1 2 0xf08>,
239 clock-frequency = <19200000>;
243 compatible = "qcom,msm8974-adsp-pil";
245 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
246 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
247 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
248 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
249 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
250 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
252 cx-supply = <&pm8841_s2>;
254 clocks = <&xo_board>;
257 memory-region = <&adsp_region>;
259 qcom,smem-states = <&adsp_smp2p_out 0>;
260 qcom,smem-state-names = "stop";
264 compatible = "qcom,smem";
266 memory-region = <&smem_region>;
267 qcom,rpm-msg-ram = <&rpm_msg_ram>;
269 hwlocks = <&tcsr_mutex 3>;
273 compatible = "qcom,smp2p";
274 qcom,smem = <443>, <429>;
276 interrupt-parent = <&intc>;
277 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
279 qcom,ipc = <&apcs 8 10>;
281 qcom,local-pid = <0>;
282 qcom,remote-pid = <2>;
284 adsp_smp2p_out: master-kernel {
285 qcom,entry-name = "master-kernel";
286 #qcom,smem-state-cells = <1>;
289 adsp_smp2p_in: slave-kernel {
290 qcom,entry-name = "slave-kernel";
292 interrupt-controller;
293 #interrupt-cells = <2>;
298 compatible = "qcom,smp2p";
299 qcom,smem = <435>, <428>;
301 interrupt-parent = <&intc>;
302 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
304 qcom,ipc = <&apcs 8 14>;
306 qcom,local-pid = <0>;
307 qcom,remote-pid = <1>;
309 modem_smp2p_out: master-kernel {
310 qcom,entry-name = "master-kernel";
311 #qcom,smem-state-cells = <1>;
314 modem_smp2p_in: slave-kernel {
315 qcom,entry-name = "slave-kernel";
317 interrupt-controller;
318 #interrupt-cells = <2>;
323 compatible = "qcom,smp2p";
324 qcom,smem = <451>, <431>;
326 interrupt-parent = <&intc>;
327 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
329 qcom,ipc = <&apcs 8 18>;
331 qcom,local-pid = <0>;
332 qcom,remote-pid = <4>;
334 wcnss_smp2p_out: master-kernel {
335 qcom,entry-name = "master-kernel";
337 #qcom,smem-state-cells = <1>;
340 wcnss_smp2p_in: slave-kernel {
341 qcom,entry-name = "slave-kernel";
343 interrupt-controller;
344 #interrupt-cells = <2>;
349 compatible = "qcom,smsm";
351 #address-cells = <1>;
354 qcom,ipc-1 = <&apcs 8 13>;
355 qcom,ipc-2 = <&apcs 8 9>;
356 qcom,ipc-3 = <&apcs 8 19>;
361 #qcom,smem-state-cells = <1>;
364 modem_smsm: modem@1 {
366 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
368 interrupt-controller;
369 #interrupt-cells = <2>;
374 interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
376 interrupt-controller;
377 #interrupt-cells = <2>;
380 wcnss_smsm: wcnss@7 {
382 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
384 interrupt-controller;
385 #interrupt-cells = <2>;
391 compatible = "qcom,scm";
392 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
393 clock-names = "core", "bus", "iface";
398 #address-cells = <1>;
401 compatible = "simple-bus";
403 intc: interrupt-controller@f9000000 {
404 compatible = "qcom,msm-qgic2";
405 interrupt-controller;
406 #interrupt-cells = <3>;
407 reg = <0xf9000000 0x1000>,
411 apcs: syscon@f9011000 {
412 compatible = "syscon";
413 reg = <0xf9011000 0x1000>;
416 qfprom: qfprom@fc4bc000 {
417 #address-cells = <1>;
419 compatible = "qcom,qfprom";
420 reg = <0xfc4bc000 0x1000>;
421 tsens_calib: calib@d0 {
424 tsens_backup: backup@440 {
429 tsens: thermal-sensor@fc4a8000 {
430 compatible = "qcom,msm8974-tsens";
431 reg = <0xfc4a8000 0x2000>;
432 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
433 nvmem-cell-names = "calib", "calib_backup";
434 #thermal-sensor-cells = <1>;
438 #address-cells = <1>;
441 compatible = "arm,armv7-timer-mem";
442 reg = <0xf9020000 0x1000>;
443 clock-frequency = <19200000>;
447 interrupts = <0 8 0x4>,
449 reg = <0xf9021000 0x1000>,
455 interrupts = <0 9 0x4>;
456 reg = <0xf9023000 0x1000>;
462 interrupts = <0 10 0x4>;
463 reg = <0xf9024000 0x1000>;
469 interrupts = <0 11 0x4>;
470 reg = <0xf9025000 0x1000>;
476 interrupts = <0 12 0x4>;
477 reg = <0xf9026000 0x1000>;
483 interrupts = <0 13 0x4>;
484 reg = <0xf9027000 0x1000>;
490 interrupts = <0 14 0x4>;
491 reg = <0xf9028000 0x1000>;
496 saw0: power-controller@f9089000 {
497 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
498 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
501 saw1: power-controller@f9099000 {
502 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
503 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
506 saw2: power-controller@f90a9000 {
507 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
508 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
511 saw3: power-controller@f90b9000 {
512 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
513 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
516 saw_l2: power-controller@f9012000 {
517 compatible = "qcom,saw2";
518 reg = <0xf9012000 0x1000>;
522 acc0: clock-controller@f9088000 {
523 compatible = "qcom,kpss-acc-v2";
524 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
527 acc1: clock-controller@f9098000 {
528 compatible = "qcom,kpss-acc-v2";
529 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
532 acc2: clock-controller@f90a8000 {
533 compatible = "qcom,kpss-acc-v2";
534 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
537 acc3: clock-controller@f90b8000 {
538 compatible = "qcom,kpss-acc-v2";
539 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
543 compatible = "qcom,pshold";
544 reg = <0xfc4ab000 0x4>;
547 gcc: clock-controller@fc400000 {
548 compatible = "qcom,gcc-msm8974";
551 #power-domain-cells = <1>;
552 reg = <0xfc400000 0x4000>;
555 tcsr: syscon@fd4a0000 {
556 compatible = "syscon";
557 reg = <0xfd4a0000 0x10000>;
560 tcsr_mutex_block: syscon@fd484000 {
561 compatible = "syscon";
562 reg = <0xfd484000 0x2000>;
565 mmcc: clock-controller@fd8c0000 {
566 compatible = "qcom,mmcc-msm8974";
569 #power-domain-cells = <1>;
570 reg = <0xfd8c0000 0x6000>;
573 tcsr_mutex: tcsr-mutex {
574 compatible = "qcom,tcsr-mutex";
575 syscon = <&tcsr_mutex_block 0 0x80>;
580 rpm_msg_ram: memory@fc428000 {
581 compatible = "qcom,rpm-msg-ram";
582 reg = <0xfc428000 0x4000>;
585 blsp1_uart1: serial@f991d000 {
586 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
587 reg = <0xf991d000 0x1000>;
588 interrupts = <0 107 0x0>;
589 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
590 clock-names = "core", "iface";
594 blsp1_uart2: serial@f991e000 {
595 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
596 reg = <0xf991e000 0x1000>;
597 interrupts = <0 108 0x0>;
598 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
599 clock-names = "core", "iface";
604 compatible = "qcom,sdhci-msm-v4";
605 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
606 reg-names = "hc_mem", "core_mem";
607 interrupts = <0 123 0>, <0 138 0>;
608 interrupt-names = "hc_irq", "pwr_irq";
609 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
610 <&gcc GCC_SDCC1_AHB_CLK>,
612 clock-names = "core", "iface", "xo";
617 compatible = "qcom,sdhci-msm-v4";
618 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
619 reg-names = "hc_mem", "core_mem";
620 interrupts = <0 125 0>, <0 221 0>;
621 interrupt-names = "hc_irq", "pwr_irq";
622 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
623 <&gcc GCC_SDCC2_AHB_CLK>,
625 clock-names = "core", "iface", "xo";
630 compatible = "qcom,ci-hdrc";
631 reg = <0xf9a55000 0x200>,
633 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
635 <&gcc GCC_USB_HS_SYSTEM_CLK>;
636 clock-names = "iface", "core";
637 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
638 assigned-clock-rates = <75000000>;
639 resets = <&gcc GCC_USB_HS_BCR>;
640 reset-names = "core";
643 ahb-burst-config = <0>;
644 phy-names = "usb-phy";
650 compatible = "qcom,usb-hs-phy-msm8974",
653 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
654 clock-names = "ref", "sleep";
655 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
656 reset-names = "phy", "por";
661 compatible = "qcom,usb-hs-phy-msm8974",
664 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
665 clock-names = "ref", "sleep";
666 resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
667 reset-names = "phy", "por";
674 compatible = "qcom,prng";
675 reg = <0xf9bff000 0x200>;
676 clocks = <&gcc GCC_PRNG_AHB_CLK>;
677 clock-names = "core";
680 msmgpio: pinctrl@fd510000 {
681 compatible = "qcom,msm8974-pinctrl";
682 reg = <0xfd510000 0x4000>;
685 interrupt-controller;
686 #interrupt-cells = <2>;
687 interrupts = <0 208 0>;
692 compatible = "qcom,i2c-qup-v2.1.1";
693 reg = <0xf9924000 0x1000>;
694 interrupts = <0 96 IRQ_TYPE_NONE>;
695 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
696 clock-names = "core", "iface";
697 #address-cells = <1>;
701 blsp_i2c8: i2c@f9964000 {
703 compatible = "qcom,i2c-qup-v2.1.1";
704 reg = <0xf9964000 0x1000>;
705 interrupts = <0 102 IRQ_TYPE_NONE>;
706 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
707 clock-names = "core", "iface";
708 #address-cells = <1>;
712 blsp_i2c11: i2c@f9967000 {
714 compatible = "qcom,i2c-qup-v2.1.1";
715 reg = <0xf9967000 0x1000>;
716 interrupts = <0 105 IRQ_TYPE_NONE>;
717 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
718 clock-names = "core", "iface";
719 #address-cells = <1>;
721 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
722 dma-names = "tx", "rx";
725 spmi_bus: spmi@fc4cf000 {
726 compatible = "qcom,spmi-pmic-arb";
727 reg-names = "core", "intr", "cnfg";
728 reg = <0xfc4cf000 0x1000>,
731 interrupt-names = "periph_irq";
732 interrupts = <0 190 0>;
735 #address-cells = <2>;
737 interrupt-controller;
738 #interrupt-cells = <4>;
741 blsp2_dma: dma-controller@f9944000 {
742 compatible = "qcom,bam-v1.4.0";
743 reg = <0xf9944000 0x19000>;
744 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
746 clock-names = "bam_clk";
752 compatible = "arm,coresight-tmc", "arm,primecell";
753 reg = <0xfc322000 0x1000>;
755 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
756 clock-names = "apb_pclk", "atclk";
761 remote-endpoint = <&replicator_out0>;
767 compatible = "arm,coresight-tpiu", "arm,primecell";
768 reg = <0xfc318000 0x1000>;
770 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
771 clock-names = "apb_pclk", "atclk";
776 remote-endpoint = <&replicator_out1>;
781 replicator@fc31c000 {
782 compatible = "qcom,coresight-replicator1x", "arm,primecell";
783 reg = <0xfc31c000 0x1000>;
785 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
786 clock-names = "apb_pclk", "atclk";
789 #address-cells = <1>;
794 replicator_out0: endpoint {
795 remote-endpoint = <&etr_in>;
800 replicator_out1: endpoint {
801 remote-endpoint = <&tpiu_in>;
806 replicator_in: endpoint {
808 remote-endpoint = <&etf_out>;
815 compatible = "arm,coresight-tmc", "arm,primecell";
816 reg = <0xfc307000 0x1000>;
818 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
819 clock-names = "apb_pclk", "atclk";
822 #address-cells = <1>;
828 remote-endpoint = <&replicator_in>;
835 remote-endpoint = <&merger_out>;
842 compatible = "arm,coresight-funnel", "arm,primecell";
843 reg = <0xfc31b000 0x1000>;
845 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
846 clock-names = "apb_pclk", "atclk";
849 #address-cells = <1>;
853 * Not described input ports:
854 * 0 - connected trought funnel to Audio, Modem and
855 * Resource and Power Manager CPU's
856 * 2...7 - not-connected
860 merger_in1: endpoint {
862 remote-endpoint = <&funnel1_out>;
867 merger_out: endpoint {
868 remote-endpoint = <&etf_in>;
875 compatible = "arm,coresight-funnel", "arm,primecell";
876 reg = <0xfc31a000 0x1000>;
878 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
879 clock-names = "apb_pclk", "atclk";
882 #address-cells = <1>;
886 * Not described input ports:
888 * 1 - connected trought funnel to Multimedia CPU
889 * 2 - connected to Wireless CPU
893 * 7 - connected to STM
897 funnel1_in5: endpoint {
899 remote-endpoint = <&kpss_out>;
904 funnel1_out: endpoint {
905 remote-endpoint = <&merger_in1>;
911 funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
912 compatible = "arm,coresight-funnel", "arm,primecell";
913 reg = <0xfc345000 0x1000>;
915 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
916 clock-names = "apb_pclk", "atclk";
919 #address-cells = <1>;
926 remote-endpoint = <&etm0_out>;
933 remote-endpoint = <&etm1_out>;
940 remote-endpoint = <&etm2_out>;
947 remote-endpoint = <&etm3_out>;
953 remote-endpoint = <&funnel1_in5>;
960 compatible = "arm,coresight-etm4x", "arm,primecell";
961 reg = <0xfc33c000 0x1000>;
963 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
964 clock-names = "apb_pclk", "atclk";
970 remote-endpoint = <&kpss_in0>;
976 compatible = "arm,coresight-etm4x", "arm,primecell";
977 reg = <0xfc33d000 0x1000>;
979 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
980 clock-names = "apb_pclk", "atclk";
986 remote-endpoint = <&kpss_in1>;
992 compatible = "arm,coresight-etm4x", "arm,primecell";
993 reg = <0xfc33e000 0x1000>;
995 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
996 clock-names = "apb_pclk", "atclk";
1001 etm2_out: endpoint {
1002 remote-endpoint = <&kpss_in2>;
1008 compatible = "arm,coresight-etm4x", "arm,primecell";
1009 reg = <0xfc33f000 0x1000>;
1011 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1012 clock-names = "apb_pclk", "atclk";
1017 etm3_out: endpoint {
1018 remote-endpoint = <&kpss_in3>;
1025 compatible = "qcom,smd";
1028 interrupts = <0 156 IRQ_TYPE_EDGE_RISING>;
1030 qcom,ipc = <&apcs 8 8>;
1031 qcom,smd-edge = <1>;
1035 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
1037 qcom,ipc = <&apcs 8 12>;
1038 qcom,smd-edge = <0>;
1042 interrupts = <0 168 1>;
1043 qcom,ipc = <&apcs 8 0>;
1044 qcom,smd-edge = <15>;
1047 compatible = "qcom,rpm-msm8974";
1048 qcom,smd-channels = "rpm_requests";
1050 rpmcc: clock-controller {
1051 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
1056 compatible = "qcom,rpm-pm8841-regulators";
1069 compatible = "qcom,rpm-pm8941-regulators";
1100 pm8941_lvs1: lvs1 {};
1101 pm8941_lvs2: lvs2 {};
1102 pm8941_lvs3: lvs3 {};
1108 vreg_boost: vreg-boost {
1109 compatible = "regulator-fixed";
1111 regulator-name = "vreg-boost";
1112 regulator-min-microvolt = <3150000>;
1113 regulator-max-microvolt = <3150000>;
1115 regulator-always-on;
1118 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1121 pinctrl-names = "default";
1122 pinctrl-0 = <&boost_bypass_n_pin>;
1124 vreg_vph_pwr: vreg-vph-pwr {
1125 compatible = "regulator-fixed";
1126 regulator-name = "vph-pwr";
1128 regulator-min-microvolt = <3600000>;
1129 regulator-max-microvolt = <3600000>;
1131 regulator-always-on;