1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
8 #include <dt-bindings/gpio/gpio.h>
13 model = "Qualcomm MSM8974";
14 compatible = "qcom,msm8974";
15 interrupt-parent = <&intc>;
23 reg = <0x08000000 0x5100000>;
28 reg = <0x0d100000 0x100000>;
33 reg = <0x0d200000 0xa00000>;
37 adsp_region: adsp@dc00000 {
38 reg = <0x0dc00000 0x1900000>;
43 reg = <0x0f500000 0x500000>;
47 smem_region: smem@fa00000 {
48 reg = <0xfa00000 0x200000>;
53 reg = <0x0fc00000 0x160000>;
58 reg = <0x0fd60000 0x20000>;
63 reg = <0x0fd80000 0x180000>;
71 interrupts = <GIC_PPI 9 0xf04>;
74 compatible = "qcom,krait";
75 enable-method = "qcom,kpss-acc-v2";
78 next-level-cache = <&L2>;
81 cpu-idle-states = <&CPU_SPC>;
85 compatible = "qcom,krait";
86 enable-method = "qcom,kpss-acc-v2";
89 next-level-cache = <&L2>;
92 cpu-idle-states = <&CPU_SPC>;
96 compatible = "qcom,krait";
97 enable-method = "qcom,kpss-acc-v2";
100 next-level-cache = <&L2>;
103 cpu-idle-states = <&CPU_SPC>;
107 compatible = "qcom,krait";
108 enable-method = "qcom,kpss-acc-v2";
111 next-level-cache = <&L2>;
114 cpu-idle-states = <&CPU_SPC>;
118 compatible = "cache";
120 qcom,saw = <&saw_l2>;
125 compatible = "qcom,idle-state-spc",
127 entry-latency-us = <150>;
128 exit-latency-us = <200>;
129 min-residency-us = <2000>;
135 device_type = "memory";
141 polling-delay-passive = <250>;
142 polling-delay = <1000>;
144 thermal-sensors = <&tsens 5>;
148 temperature = <75000>;
153 temperature = <110000>;
161 polling-delay-passive = <250>;
162 polling-delay = <1000>;
164 thermal-sensors = <&tsens 6>;
168 temperature = <75000>;
173 temperature = <110000>;
181 polling-delay-passive = <250>;
182 polling-delay = <1000>;
184 thermal-sensors = <&tsens 7>;
188 temperature = <75000>;
193 temperature = <110000>;
201 polling-delay-passive = <250>;
202 polling-delay = <1000>;
204 thermal-sensors = <&tsens 8>;
208 temperature = <75000>;
213 temperature = <110000>;
222 compatible = "qcom,krait-pmu";
223 interrupts = <GIC_PPI 7 0xf04>;
228 compatible = "fixed-clock";
230 clock-frequency = <19200000>;
233 sleep_clk: sleep_clk {
234 compatible = "fixed-clock";
236 clock-frequency = <32768>;
241 compatible = "arm,armv7-timer";
242 interrupts = <GIC_PPI 2 0xf08>,
246 clock-frequency = <19200000>;
250 compatible = "qcom,msm8974-adsp-pil";
252 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
253 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
254 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
255 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
256 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
257 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
259 cx-supply = <&pm8841_s2>;
261 clocks = <&xo_board>;
264 memory-region = <&adsp_region>;
266 qcom,smem-states = <&adsp_smp2p_out 0>;
267 qcom,smem-state-names = "stop";
271 compatible = "qcom,smem";
273 memory-region = <&smem_region>;
274 qcom,rpm-msg-ram = <&rpm_msg_ram>;
276 hwlocks = <&tcsr_mutex 3>;
280 compatible = "qcom,smp2p";
281 qcom,smem = <443>, <429>;
283 interrupt-parent = <&intc>;
284 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
286 qcom,ipc = <&apcs 8 10>;
288 qcom,local-pid = <0>;
289 qcom,remote-pid = <2>;
291 adsp_smp2p_out: master-kernel {
292 qcom,entry-name = "master-kernel";
293 #qcom,smem-state-cells = <1>;
296 adsp_smp2p_in: slave-kernel {
297 qcom,entry-name = "slave-kernel";
299 interrupt-controller;
300 #interrupt-cells = <2>;
305 compatible = "qcom,smp2p";
306 qcom,smem = <435>, <428>;
308 interrupt-parent = <&intc>;
309 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
311 qcom,ipc = <&apcs 8 14>;
313 qcom,local-pid = <0>;
314 qcom,remote-pid = <1>;
316 modem_smp2p_out: master-kernel {
317 qcom,entry-name = "master-kernel";
318 #qcom,smem-state-cells = <1>;
321 modem_smp2p_in: slave-kernel {
322 qcom,entry-name = "slave-kernel";
324 interrupt-controller;
325 #interrupt-cells = <2>;
330 compatible = "qcom,smp2p";
331 qcom,smem = <451>, <431>;
333 interrupt-parent = <&intc>;
334 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
336 qcom,ipc = <&apcs 8 18>;
338 qcom,local-pid = <0>;
339 qcom,remote-pid = <4>;
341 wcnss_smp2p_out: master-kernel {
342 qcom,entry-name = "master-kernel";
344 #qcom,smem-state-cells = <1>;
347 wcnss_smp2p_in: slave-kernel {
348 qcom,entry-name = "slave-kernel";
350 interrupt-controller;
351 #interrupt-cells = <2>;
356 compatible = "qcom,smsm";
358 #address-cells = <1>;
361 qcom,ipc-1 = <&apcs 8 13>;
362 qcom,ipc-2 = <&apcs 8 9>;
363 qcom,ipc-3 = <&apcs 8 19>;
368 #qcom,smem-state-cells = <1>;
371 modem_smsm: modem@1 {
373 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
375 interrupt-controller;
376 #interrupt-cells = <2>;
381 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
383 interrupt-controller;
384 #interrupt-cells = <2>;
387 wcnss_smsm: wcnss@7 {
389 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
391 interrupt-controller;
392 #interrupt-cells = <2>;
398 compatible = "qcom,scm";
399 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
400 clock-names = "core", "bus", "iface";
405 #address-cells = <1>;
408 compatible = "simple-bus";
410 intc: interrupt-controller@f9000000 {
411 compatible = "qcom,msm-qgic2";
412 interrupt-controller;
413 #interrupt-cells = <3>;
414 reg = <0xf9000000 0x1000>,
418 apcs: syscon@f9011000 {
419 compatible = "syscon";
420 reg = <0xf9011000 0x1000>;
423 qfprom: qfprom@fc4bc000 {
424 #address-cells = <1>;
426 compatible = "qcom,qfprom";
427 reg = <0xfc4bc000 0x1000>;
428 tsens_calib: calib@d0 {
431 tsens_backup: backup@440 {
436 tsens: thermal-sensor@fc4a9000 {
437 compatible = "qcom,msm8974-tsens";
438 reg = <0xfc4a9000 0x1000>, /* TM */
439 <0xfc4a8000 0x1000>; /* SROT */
440 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
441 nvmem-cell-names = "calib", "calib_backup";
442 #qcom,sensors = <11>;
443 #thermal-sensor-cells = <1>;
447 #address-cells = <1>;
450 compatible = "arm,armv7-timer-mem";
451 reg = <0xf9020000 0x1000>;
452 clock-frequency = <19200000>;
456 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
458 reg = <0xf9021000 0x1000>,
464 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
465 reg = <0xf9023000 0x1000>;
471 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
472 reg = <0xf9024000 0x1000>;
478 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
479 reg = <0xf9025000 0x1000>;
485 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
486 reg = <0xf9026000 0x1000>;
492 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
493 reg = <0xf9027000 0x1000>;
499 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
500 reg = <0xf9028000 0x1000>;
505 saw0: power-controller@f9089000 {
506 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
507 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
510 saw1: power-controller@f9099000 {
511 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
512 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
515 saw2: power-controller@f90a9000 {
516 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
517 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
520 saw3: power-controller@f90b9000 {
521 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
522 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
525 saw_l2: power-controller@f9012000 {
526 compatible = "qcom,saw2";
527 reg = <0xf9012000 0x1000>;
531 acc0: clock-controller@f9088000 {
532 compatible = "qcom,kpss-acc-v2";
533 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
536 acc1: clock-controller@f9098000 {
537 compatible = "qcom,kpss-acc-v2";
538 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
541 acc2: clock-controller@f90a8000 {
542 compatible = "qcom,kpss-acc-v2";
543 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
546 acc3: clock-controller@f90b8000 {
547 compatible = "qcom,kpss-acc-v2";
548 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
552 compatible = "qcom,pshold";
553 reg = <0xfc4ab000 0x4>;
556 gcc: clock-controller@fc400000 {
557 compatible = "qcom,gcc-msm8974";
560 #power-domain-cells = <1>;
561 reg = <0xfc400000 0x4000>;
564 tcsr: syscon@fd4a0000 {
565 compatible = "syscon";
566 reg = <0xfd4a0000 0x10000>;
569 tcsr_mutex_block: syscon@fd484000 {
570 compatible = "syscon";
571 reg = <0xfd484000 0x2000>;
574 mmcc: clock-controller@fd8c0000 {
575 compatible = "qcom,mmcc-msm8974";
578 #power-domain-cells = <1>;
579 reg = <0xfd8c0000 0x6000>;
582 tcsr_mutex: tcsr-mutex {
583 compatible = "qcom,tcsr-mutex";
584 syscon = <&tcsr_mutex_block 0 0x80>;
589 rpm_msg_ram: memory@fc428000 {
590 compatible = "qcom,rpm-msg-ram";
591 reg = <0xfc428000 0x4000>;
594 blsp1_uart1: serial@f991d000 {
595 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
596 reg = <0xf991d000 0x1000>;
597 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
599 clock-names = "core", "iface";
603 blsp1_uart2: serial@f991e000 {
604 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
605 reg = <0xf991e000 0x1000>;
606 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
608 clock-names = "core", "iface";
613 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
614 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
615 reg-names = "hc_mem", "core_mem";
616 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
618 interrupt-names = "hc_irq", "pwr_irq";
619 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
620 <&gcc GCC_SDCC1_AHB_CLK>,
622 clock-names = "core", "iface", "xo";
627 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
628 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
629 reg-names = "hc_mem", "core_mem";
630 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
632 interrupt-names = "hc_irq", "pwr_irq";
633 clocks = <&gcc GCC_SDCC3_APPS_CLK>,
634 <&gcc GCC_SDCC3_AHB_CLK>,
636 clock-names = "core", "iface", "xo";
641 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
642 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
643 reg-names = "hc_mem", "core_mem";
644 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
646 interrupt-names = "hc_irq", "pwr_irq";
647 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
648 <&gcc GCC_SDCC2_AHB_CLK>,
650 clock-names = "core", "iface", "xo";
655 compatible = "qcom,ci-hdrc";
656 reg = <0xf9a55000 0x200>,
658 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
660 <&gcc GCC_USB_HS_SYSTEM_CLK>;
661 clock-names = "iface", "core";
662 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
663 assigned-clock-rates = <75000000>;
664 resets = <&gcc GCC_USB_HS_BCR>;
665 reset-names = "core";
668 ahb-burst-config = <0>;
669 phy-names = "usb-phy";
675 compatible = "qcom,usb-hs-phy-msm8974",
678 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
679 clock-names = "ref", "sleep";
680 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
681 reset-names = "phy", "por";
686 compatible = "qcom,usb-hs-phy-msm8974",
689 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
690 clock-names = "ref", "sleep";
691 resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
692 reset-names = "phy", "por";
699 compatible = "qcom,prng";
700 reg = <0xf9bff000 0x200>;
701 clocks = <&gcc GCC_PRNG_AHB_CLK>;
702 clock-names = "core";
705 msmgpio: pinctrl@fd510000 {
706 compatible = "qcom,msm8974-pinctrl";
707 reg = <0xfd510000 0x4000>;
710 interrupt-controller;
711 #interrupt-cells = <2>;
712 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
717 compatible = "qcom,i2c-qup-v2.1.1";
718 reg = <0xf9923000 0x1000>;
719 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
721 clock-names = "core", "iface";
722 #address-cells = <1>;
728 compatible = "qcom,i2c-qup-v2.1.1";
729 reg = <0xf9924000 0x1000>;
730 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
731 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
732 clock-names = "core", "iface";
733 #address-cells = <1>;
737 blsp_i2c3: i2c@f9925000 {
739 compatible = "qcom,i2c-qup-v2.1.1";
740 reg = <0xf9925000 0x1000>;
741 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
742 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
743 clock-names = "core", "iface";
744 #address-cells = <1>;
748 blsp_i2c8: i2c@f9964000 {
750 compatible = "qcom,i2c-qup-v2.1.1";
751 reg = <0xf9964000 0x1000>;
752 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
754 clock-names = "core", "iface";
755 #address-cells = <1>;
759 blsp_i2c11: i2c@f9967000 {
761 compatible = "qcom,i2c-qup-v2.1.1";
762 reg = <0xf9967000 0x1000>;
763 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
765 clock-names = "core", "iface";
766 #address-cells = <1>;
768 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
769 dma-names = "tx", "rx";
772 blsp_i2c12: i2c@f9968000 {
774 compatible = "qcom,i2c-qup-v2.1.1";
775 reg = <0xf9968000 0x1000>;
776 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
778 clock-names = "core", "iface";
779 #address-cells = <1>;
783 spmi_bus: spmi@fc4cf000 {
784 compatible = "qcom,spmi-pmic-arb";
785 reg-names = "core", "intr", "cnfg";
786 reg = <0xfc4cf000 0x1000>,
789 interrupt-names = "periph_irq";
790 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
793 #address-cells = <2>;
795 interrupt-controller;
796 #interrupt-cells = <4>;
799 blsp2_dma: dma-controller@f9944000 {
800 compatible = "qcom,bam-v1.4.0";
801 reg = <0xf9944000 0x19000>;
802 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
804 clock-names = "bam_clk";
810 compatible = "arm,coresight-tmc", "arm,primecell";
811 reg = <0xfc322000 0x1000>;
813 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
814 clock-names = "apb_pclk", "atclk";
819 remote-endpoint = <&replicator_out0>;
826 compatible = "arm,coresight-tpiu", "arm,primecell";
827 reg = <0xfc318000 0x1000>;
829 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
830 clock-names = "apb_pclk", "atclk";
835 remote-endpoint = <&replicator_out1>;
841 replicator@fc31c000 {
842 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
843 reg = <0xfc31c000 0x1000>;
845 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
846 clock-names = "apb_pclk", "atclk";
849 #address-cells = <1>;
854 replicator_out0: endpoint {
855 remote-endpoint = <&etr_in>;
860 replicator_out1: endpoint {
861 remote-endpoint = <&tpiu_in>;
868 replicator_in: endpoint {
869 remote-endpoint = <&etf_out>;
876 compatible = "arm,coresight-tmc", "arm,primecell";
877 reg = <0xfc307000 0x1000>;
879 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
880 clock-names = "apb_pclk", "atclk";
885 remote-endpoint = <&replicator_in>;
893 remote-endpoint = <&merger_out>;
900 compatible = "arm,coresight-funnel", "arm,primecell";
901 reg = <0xfc31b000 0x1000>;
903 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
904 clock-names = "apb_pclk", "atclk";
907 #address-cells = <1>;
911 * Not described input ports:
912 * 0 - connected trought funnel to Audio, Modem and
913 * Resource and Power Manager CPU's
914 * 2...7 - not-connected
918 merger_in1: endpoint {
919 remote-endpoint = <&funnel1_out>;
926 merger_out: endpoint {
927 remote-endpoint = <&etf_in>;
934 compatible = "arm,coresight-funnel", "arm,primecell";
935 reg = <0xfc31a000 0x1000>;
937 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
938 clock-names = "apb_pclk", "atclk";
941 #address-cells = <1>;
945 * Not described input ports:
947 * 1 - connected trought funnel to Multimedia CPU
948 * 2 - connected to Wireless CPU
952 * 7 - connected to STM
956 funnel1_in5: endpoint {
957 remote-endpoint = <&kpss_out>;
964 funnel1_out: endpoint {
965 remote-endpoint = <&merger_in1>;
971 funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
972 compatible = "arm,coresight-funnel", "arm,primecell";
973 reg = <0xfc345000 0x1000>;
975 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
976 clock-names = "apb_pclk", "atclk";
979 #address-cells = <1>;
985 remote-endpoint = <&etm0_out>;
991 remote-endpoint = <&etm1_out>;
997 remote-endpoint = <&etm2_out>;
1002 kpss_in3: endpoint {
1003 remote-endpoint = <&etm3_out>;
1010 kpss_out: endpoint {
1011 remote-endpoint = <&funnel1_in5>;
1018 compatible = "arm,coresight-etm4x", "arm,primecell";
1019 reg = <0xfc33c000 0x1000>;
1021 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1022 clock-names = "apb_pclk", "atclk";
1028 etm0_out: endpoint {
1029 remote-endpoint = <&kpss_in0>;
1036 compatible = "arm,coresight-etm4x", "arm,primecell";
1037 reg = <0xfc33d000 0x1000>;
1039 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1040 clock-names = "apb_pclk", "atclk";
1046 etm1_out: endpoint {
1047 remote-endpoint = <&kpss_in1>;
1054 compatible = "arm,coresight-etm4x", "arm,primecell";
1055 reg = <0xfc33e000 0x1000>;
1057 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1058 clock-names = "apb_pclk", "atclk";
1064 etm2_out: endpoint {
1065 remote-endpoint = <&kpss_in2>;
1072 compatible = "arm,coresight-etm4x", "arm,primecell";
1073 reg = <0xfc33f000 0x1000>;
1075 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1076 clock-names = "apb_pclk", "atclk";
1082 etm3_out: endpoint {
1083 remote-endpoint = <&kpss_in3>;
1091 compatible = "qcom,smd";
1094 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1096 qcom,ipc = <&apcs 8 8>;
1097 qcom,smd-edge = <1>;
1101 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
1103 qcom,ipc = <&apcs 8 12>;
1104 qcom,smd-edge = <0>;
1108 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1109 qcom,ipc = <&apcs 8 0>;
1110 qcom,smd-edge = <15>;
1113 compatible = "qcom,rpm-msm8974";
1114 qcom,smd-channels = "rpm_requests";
1116 rpmcc: clock-controller {
1117 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
1122 compatible = "qcom,rpm-pm8841-regulators";
1135 compatible = "qcom,rpm-pm8941-regulators";
1166 pm8941_lvs1: lvs1 {};
1167 pm8941_lvs2: lvs2 {};
1168 pm8941_lvs3: lvs3 {};
1174 vreg_boost: vreg-boost {
1175 compatible = "regulator-fixed";
1177 regulator-name = "vreg-boost";
1178 regulator-min-microvolt = <3150000>;
1179 regulator-max-microvolt = <3150000>;
1181 regulator-always-on;
1184 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1187 pinctrl-names = "default";
1188 pinctrl-0 = <&boost_bypass_n_pin>;
1190 vreg_vph_pwr: vreg-vph-pwr {
1191 compatible = "regulator-fixed";
1192 regulator-name = "vph-pwr";
1194 regulator-min-microvolt = <3600000>;
1195 regulator-max-microvolt = <3600000>;
1197 regulator-always-on;