3 /include/ "skeleton.dtsi"
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
11 model = "Qualcomm MSM8660";
12 compatible = "qcom,msm8660";
13 interrupt-parent = <&intc>;
20 compatible = "qcom,scorpion";
21 enable-method = "qcom,gcc-msm8660";
24 next-level-cache = <&L2>;
28 compatible = "qcom,scorpion";
29 enable-method = "qcom,gcc-msm8660";
32 next-level-cache = <&L2>;
42 compatible = "qcom,scorpion-mp-pmu";
43 interrupts = <1 9 0x304>;
48 compatible = "fixed-clock";
50 clock-frequency = <19200000>;
54 compatible = "fixed-clock";
56 clock-frequency = <27000000>;
60 compatible = "fixed-clock";
62 clock-frequency = <32768>;
70 compatible = "simple-bus";
72 intc: interrupt-controller@2080000 {
73 compatible = "qcom,msm-8660-qgic";
75 #interrupt-cells = <3>;
76 reg = < 0x02080000 0x1000 >,
77 < 0x02081000 0x1000 >;
81 compatible = "qcom,scss-timer", "qcom,msm-timer";
82 interrupts = <1 0 0x301>,
85 reg = <0x02000000 0x100>;
86 clock-frequency = <27000000>,
88 cpu-offset = <0x40000>;
91 tlmm: pinctrl@800000 {
92 compatible = "qcom,msm8660-pinctrl";
93 reg = <0x800000 0x4000>;
97 interrupts = <0 16 0x4>;
99 #interrupt-cells = <2>;
103 gcc: clock-controller@900000 {
104 compatible = "qcom,gcc-msm8660";
107 reg = <0x900000 0x4000>;
110 gsbi12: gsbi@19c00000 {
111 compatible = "qcom,gsbi-v1.0.0";
113 reg = <0x19c00000 0x100>;
114 clocks = <&gcc GSBI12_H_CLK>;
115 clock-names = "iface";
116 #address-cells = <1>;
120 syscon-tcsr = <&tcsr>;
122 gsbi12_serial: serial@19c40000 {
123 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
124 reg = <0x19c40000 0x1000>,
126 interrupts = <0 195 IRQ_TYPE_NONE>;
127 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
128 clock-names = "core", "iface";
132 gsbi12_i2c: i2c@19c80000 {
133 compatible = "qcom,i2c-qup-v1.1.1";
134 reg = <0x19c80000 0x1000>;
135 interrupts = <0 196 IRQ_TYPE_NONE>;
136 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
137 clock-names = "core", "iface";
138 #address-cells = <1>;
144 external-bus@1a100000 {
145 compatible = "qcom,msm8660-ebi2";
146 #address-cells = <2>;
148 ranges = <0 0x0 0x1a800000 0x00800000>,
149 <1 0x0 0x1b000000 0x00800000>,
150 <2 0x0 0x1b800000 0x00800000>,
151 <3 0x0 0x1d000000 0x08000000>,
152 <4 0x0 0x1c800000 0x00800000>,
153 <5 0x0 0x1c000000 0x00800000>;
154 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
155 reg-names = "ebi2", "xmem";
156 clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
157 clock-names = "ebi2x", "ebi2";
162 compatible = "qcom,ssbi";
163 reg = <0x500000 0x1000>;
164 qcom,controller-type = "pmic-arbiter";
167 compatible = "qcom,pm8058";
168 interrupt-parent = <&tlmm>;
170 #interrupt-cells = <2>;
171 interrupt-controller;
172 #address-cells = <1>;
175 pm8058_gpio: gpio@150 {
176 compatible = "qcom,pm8058-gpio",
179 interrupt-parent = <&pm8058>;
180 interrupts = <192 IRQ_TYPE_NONE>,
229 pm8058_mpps: mpps@50 {
230 compatible = "qcom,pm8058-mpp",
235 interrupt-parent = <&pm8058>;
252 compatible = "qcom,pm8058-pwrkey";
254 interrupt-parent = <&pm8058>;
255 interrupts = <50 1>, <51 1>;
261 compatible = "qcom,pm8058-keypad";
263 interrupt-parent = <&pm8058>;
264 interrupts = <74 1>, <75 1>;
271 compatible = "qcom,pm8058-rtc";
273 interrupt-parent = <&pm8058>;
279 compatible = "qcom,pm8058-vib";
285 l2cc: clock-controller@2082000 {
286 compatible = "syscon";
287 reg = <0x02082000 0x1000>;
291 compatible = "qcom,rpm-msm8660";
292 reg = <0x00104000 0x1000>;
293 qcom,ipc = <&l2cc 0x8 2>;
295 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
296 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
297 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
298 interrupt-names = "ack", "err", "wakeup";
299 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
302 rpmcc: clock-controller {
303 compatible = "qcom,rpmcc-apq8660", "qcom,rpmcc";
308 compatible = "qcom,rpm-pm8901-regulators";
318 /* S0 and S1 Handled as SAW regulators by SPM */
323 pm8901_lvs0: lvs0 {};
324 pm8901_lvs1: lvs1 {};
325 pm8901_lvs2: lvs2 {};
326 pm8901_lvs3: lvs3 {};
332 compatible = "qcom,rpm-pm8058-regulators";
367 pm8058_lvs0: lvs0 {};
368 pm8058_lvs1: lvs1 {};
375 compatible = "simple-bus";
376 #address-cells = <1>;
379 sdcc1: sdcc@12400000 {
381 compatible = "arm,pl18x", "arm,primecell";
382 arm,primecell-periphid = <0x00051180>;
383 reg = <0x12400000 0x8000>;
384 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
385 interrupt-names = "cmd_irq";
386 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
387 clock-names = "mclk", "apb_pclk";
389 max-frequency = <48000000>;
395 sdcc3: sdcc@12180000 {
396 compatible = "arm,pl18x", "arm,primecell";
397 arm,primecell-periphid = <0x00051180>;
399 reg = <0x12180000 0x8000>;
400 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
401 interrupt-names = "cmd_irq";
402 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
403 clock-names = "mclk", "apb_pclk";
407 max-frequency = <48000000>;
411 sdcc5: sdcc@12200000 {
412 compatible = "arm,pl18x", "arm,primecell";
413 arm,primecell-periphid = <0x00051180>;
415 reg = <0x12200000 0x8000>;
416 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
417 interrupt-names = "cmd_irq";
418 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
419 clock-names = "mclk", "apb_pclk";
423 max-frequency = <48000000>;
427 tcsr: syscon@1a400000 {
428 compatible = "qcom,tcsr-msm8660", "syscon";
429 reg = <0x1a400000 0x100>;