1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
14 interrupt-parent = <&intc>;
19 device_type = "memory";
24 compatible = "simple-bus";
29 intc: interrupt-controller@f9000000 {
30 compatible = "qcom,msm-qgic2";
31 reg = <0xf9000000 0x1000>,
34 #interrupt-cells = <3>;
37 gcc: clock-controller@fc400000 {
38 compatible = "qcom,gcc-msm8226";
39 reg = <0xfc400000 0x4000>;
42 #power-domain-cells = <1>;
45 tlmm: pinctrl@fd510000 {
46 compatible = "qcom,msm8226-pinctrl";
47 reg = <0xfd510000 0x4000>;
50 gpio-ranges = <&tlmm 0 0 117>;
52 #interrupt-cells = <2>;
53 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
56 blsp1_uart3: serial@f991f000 {
57 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
58 reg = <0xf991f000 0x1000>;
59 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
60 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
61 clock-names = "core", "iface";
66 compatible = "qcom,pshold";
67 reg = <0xfc4ab000 0x4>;
71 compatible = "qcom,prng";
72 reg = <0xf9bff000 0x200>;
73 clocks = <&gcc GCC_PRNG_AHB_CLK>;
78 compatible = "arm,armv7-timer-mem";
79 reg = <0xf9020000 0x1000>;
86 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
88 reg = <0xf9021000 0x1000>,
94 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
95 reg = <0xf9023000 0x1000>;
101 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
102 reg = <0xf9024000 0x1000>;
108 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
109 reg = <0xf9025000 0x1000>;
115 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
116 reg = <0xf9026000 0x1000>;
122 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
123 reg = <0xf9027000 0x1000>;
129 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
130 reg = <0xf9028000 0x1000>;
137 compatible = "arm,armv7-timer";
138 interrupts = <GIC_PPI 2
139 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
141 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
143 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
145 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;