2 * Device Tree Source for Qualcomm MDM9615 SoC
4 * Copyright (C) 2016 BayLibre, SAS.
5 * Author : Neil Armstrong <narmstrong@baylibre.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
50 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
51 #include <dt-bindings/mfd/qcom-rpm.h>
52 #include <dt-bindings/soc/qcom,gsbi.h>
57 model = "Qualcomm MDM9615";
58 compatible = "qcom,mdm9615";
59 interrupt-parent = <&intc>;
66 compatible = "arm,cortex-a5";
68 next-level-cache = <&L2>;
73 compatible = "arm,cortex-a5-pmu";
74 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
79 compatible = "fixed-clock";
81 clock-frequency = <19200000>;
86 vsdcc_fixed: vsdcc-regulator {
87 compatible = "regulator-fixed";
88 regulator-name = "SDCC Power";
89 regulator-min-microvolt = <2700000>;
90 regulator-max-microvolt = <2700000>;
99 compatible = "simple-bus";
101 L2: cache-controller@2040000 {
102 compatible = "arm,pl310-cache";
103 reg = <0x02040000 0x1000>;
104 arm,data-latency = <2 2 0>;
109 intc: interrupt-controller@2000000 {
110 compatible = "qcom,msm-qgic2";
111 interrupt-controller;
112 #interrupt-cells = <3>;
113 reg = <0x02000000 0x1000>,
118 compatible = "qcom,kpss-timer", "qcom,msm-timer";
119 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
120 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
121 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
122 reg = <0x0200a000 0x100>;
123 clock-frequency = <27000000>,
125 cpu-offset = <0x80000>;
128 msmgpio: pinctrl@800000 {
129 compatible = "qcom,mdm9615-pinctrl";
131 gpio-ranges = <&msmgpio 0 0 88>;
133 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-controller;
135 #interrupt-cells = <2>;
136 reg = <0x800000 0x4000>;
139 gcc: clock-controller@900000 {
140 compatible = "qcom,gcc-mdm9615";
143 reg = <0x900000 0x4000>;
146 lcc: clock-controller@28000000 {
147 compatible = "qcom,lcc-mdm9615";
148 reg = <0x28000000 0x1000>;
153 l2cc: clock-controller@2011000 {
154 compatible = "syscon";
155 reg = <0x02011000 0x1000>;
159 compatible = "qcom,prng";
160 reg = <0x1a500000 0x200>;
161 clocks = <&gcc PRNG_CLK>;
162 clock-names = "core";
163 assigned-clocks = <&gcc PRNG_CLK>;
164 assigned-clock-rates = <32000000>;
167 gsbi2: gsbi@16100000 {
168 compatible = "qcom,gsbi-v1.0.0";
170 reg = <0x16100000 0x100>;
171 clocks = <&gcc GSBI2_H_CLK>;
172 clock-names = "iface";
174 #address-cells = <1>;
178 gsbi2_i2c: i2c@16180000 {
179 compatible = "qcom,i2c-qup-v1.1.1";
180 #address-cells = <1>;
182 reg = <0x16180000 0x1000>;
183 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
186 clock-names = "core", "iface";
191 gsbi3: gsbi@16200000 {
192 compatible = "qcom,gsbi-v1.0.0";
194 reg = <0x16200000 0x100>;
195 clocks = <&gcc GSBI3_H_CLK>;
196 clock-names = "iface";
198 #address-cells = <1>;
202 gsbi3_spi: spi@16280000 {
203 compatible = "qcom,spi-qup-v1.1.1";
204 #address-cells = <1>;
206 reg = <0x16280000 0x1000>;
207 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
208 spi-max-frequency = <24000000>;
210 clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
211 clock-names = "core", "iface";
216 gsbi4: gsbi@16300000 {
217 compatible = "qcom,gsbi-v1.0.0";
219 reg = <0x16300000 0x100>;
220 clocks = <&gcc GSBI4_H_CLK>;
221 clock-names = "iface";
223 #address-cells = <1>;
227 syscon-tcsr = <&tcsr>;
229 gsbi4_serial: serial@16340000 {
230 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
231 reg = <0x16340000 0x1000>,
233 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
235 clock-names = "core", "iface";
240 gsbi5: gsbi@16400000 {
241 compatible = "qcom,gsbi-v1.0.0";
243 reg = <0x16400000 0x100>;
244 clocks = <&gcc GSBI5_H_CLK>;
245 clock-names = "iface";
247 #address-cells = <1>;
251 syscon-tcsr = <&tcsr>;
253 gsbi5_i2c: i2c@16480000 {
254 compatible = "qcom,i2c-qup-v1.1.1";
255 #address-cells = <1>;
257 reg = <0x16480000 0x1000>;
258 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
260 /* QUP clock is not initialized, set rate */
261 assigned-clocks = <&gcc GSBI5_QUP_CLK>;
262 assigned-clock-rates = <24000000>;
264 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
265 clock-names = "core", "iface";
269 gsbi5_serial: serial@16440000 {
270 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
271 reg = <0x16440000 0x1000>,
273 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
275 clock-names = "core", "iface";
281 compatible = "qcom,ssbi";
282 reg = <0x500000 0x1000>;
283 qcom,controller-type = "pmic-arbiter";
286 compatible = "qcom,pm8018", "qcom,pm8921";
287 interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
288 #interrupt-cells = <2>;
289 interrupt-controller;
290 #address-cells = <1>;
294 compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey";
296 interrupt-parent = <&pmicintc>;
297 interrupts = <50 IRQ_TYPE_EDGE_RISING>,
298 <51 IRQ_TYPE_EDGE_RISING>;
304 compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
305 interrupt-parent = <&pmicintc>;
306 interrupts = <24 IRQ_TYPE_NONE>,
318 compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
319 interrupt-parent = <&pmicintc>;
320 interrupts = <39 IRQ_TYPE_EDGE_RISING>;
326 compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
327 interrupt-controller;
328 #interrupt-cells = <2>;
330 gpio-ranges = <&pmicgpio 0 0 6>;
336 sdcc1bam: dma@12182000{
337 compatible = "qcom,bam-v1.3.0";
338 reg = <0x12182000 0x8000>;
339 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&gcc SDC1_H_CLK>;
341 clock-names = "bam_clk";
346 sdcc2bam: dma@12142000{
347 compatible = "qcom,bam-v1.3.0";
348 reg = <0x12142000 0x8000>;
349 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&gcc SDC2_H_CLK>;
351 clock-names = "bam_clk";
357 compatible = "simple-bus";
358 #address-cells = <1>;
361 sdcc1: sdcc@12180000 {
363 compatible = "arm,pl18x", "arm,primecell";
364 arm,primecell-periphid = <0x00051180>;
365 reg = <0x12180000 0x2000>;
366 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
367 interrupt-names = "cmd_irq";
368 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
369 clock-names = "mclk", "apb_pclk";
371 max-frequency = <48000000>;
374 vmmc-supply = <&vsdcc_fixed>;
375 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
376 dma-names = "tx", "rx";
377 assigned-clocks = <&gcc SDC1_CLK>;
378 assigned-clock-rates = <400000>;
381 sdcc2: sdcc@12140000 {
382 compatible = "arm,pl18x", "arm,primecell";
383 arm,primecell-periphid = <0x00051180>;
385 reg = <0x12140000 0x2000>;
386 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
387 interrupt-names = "cmd_irq";
388 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
389 clock-names = "mclk", "apb_pclk";
393 max-frequency = <48000000>;
395 vmmc-supply = <&vsdcc_fixed>;
396 dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
397 dma-names = "tx", "rx";
398 assigned-clocks = <&gcc SDC2_CLK>;
399 assigned-clock-rates = <400000>;
403 tcsr: syscon@1a400000 {
404 compatible = "qcom,tcsr-mdm9615", "syscon";
405 reg = <0x1a400000 0x100>;
409 compatible = "qcom,rpm-mdm9615";
410 reg = <0x108000 0x1000>;
412 qcom,ipc = <&l2cc 0x8 2>;
414 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
415 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
416 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
417 interrupt-names = "ack", "err", "wakeup";
420 compatible = "qcom,rpm-pm8018-regulators";
422 vin_lvs1-supply = <&pm8018_s3>;
424 vdd_l7-supply = <&pm8018_s4>;
425 vdd_l8-supply = <&pm8018_s3>;
426 vdd_l9_l10_l11_l12-supply = <&pm8018_s5>;
430 regulator-min-microvolt = <500000>;
431 regulator-max-microvolt = <1150000>;
432 qcom,switch-mode-frequency = <1600000>;
437 regulator-min-microvolt = <1225000>;
438 regulator-max-microvolt = <1300000>;
439 qcom,switch-mode-frequency = <1600000>;
445 regulator-min-microvolt = <1800000>;
446 regulator-max-microvolt = <1800000>;
447 qcom,switch-mode-frequency = <1600000>;
452 regulator-min-microvolt = <2100000>;
453 regulator-max-microvolt = <2200000>;
454 qcom,switch-mode-frequency = <1600000>;
460 regulator-min-microvolt = <1350000>;
461 regulator-max-microvolt = <1350000>;
462 qcom,switch-mode-frequency = <1600000>;
469 regulator-min-microvolt = <1800000>;
470 regulator-max-microvolt = <1800000>;
476 regulator-min-microvolt = <1800000>;
477 regulator-max-microvolt = <1800000>;
482 regulator-min-microvolt = <3300000>;
483 regulator-max-microvolt = <3300000>;
488 regulator-min-microvolt = <2850000>;
489 regulator-max-microvolt = <2850000>;
494 regulator-min-microvolt = <1800000>;
495 regulator-max-microvolt = <2850000>;
500 regulator-min-microvolt = <1850000>;
501 regulator-max-microvolt = <1900000>;
506 regulator-min-microvolt = <1200000>;
507 regulator-max-microvolt = <1200000>;
512 regulator-min-microvolt = <750000>;
513 regulator-max-microvolt = <1150000>;
518 regulator-min-microvolt = <1050000>;
519 regulator-max-microvolt = <1050000>;
524 regulator-min-microvolt = <1050000>;
525 regulator-max-microvolt = <1050000>;
530 regulator-min-microvolt = <1050000>;
531 regulator-max-microvolt = <1050000>;
536 regulator-min-microvolt = <1850000>;
537 regulator-max-microvolt = <2950000>;
542 regulator-min-microvolt = <2850000>;
543 regulator-max-microvolt = <2850000>;
547 /* Low Voltage Switch */