1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
6 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Qualcomm IPQ8064";
16 compatible = "qcom,ipq8064";
17 interrupt-parent = <&intc>;
24 compatible = "qcom,krait";
25 enable-method = "qcom,kpss-acc-v1";
28 next-level-cache = <&L2>;
34 compatible = "qcom,krait";
35 enable-method = "qcom,kpss-acc-v1";
38 next-level-cache = <&L2>;
50 device_type = "memory";
55 compatible = "qcom,krait-pmu";
56 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
57 IRQ_TYPE_LEVEL_HIGH)>;
66 reg = <0x40000000 0x1000000>;
71 reg = <0x41000000 0x200000>;
78 compatible = "fixed-clock";
80 clock-frequency = <25000000>;
84 compatible = "fixed-clock";
86 clock-frequency = <25000000>;
89 sleep_clk: sleep_clk {
90 compatible = "fixed-clock";
91 clock-frequency = <32768>;
100 compatible = "simple-bus";
103 compatible = "qcom,lpass-cpu";
105 clocks = <&lcc AHBIX_CLK>,
108 clock-names = "ahbix-clk",
111 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
112 interrupt-names = "lpass-irq-lpaif";
113 reg = <0x28100000 0x10000>;
114 reg-names = "lpass-lpaif";
117 qcom_pinmux: pinmux@800000 {
118 compatible = "qcom,ipq8064-pinctrl";
119 reg = <0x800000 0x4000>;
122 gpio-ranges = <&qcom_pinmux 0 0 69>;
124 interrupt-controller;
125 #interrupt-cells = <2>;
126 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
128 pcie0_pins: pcie0_pinmux {
131 function = "pcie1_rst";
132 drive-strength = <12>;
137 pcie1_pins: pcie1_pinmux {
140 function = "pcie2_rst";
141 drive-strength = <12>;
146 pcie2_pins: pcie2_pinmux {
149 function = "pcie3_rst";
150 drive-strength = <12>;
157 pins = "gpio18", "gpio19", "gpio21";
159 drive-strength = <10>;
164 leds_pins: leds_pins {
166 pins = "gpio7", "gpio8", "gpio9",
169 drive-strength = <2>;
175 buttons_pins: buttons_pins {
178 drive-strength = <2>;
184 intc: interrupt-controller@2000000 {
185 compatible = "qcom,msm-qgic2";
186 interrupt-controller;
187 #interrupt-cells = <3>;
188 reg = <0x02000000 0x1000>,
193 compatible = "qcom,kpss-timer",
194 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
195 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
196 IRQ_TYPE_EDGE_RISING)>,
197 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
198 IRQ_TYPE_EDGE_RISING)>,
199 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
200 IRQ_TYPE_EDGE_RISING)>,
201 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
202 IRQ_TYPE_EDGE_RISING)>,
203 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
204 IRQ_TYPE_EDGE_RISING)>;
205 reg = <0x0200a000 0x100>;
206 clock-frequency = <25000000>,
208 clocks = <&sleep_clk>;
209 clock-names = "sleep";
210 cpu-offset = <0x80000>;
213 acc0: clock-controller@2088000 {
214 compatible = "qcom,kpss-acc-v1";
215 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
218 acc1: clock-controller@2098000 {
219 compatible = "qcom,kpss-acc-v1";
220 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
223 saw0: regulator@2089000 {
224 compatible = "qcom,saw2";
225 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
229 saw1: regulator@2099000 {
230 compatible = "qcom,saw2";
231 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
235 gsbi2: gsbi@12480000 {
236 compatible = "qcom,gsbi-v1.0.0";
238 reg = <0x12480000 0x100>;
239 clocks = <&gcc GSBI2_H_CLK>;
240 clock-names = "iface";
241 #address-cells = <1>;
246 syscon-tcsr = <&tcsr>;
249 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
250 reg = <0x12490000 0x1000>,
252 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
254 clock-names = "core", "iface";
259 compatible = "qcom,i2c-qup-v1.1.1";
260 reg = <0x124a0000 0x1000>;
261 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
263 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
264 clock-names = "core", "iface";
267 #address-cells = <1>;
273 gsbi4: gsbi@16300000 {
274 compatible = "qcom,gsbi-v1.0.0";
276 reg = <0x16300000 0x100>;
277 clocks = <&gcc GSBI4_H_CLK>;
278 clock-names = "iface";
279 #address-cells = <1>;
284 syscon-tcsr = <&tcsr>;
286 gsbi4_serial: serial@16340000 {
287 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
288 reg = <0x16340000 0x1000>,
290 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
292 clock-names = "core", "iface";
297 compatible = "qcom,i2c-qup-v1.1.1";
298 reg = <0x16380000 0x1000>;
299 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
302 clock-names = "core", "iface";
305 #address-cells = <1>;
310 gsbi5: gsbi@1a200000 {
311 compatible = "qcom,gsbi-v1.0.0";
313 reg = <0x1a200000 0x100>;
314 clocks = <&gcc GSBI5_H_CLK>;
315 clock-names = "iface";
316 #address-cells = <1>;
321 syscon-tcsr = <&tcsr>;
324 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
325 reg = <0x1a240000 0x1000>,
327 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
329 clock-names = "core", "iface";
334 compatible = "qcom,i2c-qup-v1.1.1";
335 reg = <0x1a280000 0x1000>;
336 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
339 clock-names = "core", "iface";
342 #address-cells = <1>;
347 compatible = "qcom,spi-qup-v1.1.1";
348 reg = <0x1a280000 0x1000>;
349 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
352 clock-names = "core", "iface";
355 #address-cells = <1>;
360 gsbi7: gsbi@16600000 {
362 compatible = "qcom,gsbi-v1.0.0";
364 reg = <0x16600000 0x100>;
365 clocks = <&gcc GSBI7_H_CLK>;
366 clock-names = "iface";
367 #address-cells = <1>;
370 syscon-tcsr = <&tcsr>;
372 gsbi7_serial: serial@16640000 {
373 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
374 reg = <0x16640000 0x1000>,
376 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
378 clock-names = "core", "iface";
383 sata_phy: sata-phy@1b400000 {
384 compatible = "qcom,ipq806x-sata-phy";
385 reg = <0x1b400000 0x200>;
387 clocks = <&gcc SATA_PHY_CFG_CLK>;
395 compatible = "qcom,ipq806x-ahci", "generic-ahci";
396 reg = <0x29000000 0x180>;
398 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&gcc SFAB_SATA_S_H_CLK>,
403 <&gcc SATA_RXOOB_CLK>,
404 <&gcc SATA_PMALIVE_CLK>;
405 clock-names = "slave_face", "iface", "core",
408 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
409 assigned-clock-rates = <100000000>, <100000000>;
412 phy-names = "sata-phy";
417 compatible = "qcom,ssbi";
418 reg = <0x00500000 0x1000>;
419 qcom,controller-type = "pmic-arbiter";
422 gcc: clock-controller@900000 {
423 compatible = "qcom,gcc-ipq8064";
424 reg = <0x00900000 0x4000>;
429 tcsr: syscon@1a400000 {
430 compatible = "qcom,tcsr-ipq8064", "syscon";
431 reg = <0x1a400000 0x100>;
434 lcc: clock-controller@28000000 {
435 compatible = "qcom,lcc-ipq8064";
436 reg = <0x28000000 0x1000>;
441 pcie0: pci@1b500000 {
442 compatible = "qcom,pcie-ipq8064";
443 reg = <0x1b500000 0x1000
446 0x0ff00000 0x100000>;
447 reg-names = "dbi", "elbi", "parf", "config";
449 linux,pci-domain = <0>;
450 bus-range = <0x00 0xff>;
452 #address-cells = <3>;
455 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
456 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
458 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
459 interrupt-names = "msi";
460 #interrupt-cells = <1>;
461 interrupt-map-mask = <0 0 0 0x7>;
462 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
463 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
464 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
465 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
467 clocks = <&gcc PCIE_A_CLK>,
471 <&gcc PCIE_ALT_REF_CLK>;
472 clock-names = "core", "iface", "phy", "aux", "ref";
474 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
475 assigned-clock-rates = <100000000>;
477 resets = <&gcc PCIE_ACLK_RESET>,
478 <&gcc PCIE_HCLK_RESET>,
479 <&gcc PCIE_POR_RESET>,
480 <&gcc PCIE_PCI_RESET>,
481 <&gcc PCIE_PHY_RESET>,
482 <&gcc PCIE_EXT_RESET>;
483 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
485 pinctrl-0 = <&pcie0_pins>;
486 pinctrl-names = "default";
489 perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
492 pcie1: pci@1b700000 {
493 compatible = "qcom,pcie-ipq8064";
494 reg = <0x1b700000 0x1000
497 0x31f00000 0x100000>;
498 reg-names = "dbi", "elbi", "parf", "config";
500 linux,pci-domain = <1>;
501 bus-range = <0x00 0xff>;
503 #address-cells = <3>;
506 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
507 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
509 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
510 interrupt-names = "msi";
511 #interrupt-cells = <1>;
512 interrupt-map-mask = <0 0 0 0x7>;
513 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
514 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
515 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
516 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
518 clocks = <&gcc PCIE_1_A_CLK>,
520 <&gcc PCIE_1_PHY_CLK>,
521 <&gcc PCIE_1_AUX_CLK>,
522 <&gcc PCIE_1_ALT_REF_CLK>;
523 clock-names = "core", "iface", "phy", "aux", "ref";
525 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
526 assigned-clock-rates = <100000000>;
528 resets = <&gcc PCIE_1_ACLK_RESET>,
529 <&gcc PCIE_1_HCLK_RESET>,
530 <&gcc PCIE_1_POR_RESET>,
531 <&gcc PCIE_1_PCI_RESET>,
532 <&gcc PCIE_1_PHY_RESET>,
533 <&gcc PCIE_1_EXT_RESET>;
534 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
536 pinctrl-0 = <&pcie1_pins>;
537 pinctrl-names = "default";
540 perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
543 pcie2: pci@1b900000 {
544 compatible = "qcom,pcie-ipq8064";
545 reg = <0x1b900000 0x1000
548 0x35f00000 0x100000>;
549 reg-names = "dbi", "elbi", "parf", "config";
551 linux,pci-domain = <2>;
552 bus-range = <0x00 0xff>;
554 #address-cells = <3>;
557 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
558 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
560 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
561 interrupt-names = "msi";
562 #interrupt-cells = <1>;
563 interrupt-map-mask = <0 0 0 0x7>;
564 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
565 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
566 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
567 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
569 clocks = <&gcc PCIE_2_A_CLK>,
571 <&gcc PCIE_2_PHY_CLK>,
572 <&gcc PCIE_2_AUX_CLK>,
573 <&gcc PCIE_2_ALT_REF_CLK>;
574 clock-names = "core", "iface", "phy", "aux", "ref";
576 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
577 assigned-clock-rates = <100000000>;
579 resets = <&gcc PCIE_2_ACLK_RESET>,
580 <&gcc PCIE_2_HCLK_RESET>,
581 <&gcc PCIE_2_POR_RESET>,
582 <&gcc PCIE_2_PCI_RESET>,
583 <&gcc PCIE_2_PHY_RESET>,
584 <&gcc PCIE_2_EXT_RESET>;
585 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
587 pinctrl-0 = <&pcie2_pins>;
588 pinctrl-names = "default";
591 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
594 vsdcc_fixed: vsdcc-regulator {
595 compatible = "regulator-fixed";
596 regulator-name = "SDCC Power";
597 regulator-min-microvolt = <3300000>;
598 regulator-max-microvolt = <3300000>;
602 sdcc1bam:dma@12402000 {
603 compatible = "qcom,bam-v1.3.0";
604 reg = <0x12402000 0x8000>;
605 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&gcc SDC1_H_CLK>;
607 clock-names = "bam_clk";
612 sdcc3bam:dma@12182000 {
613 compatible = "qcom,bam-v1.3.0";
614 reg = <0x12182000 0x8000>;
615 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&gcc SDC3_H_CLK>;
617 clock-names = "bam_clk";
623 compatible = "simple-bus";
624 #address-cells = <1>;
630 compatible = "arm,pl18x", "arm,primecell";
631 arm,primecell-periphid = <0x00051180>;
632 reg = <0x12400000 0x2000>;
633 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
634 interrupt-names = "cmd_irq";
635 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
636 clock-names = "mclk", "apb_pclk";
638 max-frequency = <96000000>;
643 vmmc-supply = <&vsdcc_fixed>;
644 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
645 dma-names = "tx", "rx";
649 compatible = "arm,pl18x", "arm,primecell";
650 arm,primecell-periphid = <0x00051180>;
652 reg = <0x12180000 0x2000>;
653 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
654 interrupt-names = "cmd_irq";
655 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
656 clock-names = "mclk", "apb_pclk";
660 max-frequency = <192000000>;
664 vqmmc-supply = <&vsdcc_fixed>;
665 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
666 dma-names = "tx", "rx";