1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
16 model = "Qualcomm Technologies, Inc. IPQ4019";
17 compatible = "qcom,ipq4019";
18 interrupt-parent = <&intc>;
21 #address-cells = <0x1>;
25 smem_region: smem@87e00000 {
26 reg = <0x87e00000 0x080000>;
31 reg = <0x87e80000 0x180000>;
48 compatible = "arm,cortex-a7";
49 enable-method = "qcom,kpss-acc-v2";
50 next-level-cache = <&L2>;
54 clocks = <&gcc GCC_APPS_CLK_SRC>;
55 clock-frequency = <0>;
56 clock-latency = <256000>;
57 operating-points-v2 = <&cpu0_opp_table>;
62 compatible = "arm,cortex-a7";
63 enable-method = "qcom,kpss-acc-v2";
64 next-level-cache = <&L2>;
68 clocks = <&gcc GCC_APPS_CLK_SRC>;
69 clock-frequency = <0>;
70 clock-latency = <256000>;
71 operating-points-v2 = <&cpu0_opp_table>;
76 compatible = "arm,cortex-a7";
77 enable-method = "qcom,kpss-acc-v2";
78 next-level-cache = <&L2>;
82 clocks = <&gcc GCC_APPS_CLK_SRC>;
83 clock-frequency = <0>;
84 clock-latency = <256000>;
85 operating-points-v2 = <&cpu0_opp_table>;
90 compatible = "arm,cortex-a7";
91 enable-method = "qcom,kpss-acc-v2";
92 next-level-cache = <&L2>;
96 clocks = <&gcc GCC_APPS_CLK_SRC>;
97 clock-frequency = <0>;
98 clock-latency = <256000>;
99 operating-points-v2 = <&cpu0_opp_table>;
103 compatible = "cache";
105 qcom,saw = <&saw_l2>;
109 cpu0_opp_table: opp_table0 {
110 compatible = "operating-points-v2";
114 opp-hz = /bits/ 64 <48000000>;
115 clock-latency-ns = <256000>;
118 opp-hz = /bits/ 64 <200000000>;
119 clock-latency-ns = <256000>;
122 opp-hz = /bits/ 64 <500000000>;
123 clock-latency-ns = <256000>;
126 opp-hz = /bits/ 64 <716000000>;
127 clock-latency-ns = <256000>;
132 device_type = "memory";
137 compatible = "arm,cortex-a7-pmu";
138 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
139 IRQ_TYPE_LEVEL_HIGH)>;
143 sleep_clk: sleep_clk {
144 compatible = "fixed-clock";
145 clock-frequency = <32768>;
150 compatible = "fixed-clock";
151 clock-frequency = <48000000>;
158 compatible = "qcom,scm-ipq4019";
163 compatible = "arm,armv7-timer";
164 interrupts = <1 2 0xf08>,
168 clock-frequency = <48000000>;
172 #address-cells = <1>;
175 compatible = "simple-bus";
177 intc: interrupt-controller@b000000 {
178 compatible = "qcom,msm-qgic2";
179 interrupt-controller;
180 #interrupt-cells = <3>;
181 reg = <0x0b000000 0x1000>,
185 gcc: clock-controller@1800000 {
186 compatible = "qcom,gcc-ipq4019";
189 reg = <0x1800000 0x60000>;
193 compatible = "qcom,prng";
194 reg = <0x22000 0x140>;
195 clocks = <&gcc GCC_PRNG_AHB_CLK>;
196 clock-names = "core";
200 tlmm: pinctrl@1000000 {
201 compatible = "qcom,ipq4019-pinctrl";
202 reg = <0x01000000 0x300000>;
204 gpio-ranges = <&tlmm 0 0 100>;
206 interrupt-controller;
207 #interrupt-cells = <2>;
208 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
211 sdhci: sdhci@7824900 {
212 compatible = "qcom,sdhci-msm-v4";
213 reg = <0x7824900 0x11c>, <0x7824000 0x800>;
214 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
215 interrupt-names = "hc_irq", "pwr_irq";
217 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
218 <&gcc GCC_DCD_XO_CLK>;
219 clock-names = "core", "iface", "xo";
223 blsp_dma: dma@7884000 {
224 compatible = "qcom,bam-v1.7.0";
225 reg = <0x07884000 0x23000>;
226 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
228 clock-names = "bam_clk";
234 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
235 compatible = "qcom,spi-qup-v2.2.1";
236 reg = <0x78b5000 0x600>;
237 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
239 <&gcc GCC_BLSP1_AHB_CLK>;
240 clock-names = "core", "iface";
241 #address-cells = <1>;
243 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
244 dma-names = "rx", "tx";
248 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
249 compatible = "qcom,spi-qup-v2.2.1";
250 reg = <0x78b6000 0x600>;
251 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
253 <&gcc GCC_BLSP1_AHB_CLK>;
254 clock-names = "core", "iface";
255 #address-cells = <1>;
257 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
258 dma-names = "rx", "tx";
262 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
263 compatible = "qcom,i2c-qup-v2.2.1";
264 reg = <0x78b7000 0x600>;
265 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
267 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
268 clock-names = "iface", "core";
269 #address-cells = <1>;
271 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
272 dma-names = "rx", "tx";
276 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
277 compatible = "qcom,i2c-qup-v2.2.1";
278 reg = <0x78b8000 0x600>;
279 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
281 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
282 clock-names = "iface", "core";
283 #address-cells = <1>;
285 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
286 dma-names = "rx", "tx";
290 cryptobam: dma@8e04000 {
291 compatible = "qcom,bam-v1.7.0";
292 reg = <0x08e04000 0x20000>;
293 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
295 clock-names = "bam_clk";
298 qcom,controlled-remotely;
303 compatible = "qcom,crypto-v5.1";
304 reg = <0x08e3a000 0x6000>;
305 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
306 <&gcc GCC_CRYPTO_AXI_CLK>,
307 <&gcc GCC_CRYPTO_CLK>;
308 clock-names = "iface", "bus", "core";
309 dmas = <&cryptobam 2>, <&cryptobam 3>;
310 dma-names = "rx", "tx";
314 acc0: clock-controller@b088000 {
315 compatible = "qcom,kpss-acc-v2";
316 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
319 acc1: clock-controller@b098000 {
320 compatible = "qcom,kpss-acc-v2";
321 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
324 acc2: clock-controller@b0a8000 {
325 compatible = "qcom,kpss-acc-v2";
326 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
329 acc3: clock-controller@b0b8000 {
330 compatible = "qcom,kpss-acc-v2";
331 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
334 saw0: regulator@b089000 {
335 compatible = "qcom,saw2";
336 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
340 saw1: regulator@b099000 {
341 compatible = "qcom,saw2";
342 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
346 saw2: regulator@b0a9000 {
347 compatible = "qcom,saw2";
348 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
352 saw3: regulator@b0b9000 {
353 compatible = "qcom,saw2";
354 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
358 saw_l2: regulator@b012000 {
359 compatible = "qcom,saw2";
360 reg = <0xb012000 0x1000>;
364 blsp1_uart1: serial@78af000 {
365 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
366 reg = <0x78af000 0x200>;
367 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
370 <&gcc GCC_BLSP1_AHB_CLK>;
371 clock-names = "core", "iface";
372 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
373 dma-names = "rx", "tx";
376 blsp1_uart2: serial@78b0000 {
377 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
378 reg = <0x78b0000 0x200>;
379 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
382 <&gcc GCC_BLSP1_AHB_CLK>;
383 clock-names = "core", "iface";
384 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
385 dma-names = "rx", "tx";
389 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
390 reg = <0xb017000 0x40>;
391 clocks = <&sleep_clk>;
397 compatible = "qcom,pshold";
398 reg = <0x4ab000 0x4>;
401 pcie0: pci@40000000 {
402 compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
403 reg = <0x40000000 0xf1d
407 reg-names = "dbi", "elbi", "parf", "config";
409 linux,pci-domain = <0>;
410 bus-range = <0x00 0xff>;
412 #address-cells = <3>;
415 ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
416 <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
418 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
419 interrupt-names = "msi";
420 #interrupt-cells = <1>;
421 interrupt-map-mask = <0 0 0 0x7>;
422 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
423 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
424 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
425 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
426 clocks = <&gcc GCC_PCIE_AHB_CLK>,
427 <&gcc GCC_PCIE_AXI_M_CLK>,
428 <&gcc GCC_PCIE_AXI_S_CLK>;
433 resets = <&gcc PCIE_AXI_M_ARES>,
434 <&gcc PCIE_AXI_S_ARES>,
435 <&gcc PCIE_PIPE_ARES>,
436 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
437 <&gcc PCIE_AXI_S_XPU_ARES>,
438 <&gcc PCIE_PARF_XPU_ARES>,
439 <&gcc PCIE_PHY_ARES>,
440 <&gcc PCIE_AXI_M_STICKY_ARES>,
441 <&gcc PCIE_PIPE_STICKY_ARES>,
442 <&gcc PCIE_PWR_ARES>,
443 <&gcc PCIE_AHB_ARES>,
444 <&gcc PCIE_PHY_AHB_ARES>;
445 reset-names = "axi_m",
461 qpic_bam: dma@7984000 {
462 compatible = "qcom,bam-v1.7.0";
463 reg = <0x7984000 0x1a000>;
464 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&gcc GCC_QPIC_CLK>;
466 clock-names = "bam_clk";
472 nand: qpic-nand@79b0000 {
473 compatible = "qcom,ipq4019-nand";
474 reg = <0x79b0000 0x1000>;
475 #address-cells = <1>;
477 clocks = <&gcc GCC_QPIC_CLK>,
478 <&gcc GCC_QPIC_AHB_CLK>;
479 clock-names = "core", "aon";
481 dmas = <&qpic_bam 0>,
484 dma-names = "tx", "rx", "cmd";
490 nand-ecc-strength = <4>;
491 nand-ecc-step-size = <512>;
492 nand-bus-width = <8>;
496 wifi0: wifi@a000000 {
497 compatible = "qcom,ipq4019-wifi";
498 reg = <0xa000000 0x200000>;
499 resets = <&gcc WIFI0_CPU_INIT_RESET>,
500 <&gcc WIFI0_RADIO_SRIF_RESET>,
501 <&gcc WIFI0_RADIO_WARM_RESET>,
502 <&gcc WIFI0_RADIO_COLD_RESET>,
503 <&gcc WIFI0_CORE_WARM_RESET>,
504 <&gcc WIFI0_CORE_COLD_RESET>;
505 reset-names = "wifi_cpu_init", "wifi_radio_srif",
506 "wifi_radio_warm", "wifi_radio_cold",
507 "wifi_core_warm", "wifi_core_cold";
508 clocks = <&gcc GCC_WCSS2G_CLK>,
509 <&gcc GCC_WCSS2G_REF_CLK>,
510 <&gcc GCC_WCSS2G_RTC_CLK>;
511 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
513 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
514 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
515 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
516 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
517 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
518 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
519 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
520 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
521 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
522 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
523 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
524 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
525 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
526 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
527 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
528 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
529 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
530 interrupt-names = "msi0", "msi1", "msi2", "msi3",
531 "msi4", "msi5", "msi6", "msi7",
532 "msi8", "msi9", "msi10", "msi11",
533 "msi12", "msi13", "msi14", "msi15",
538 wifi1: wifi@a800000 {
539 compatible = "qcom,ipq4019-wifi";
540 reg = <0xa800000 0x200000>;
541 resets = <&gcc WIFI1_CPU_INIT_RESET>,
542 <&gcc WIFI1_RADIO_SRIF_RESET>,
543 <&gcc WIFI1_RADIO_WARM_RESET>,
544 <&gcc WIFI1_RADIO_COLD_RESET>,
545 <&gcc WIFI1_CORE_WARM_RESET>,
546 <&gcc WIFI1_CORE_COLD_RESET>;
547 reset-names = "wifi_cpu_init", "wifi_radio_srif",
548 "wifi_radio_warm", "wifi_radio_cold",
549 "wifi_core_warm", "wifi_core_cold";
550 clocks = <&gcc GCC_WCSS5G_CLK>,
551 <&gcc GCC_WCSS5G_REF_CLK>,
552 <&gcc GCC_WCSS5G_RTC_CLK>;
553 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
555 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
556 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
557 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
558 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
559 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
560 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
561 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
562 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
563 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
564 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
565 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
566 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
567 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
568 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
569 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
570 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
571 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
572 interrupt-names = "msi0", "msi1", "msi2", "msi3",
573 "msi4", "msi5", "msi6", "msi7",
574 "msi8", "msi9", "msi10", "msi11",
575 "msi12", "msi13", "msi14", "msi15",