3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
6 #include <dt-bindings/soc/qcom,gsbi.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Qualcomm APQ8064";
11 compatible = "qcom,apq8064";
12 interrupt-parent = <&intc>;
19 compatible = "qcom,krait";
20 enable-method = "qcom,kpss-acc-v1";
23 next-level-cache = <&L2>;
26 cpu-idle-states = <&CPU_SPC>;
30 compatible = "qcom,krait";
31 enable-method = "qcom,kpss-acc-v1";
34 next-level-cache = <&L2>;
37 cpu-idle-states = <&CPU_SPC>;
41 compatible = "qcom,krait";
42 enable-method = "qcom,kpss-acc-v1";
45 next-level-cache = <&L2>;
48 cpu-idle-states = <&CPU_SPC>;
52 compatible = "qcom,krait";
53 enable-method = "qcom,kpss-acc-v1";
56 next-level-cache = <&L2>;
59 cpu-idle-states = <&CPU_SPC>;
69 compatible = "qcom,idle-state-spc",
71 entry-latency-us = <400>;
72 exit-latency-us = <900>;
73 min-residency-us = <3000>;
79 compatible = "qcom,krait-pmu";
80 interrupts = <1 10 0x304>;
87 compatible = "simple-bus";
89 tlmm_pinmux: pinctrl@800000 {
90 compatible = "qcom,apq8064-pinctrl";
91 reg = <0x800000 0x4000>;
96 #interrupt-cells = <2>;
97 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&ps_hold>;
102 sdc4_gpios: sdc4-gpios {
104 pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
112 function = "ps_hold";
117 intc: interrupt-controller@2000000 {
118 compatible = "qcom,msm-qgic2";
119 interrupt-controller;
120 #interrupt-cells = <3>;
121 reg = <0x02000000 0x1000>,
126 compatible = "qcom,kpss-timer", "qcom,msm-timer";
127 interrupts = <1 1 0x301>,
130 reg = <0x0200a000 0x100>;
131 clock-frequency = <27000000>,
133 cpu-offset = <0x80000>;
136 acc0: clock-controller@2088000 {
137 compatible = "qcom,kpss-acc-v1";
138 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
141 acc1: clock-controller@2098000 {
142 compatible = "qcom,kpss-acc-v1";
143 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
146 acc2: clock-controller@20a8000 {
147 compatible = "qcom,kpss-acc-v1";
148 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
151 acc3: clock-controller@20b8000 {
152 compatible = "qcom,kpss-acc-v1";
153 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
156 saw0: power-controller@2089000 {
157 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
158 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
162 saw1: power-controller@2099000 {
163 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
164 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
168 saw2: power-controller@20a9000 {
169 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
170 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
174 saw3: power-controller@20b9000 {
175 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
176 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
180 gsbi1: gsbi@12440000 {
182 compatible = "qcom,gsbi-v1.0.0";
184 reg = <0x12440000 0x100>;
185 clocks = <&gcc GSBI1_H_CLK>;
186 clock-names = "iface";
187 #address-cells = <1>;
191 syscon-tcsr = <&tcsr>;
194 compatible = "qcom,i2c-qup-v1.1.1";
195 reg = <0x12460000 0x1000>;
196 interrupts = <0 194 IRQ_TYPE_NONE>;
197 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
198 clock-names = "core", "iface";
199 #address-cells = <1>;
204 gsbi2: gsbi@12480000 {
206 compatible = "qcom,gsbi-v1.0.0";
208 reg = <0x12480000 0x100>;
209 clocks = <&gcc GSBI2_H_CLK>;
210 clock-names = "iface";
211 #address-cells = <1>;
215 syscon-tcsr = <&tcsr>;
218 compatible = "qcom,i2c-qup-v1.1.1";
219 reg = <0x124a0000 0x1000>;
220 interrupts = <0 196 IRQ_TYPE_NONE>;
221 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
222 clock-names = "core", "iface";
223 #address-cells = <1>;
228 gsbi7: gsbi@16600000 {
230 compatible = "qcom,gsbi-v1.0.0";
232 reg = <0x16600000 0x100>;
233 clocks = <&gcc GSBI7_H_CLK>;
234 clock-names = "iface";
235 #address-cells = <1>;
239 syscon-tcsr = <&tcsr>;
242 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
243 reg = <0x16640000 0x1000>,
245 interrupts = <0 158 0x0>;
246 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
247 clock-names = "core", "iface";
253 compatible = "qcom,ssbi";
254 reg = <0x00500000 0x1000>;
255 qcom,controller-type = "pmic-arbiter";
258 gcc: clock-controller@900000 {
259 compatible = "qcom,gcc-apq8064";
260 reg = <0x00900000 0x4000>;
265 lcc: clock-controller@28000000 {
266 compatible = "qcom,lcc-apq8064";
267 reg = <0x28000000 0x1000>;
272 mmcc: clock-controller@4000000 {
273 compatible = "qcom,mmcc-apq8064";
274 reg = <0x4000000 0x1000>;
279 /* Temporary fixed regulator */
280 vsdcc_fixed: vsdcc-regulator {
281 compatible = "regulator-fixed";
282 regulator-name = "SDCC Power";
283 regulator-min-microvolt = <2700000>;
284 regulator-max-microvolt = <2700000>;
288 sdcc1bam:dma@12402000{
289 compatible = "qcom,bam-v1.3.0";
290 reg = <0x12402000 0x8000>;
291 interrupts = <0 98 0>;
292 clocks = <&gcc SDC1_H_CLK>;
293 clock-names = "bam_clk";
298 sdcc3bam:dma@12182000{
299 compatible = "qcom,bam-v1.3.0";
300 reg = <0x12182000 0x8000>;
301 interrupts = <0 96 0>;
302 clocks = <&gcc SDC3_H_CLK>;
303 clock-names = "bam_clk";
308 sdcc4bam:dma@121c2000{
309 compatible = "qcom,bam-v1.3.0";
310 reg = <0x121c2000 0x8000>;
311 interrupts = <0 95 0>;
312 clocks = <&gcc SDC4_H_CLK>;
313 clock-names = "bam_clk";
319 compatible = "arm,amba-bus";
320 #address-cells = <1>;
323 sdcc1: sdcc@12400000 {
325 compatible = "arm,pl18x", "arm,primecell";
326 arm,primecell-periphid = <0x00051180>;
327 reg = <0x12400000 0x2000>;
328 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
329 interrupt-names = "cmd_irq";
330 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
331 clock-names = "mclk", "apb_pclk";
333 max-frequency = <96000000>;
337 vmmc-supply = <&vsdcc_fixed>;
338 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
339 dma-names = "tx", "rx";
342 sdcc3: sdcc@12180000 {
343 compatible = "arm,pl18x", "arm,primecell";
344 arm,primecell-periphid = <0x00051180>;
346 reg = <0x12180000 0x2000>;
347 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
348 interrupt-names = "cmd_irq";
349 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
350 clock-names = "mclk", "apb_pclk";
354 max-frequency = <192000000>;
356 vmmc-supply = <&vsdcc_fixed>;
357 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
358 dma-names = "tx", "rx";
361 sdcc4: sdcc@121c0000 {
362 compatible = "arm,pl18x", "arm,primecell";
363 arm,primecell-periphid = <0x00051180>;
365 reg = <0x121c0000 0x2000>;
366 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
367 interrupt-names = "cmd_irq";
368 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
369 clock-names = "mclk", "apb_pclk";
373 max-frequency = <48000000>;
374 vmmc-supply = <&vsdcc_fixed>;
375 vqmmc-supply = <&vsdcc_fixed>;
376 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
377 dma-names = "tx", "rx";
378 pinctrl-names = "default";
379 pinctrl-0 = <&sdc4_gpios>;
383 tcsr: syscon@1a400000 {
384 compatible = "qcom,tcsr-apq8064", "syscon";
385 reg = <0x1a400000 0x100>;