1 // SPDX-License-Identifier: GPL-2.0
4 #include "skeleton.dtsi"
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 model = "Qualcomm APQ8064";
14 compatible = "qcom,apq8064";
15 interrupt-parent = <&intc>;
22 smem_region: smem@80000000 {
23 reg = <0x80000000 0x200000>;
27 wcnss_mem: wcnss@8f000000 {
28 reg = <0x8f000000 0x700000>;
38 compatible = "qcom,krait";
39 enable-method = "qcom,kpss-acc-v1";
42 next-level-cache = <&L2>;
45 cpu-idle-states = <&CPU_SPC>;
49 compatible = "qcom,krait";
50 enable-method = "qcom,kpss-acc-v1";
53 next-level-cache = <&L2>;
56 cpu-idle-states = <&CPU_SPC>;
60 compatible = "qcom,krait";
61 enable-method = "qcom,kpss-acc-v1";
64 next-level-cache = <&L2>;
67 cpu-idle-states = <&CPU_SPC>;
71 compatible = "qcom,krait";
72 enable-method = "qcom,kpss-acc-v1";
75 next-level-cache = <&L2>;
78 cpu-idle-states = <&CPU_SPC>;
88 compatible = "qcom,idle-state-spc",
90 entry-latency-us = <400>;
91 exit-latency-us = <900>;
92 min-residency-us = <3000>;
99 polling-delay-passive = <250>;
100 polling-delay = <1000>;
102 thermal-sensors = <&gcc 7>;
103 coefficients = <1199 0>;
107 temperature = <75000>;
112 temperature = <110000>;
120 polling-delay-passive = <250>;
121 polling-delay = <1000>;
123 thermal-sensors = <&gcc 8>;
124 coefficients = <1132 0>;
128 temperature = <75000>;
133 temperature = <110000>;
141 polling-delay-passive = <250>;
142 polling-delay = <1000>;
144 thermal-sensors = <&gcc 9>;
145 coefficients = <1199 0>;
149 temperature = <75000>;
154 temperature = <110000>;
162 polling-delay-passive = <250>;
163 polling-delay = <1000>;
165 thermal-sensors = <&gcc 10>;
166 coefficients = <1132 0>;
170 temperature = <75000>;
175 temperature = <110000>;
184 compatible = "qcom,krait-pmu";
185 interrupts = <1 10 0x304>;
189 cxo_board: cxo_board {
190 compatible = "fixed-clock";
192 clock-frequency = <19200000>;
196 compatible = "fixed-clock";
198 clock-frequency = <27000000>;
201 sleep_clk: sleep_clk {
202 compatible = "fixed-clock";
204 clock-frequency = <32768>;
208 sfpb_mutex: hwmutex {
209 compatible = "qcom,sfpb-mutex";
210 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
215 compatible = "qcom,smem";
216 memory-region = <&smem_region>;
218 hwlocks = <&sfpb_mutex 3>;
222 compatible = "qcom,smd";
225 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
227 qcom,ipc = <&l2cc 8 3>;
234 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
236 qcom,ipc = <&l2cc 8 15>;
243 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
245 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
252 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
254 qcom,ipc = <&l2cc 8 25>;
262 compatible = "qcom,smsm";
264 #address-cells = <1>;
267 qcom,ipc-1 = <&l2cc 8 4>;
268 qcom,ipc-2 = <&l2cc 8 14>;
269 qcom,ipc-3 = <&l2cc 8 23>;
270 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
274 #qcom,smem-state-cells = <1>;
277 modem_smsm: modem@1 {
279 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
281 interrupt-controller;
282 #interrupt-cells = <2>;
287 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
289 interrupt-controller;
290 #interrupt-cells = <2>;
293 wcnss_smsm: wcnss@3 {
295 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
297 interrupt-controller;
298 #interrupt-cells = <2>;
303 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
312 compatible = "qcom,scm-apq8064";
314 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
315 clock-names = "core";
321 * These channels from the ADC are simply hardware monitors.
322 * That is why the ADC is referred to as "HKADC" - HouseKeeping
326 compatible = "iio-hwmon";
327 io-channels = <&xoadc 0x00 0x01>, /* Battery */
328 <&xoadc 0x00 0x02>, /* DC in (charger) */
329 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
330 <&xoadc 0x00 0x0b>, /* Die temperature */
331 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
332 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
333 <&xoadc 0x00 0x0e>; /* Charger temperature */
337 #address-cells = <1>;
340 compatible = "simple-bus";
342 tlmm_pinmux: pinctrl@800000 {
343 compatible = "qcom,apq8064-pinctrl";
344 reg = <0x800000 0x4000>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
350 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&ps_hold>;
356 sfpb_wrapper_mutex: syscon@1200000 {
357 compatible = "syscon";
358 reg = <0x01200000 0x8000>;
361 intc: interrupt-controller@2000000 {
362 compatible = "qcom,msm-qgic2";
363 interrupt-controller;
364 #interrupt-cells = <3>;
365 reg = <0x02000000 0x1000>,
370 compatible = "qcom,kpss-timer",
371 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
372 interrupts = <1 1 0x301>,
375 reg = <0x0200a000 0x100>;
376 clock-frequency = <27000000>,
378 cpu-offset = <0x80000>;
381 acc0: clock-controller@2088000 {
382 compatible = "qcom,kpss-acc-v1";
383 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
386 acc1: clock-controller@2098000 {
387 compatible = "qcom,kpss-acc-v1";
388 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
391 acc2: clock-controller@20a8000 {
392 compatible = "qcom,kpss-acc-v1";
393 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
396 acc3: clock-controller@20b8000 {
397 compatible = "qcom,kpss-acc-v1";
398 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
401 saw0: power-controller@2089000 {
402 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
403 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
407 saw1: power-controller@2099000 {
408 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
409 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
413 saw2: power-controller@20a9000 {
414 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
415 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
419 saw3: power-controller@20b9000 {
420 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
421 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
425 sps_sic_non_secure: sps-sic-non-secure@12100000 {
426 compatible = "syscon";
427 reg = <0x12100000 0x10000>;
430 gsbi1: gsbi@12440000 {
432 compatible = "qcom,gsbi-v1.0.0";
434 reg = <0x12440000 0x100>;
435 clocks = <&gcc GSBI1_H_CLK>;
436 clock-names = "iface";
437 #address-cells = <1>;
441 syscon-tcsr = <&tcsr>;
443 gsbi1_serial: serial@12450000 {
444 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
445 reg = <0x12450000 0x100>,
447 interrupts = <0 193 0x0>;
448 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
449 clock-names = "core", "iface";
453 gsbi1_i2c: i2c@12460000 {
454 compatible = "qcom,i2c-qup-v1.1.1";
455 pinctrl-0 = <&i2c1_pins>;
456 pinctrl-1 = <&i2c1_pins_sleep>;
457 pinctrl-names = "default", "sleep";
458 reg = <0x12460000 0x1000>;
459 interrupts = <0 194 IRQ_TYPE_NONE>;
460 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
461 clock-names = "core", "iface";
462 #address-cells = <1>;
468 gsbi2: gsbi@12480000 {
470 compatible = "qcom,gsbi-v1.0.0";
472 reg = <0x12480000 0x100>;
473 clocks = <&gcc GSBI2_H_CLK>;
474 clock-names = "iface";
475 #address-cells = <1>;
479 syscon-tcsr = <&tcsr>;
481 gsbi2_i2c: i2c@124a0000 {
482 compatible = "qcom,i2c-qup-v1.1.1";
483 reg = <0x124a0000 0x1000>;
484 pinctrl-0 = <&i2c2_pins>;
485 pinctrl-1 = <&i2c2_pins_sleep>;
486 pinctrl-names = "default", "sleep";
487 interrupts = <0 196 IRQ_TYPE_NONE>;
488 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
489 clock-names = "core", "iface";
490 #address-cells = <1>;
495 gsbi3: gsbi@16200000 {
497 compatible = "qcom,gsbi-v1.0.0";
499 reg = <0x16200000 0x100>;
500 clocks = <&gcc GSBI3_H_CLK>;
501 clock-names = "iface";
502 #address-cells = <1>;
505 gsbi3_i2c: i2c@16280000 {
506 compatible = "qcom,i2c-qup-v1.1.1";
507 pinctrl-0 = <&i2c3_pins>;
508 pinctrl-1 = <&i2c3_pins_sleep>;
509 pinctrl-names = "default", "sleep";
510 reg = <0x16280000 0x1000>;
511 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
512 clocks = <&gcc GSBI3_QUP_CLK>,
514 clock-names = "core", "iface";
515 #address-cells = <1>;
520 gsbi4: gsbi@16300000 {
522 compatible = "qcom,gsbi-v1.0.0";
524 reg = <0x16300000 0x03>;
525 clocks = <&gcc GSBI4_H_CLK>;
526 clock-names = "iface";
527 #address-cells = <1>;
531 gsbi4_i2c: i2c@16380000 {
532 compatible = "qcom,i2c-qup-v1.1.1";
533 pinctrl-0 = <&i2c4_pins>;
534 pinctrl-1 = <&i2c4_pins_sleep>;
535 pinctrl-names = "default", "sleep";
536 reg = <0x16380000 0x1000>;
537 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
538 clocks = <&gcc GSBI4_QUP_CLK>,
540 clock-names = "core", "iface";
544 gsbi5: gsbi@1a200000 {
546 compatible = "qcom,gsbi-v1.0.0";
548 reg = <0x1a200000 0x03>;
549 clocks = <&gcc GSBI5_H_CLK>;
550 clock-names = "iface";
551 #address-cells = <1>;
555 gsbi5_serial: serial@1a240000 {
556 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
557 reg = <0x1a240000 0x100>,
559 interrupts = <0 154 0x0>;
560 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
561 clock-names = "core", "iface";
565 gsbi5_spi: spi@1a280000 {
566 compatible = "qcom,spi-qup-v1.1.1";
567 reg = <0x1a280000 0x1000>;
568 interrupts = <0 155 0>;
569 pinctrl-0 = <&spi5_default>;
570 pinctrl-1 = <&spi5_sleep>;
571 pinctrl-names = "default", "sleep";
572 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
573 clock-names = "core", "iface";
575 #address-cells = <1>;
580 gsbi6: gsbi@16500000 {
582 compatible = "qcom,gsbi-v1.0.0";
584 reg = <0x16500000 0x03>;
585 clocks = <&gcc GSBI6_H_CLK>;
586 clock-names = "iface";
587 #address-cells = <1>;
591 gsbi6_serial: serial@16540000 {
592 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
593 reg = <0x16540000 0x100>,
595 interrupts = <0 156 0x0>;
596 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
597 clock-names = "core", "iface";
601 gsbi6_i2c: i2c@16580000 {
602 compatible = "qcom,i2c-qup-v1.1.1";
603 pinctrl-0 = <&i2c6_pins>;
604 pinctrl-1 = <&i2c6_pins_sleep>;
605 pinctrl-names = "default", "sleep";
606 reg = <0x16580000 0x1000>;
607 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
608 clocks = <&gcc GSBI6_QUP_CLK>,
610 clock-names = "core", "iface";
615 gsbi7: gsbi@16600000 {
617 compatible = "qcom,gsbi-v1.0.0";
619 reg = <0x16600000 0x100>;
620 clocks = <&gcc GSBI7_H_CLK>;
621 clock-names = "iface";
622 #address-cells = <1>;
625 syscon-tcsr = <&tcsr>;
627 gsbi7_serial: serial@16640000 {
628 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
629 reg = <0x16640000 0x1000>,
631 interrupts = <0 158 0x0>;
632 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
633 clock-names = "core", "iface";
637 gsbi7_i2c: i2c@16680000 {
638 compatible = "qcom,i2c-qup-v1.1.1";
639 pinctrl-0 = <&i2c7_pins>;
640 pinctrl-1 = <&i2c7_pins_sleep>;
641 pinctrl-names = "default", "sleep";
642 reg = <0x16680000 0x1000>;
643 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
644 clocks = <&gcc GSBI7_QUP_CLK>,
646 clock-names = "core", "iface";
652 compatible = "qcom,prng";
653 reg = <0x1a500000 0x200>;
654 clocks = <&gcc PRNG_CLK>;
655 clock-names = "core";
659 compatible = "qcom,ssbi";
660 reg = <0x00c00000 0x1000>;
661 qcom,controller-type = "pmic-arbiter";
664 compatible = "qcom,pm8821";
665 interrupt-parent = <&tlmm_pinmux>;
666 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
667 #interrupt-cells = <2>;
668 interrupt-controller;
669 #address-cells = <1>;
672 pm8821_mpps: mpps@50 {
673 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
675 interrupts = <24 IRQ_TYPE_NONE>,
686 compatible = "qcom,ssbi";
687 reg = <0x00500000 0x1000>;
688 qcom,controller-type = "pmic-arbiter";
691 compatible = "qcom,pm8921";
692 interrupt-parent = <&tlmm_pinmux>;
694 #interrupt-cells = <2>;
695 interrupt-controller;
696 #address-cells = <1>;
699 pm8921_gpio: gpio@150 {
701 compatible = "qcom,pm8921-gpio",
704 interrupts = <192 IRQ_TYPE_NONE>,
753 pm8921_mpps: mpps@50 {
754 compatible = "qcom,pm8921-mpp",
775 compatible = "qcom,pm8921-rtc";
776 interrupt-parent = <&pmicintc>;
783 compatible = "qcom,pm8921-pwrkey";
785 interrupt-parent = <&pmicintc>;
786 interrupts = <50 1>, <51 1>;
792 compatible = "qcom,pm8921-adc";
794 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
795 #address-cells = <2>;
797 #io-channel-cells = <2>;
799 vcoin: adc-channel@00 {
802 vbat: adc-channel@01 {
805 dcin: adc-channel@02 {
808 vph_pwr: adc-channel@04 {
811 batt_therm: adc-channel@08 {
814 batt_id: adc-channel@09 {
817 usb_vbus: adc-channel@0a {
820 die_temp: adc-channel@0b {
823 ref_625mv: adc-channel@0c {
826 ref_1250mv: adc-channel@0d {
829 chg_temp: adc-channel@0e {
832 ref_muxoff: adc-channel@0f {
839 qfprom: qfprom@700000 {
840 compatible = "qcom,qfprom";
841 reg = <0x00700000 0x1000>;
842 #address-cells = <1>;
848 tsens_backup: backup_calib {
853 gcc: clock-controller@900000 {
854 compatible = "qcom,gcc-apq8064";
855 reg = <0x00900000 0x4000>;
856 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
857 nvmem-cell-names = "calib", "calib_backup";
860 #thermal-sensor-cells = <1>;
863 lcc: clock-controller@28000000 {
864 compatible = "qcom,lcc-apq8064";
865 reg = <0x28000000 0x1000>;
870 mmcc: clock-controller@4000000 {
871 compatible = "qcom,mmcc-apq8064";
872 reg = <0x4000000 0x1000>;
877 l2cc: clock-controller@2011000 {
878 compatible = "syscon";
879 reg = <0x2011000 0x1000>;
883 compatible = "qcom,rpm-apq8064";
884 reg = <0x108000 0x1000>;
885 qcom,ipc = <&l2cc 0x8 2>;
887 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
888 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
889 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
890 interrupt-names = "ack", "err", "wakeup";
892 rpmcc: clock-controller {
893 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
898 compatible = "qcom,rpm-pm8921-regulators";
934 pm8921_lvs1: lvs1 {};
935 pm8921_lvs2: lvs2 {};
936 pm8921_lvs3: lvs3 {};
937 pm8921_lvs4: lvs4 {};
938 pm8921_lvs5: lvs5 {};
939 pm8921_lvs6: lvs6 {};
940 pm8921_lvs7: lvs7 {};
942 pm8921_usb_switch: usb-switch {};
944 pm8921_hdmi_switch: hdmi-switch {
953 compatible = "qcom,ci-hdrc";
954 reg = <0x12500000 0x200>,
956 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
957 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
958 clock-names = "core", "iface";
959 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
960 assigned-clock-rates = <60000000>;
961 resets = <&gcc USB_HS1_RESET>;
962 reset-names = "core";
964 ahb-burst-config = <0>;
965 phys = <&usb_hs1_phy>;
966 phy-names = "usb-phy";
972 compatible = "qcom,usb-hs-phy-apq8064",
974 clocks = <&sleep_clk>, <&cxo_board>;
975 clock-names = "sleep", "ref";
984 compatible = "qcom,ci-hdrc";
985 reg = <0x12520000 0x200>,
987 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
989 clock-names = "core", "iface";
990 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
991 assigned-clock-rates = <60000000>;
992 resets = <&gcc USB_HS3_RESET>;
993 reset-names = "core";
995 ahb-burst-config = <0>;
996 phys = <&usb_hs3_phy>;
997 phy-names = "usb-phy";
1003 compatible = "qcom,usb-hs-phy-apq8064",
1006 clocks = <&sleep_clk>, <&cxo_board>;
1007 clock-names = "sleep", "ref";
1009 reset-names = "por";
1014 usb4: usb@12530000 {
1015 compatible = "qcom,ci-hdrc";
1016 reg = <0x12530000 0x200>,
1018 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
1019 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
1020 clock-names = "core", "iface";
1021 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
1022 assigned-clock-rates = <60000000>;
1023 resets = <&gcc USB_HS4_RESET>;
1024 reset-names = "core";
1026 ahb-burst-config = <0>;
1027 phys = <&usb_hs4_phy>;
1028 phy-names = "usb-phy";
1029 status = "disabled";
1034 compatible = "qcom,usb-hs-phy-apq8064",
1037 clocks = <&sleep_clk>, <&cxo_board>;
1038 clock-names = "sleep", "ref";
1040 reset-names = "por";
1045 sata_phy0: phy@1b400000 {
1046 compatible = "qcom,apq8064-sata-phy";
1047 status = "disabled";
1048 reg = <0x1b400000 0x200>;
1049 reg-names = "phy_mem";
1050 clocks = <&gcc SATA_PHY_CFG_CLK>;
1051 clock-names = "cfg";
1055 sata0: sata@29000000 {
1056 compatible = "qcom,apq8064-ahci", "generic-ahci";
1057 status = "disabled";
1058 reg = <0x29000000 0x180>;
1059 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
1061 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1064 <&gcc SATA_RXOOB_CLK>,
1065 <&gcc SATA_PMALIVE_CLK>;
1066 clock-names = "slave_iface",
1072 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1073 <&gcc SATA_PMALIVE_CLK>;
1074 assigned-clock-rates = <100000000>, <100000000>;
1076 phys = <&sata_phy0>;
1077 phy-names = "sata-phy";
1078 ports-implemented = <0x1>;
1081 /* Temporary fixed regulator */
1082 sdcc1bam:dma@12402000{
1083 compatible = "qcom,bam-v1.3.0";
1084 reg = <0x12402000 0x8000>;
1085 interrupts = <0 98 0>;
1086 clocks = <&gcc SDC1_H_CLK>;
1087 clock-names = "bam_clk";
1092 sdcc3bam:dma@12182000{
1093 compatible = "qcom,bam-v1.3.0";
1094 reg = <0x12182000 0x8000>;
1095 interrupts = <0 96 0>;
1096 clocks = <&gcc SDC3_H_CLK>;
1097 clock-names = "bam_clk";
1102 sdcc4bam:dma@121c2000{
1103 compatible = "qcom,bam-v1.3.0";
1104 reg = <0x121c2000 0x8000>;
1105 interrupts = <0 95 0>;
1106 clocks = <&gcc SDC4_H_CLK>;
1107 clock-names = "bam_clk";
1113 compatible = "simple-bus";
1114 #address-cells = <1>;
1117 sdcc1: sdcc@12400000 {
1118 status = "disabled";
1119 compatible = "arm,pl18x", "arm,primecell";
1120 pinctrl-names = "default";
1121 pinctrl-0 = <&sdcc1_pins>;
1122 arm,primecell-periphid = <0x00051180>;
1123 reg = <0x12400000 0x2000>;
1124 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1125 interrupt-names = "cmd_irq";
1126 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1127 clock-names = "mclk", "apb_pclk";
1129 max-frequency = <96000000>;
1133 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1134 dma-names = "tx", "rx";
1137 sdcc3: sdcc@12180000 {
1138 compatible = "arm,pl18x", "arm,primecell";
1139 arm,primecell-periphid = <0x00051180>;
1140 status = "disabled";
1141 reg = <0x12180000 0x2000>;
1142 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1143 interrupt-names = "cmd_irq";
1144 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1145 clock-names = "mclk", "apb_pclk";
1149 max-frequency = <192000000>;
1151 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1152 dma-names = "tx", "rx";
1155 sdcc4: sdcc@121c0000 {
1156 compatible = "arm,pl18x", "arm,primecell";
1157 arm,primecell-periphid = <0x00051180>;
1158 status = "disabled";
1159 reg = <0x121c0000 0x2000>;
1160 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1161 interrupt-names = "cmd_irq";
1162 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1163 clock-names = "mclk", "apb_pclk";
1167 max-frequency = <48000000>;
1168 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1169 dma-names = "tx", "rx";
1170 pinctrl-names = "default";
1171 pinctrl-0 = <&sdc4_gpios>;
1175 tcsr: syscon@1a400000 {
1176 compatible = "qcom,tcsr-apq8064", "syscon";
1177 reg = <0x1a400000 0x100>;
1180 gpu: adreno-3xx@4300000 {
1181 compatible = "qcom,adreno-3xx";
1182 reg = <0x04300000 0x20000>;
1183 reg-names = "kgsl_3d0_reg_memory";
1184 interrupts = <GIC_SPI 80 0>;
1185 interrupt-names = "kgsl_3d0_irq";
1193 <&mmcc GFX3D_AHB_CLK>,
1194 <&mmcc GFX3D_AXI_CLK>,
1195 <&mmcc MMSS_IMEM_AHB_CLK>;
1196 qcom,chipid = <0x03020002>;
1263 qcom,gpu-pwrlevels {
1264 compatible = "qcom,gpu-pwrlevels";
1265 qcom,gpu-pwrlevel@0 {
1266 qcom,gpu-freq = <450000000>;
1268 qcom,gpu-pwrlevel@1 {
1269 qcom,gpu-freq = <27000000>;
1274 mmss_sfpb: syscon@5700000 {
1275 compatible = "syscon";
1276 reg = <0x5700000 0x70>;
1279 dsi0: mdss_dsi@4700000 {
1280 compatible = "qcom,mdss-dsi-ctrl";
1281 label = "MDSS DSI CTRL->0";
1282 #address-cells = <1>;
1284 interrupts = <GIC_SPI 82 0>;
1285 reg = <0x04700000 0x200>;
1286 reg-names = "dsi_ctrl";
1288 clocks = <&mmcc DSI_M_AHB_CLK>,
1289 <&mmcc DSI_S_AHB_CLK>,
1290 <&mmcc AMP_AHB_CLK>,
1292 <&mmcc DSI1_BYTE_CLK>,
1293 <&mmcc DSI_PIXEL_CLK>,
1294 <&mmcc DSI1_ESC_CLK>;
1295 clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
1296 "src_clk", "byte_clk", "pixel_clk",
1299 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1300 <&mmcc DSI1_ESC_SRC>,
1302 <&mmcc DSI_PIXEL_SRC>;
1303 assigned-clock-parents = <&dsi0_phy 0>,
1307 syscon-sfpb = <&mmss_sfpb>;
1310 #address-cells = <1>;
1321 dsi0_out: endpoint {
1328 dsi0_phy: dsi-phy@4700200 {
1329 compatible = "qcom,dsi-phy-28nm-8960";
1333 reg = <0x04700200 0x100>,
1336 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1337 clock-names = "iface_clk";
1338 clocks = <&mmcc DSI_M_AHB_CLK>;
1342 mdp_port0: iommu@7500000 {
1343 compatible = "qcom,apq8064-iommu";
1349 <&mmcc SMMU_AHB_CLK>,
1350 <&mmcc MDP_AXI_CLK>;
1351 reg = <0x07500000 0x100000>;
1358 mdp_port1: iommu@7600000 {
1359 compatible = "qcom,apq8064-iommu";
1365 <&mmcc SMMU_AHB_CLK>,
1366 <&mmcc MDP_AXI_CLK>;
1367 reg = <0x07600000 0x100000>;
1374 gfx3d: iommu@7c00000 {
1375 compatible = "qcom,apq8064-iommu";
1381 <&mmcc SMMU_AHB_CLK>,
1382 <&mmcc GFX3D_AXI_CLK>;
1383 reg = <0x07c00000 0x100000>;
1390 gfx3d1: iommu@7d00000 {
1391 compatible = "qcom,apq8064-iommu";
1397 <&mmcc SMMU_AHB_CLK>,
1398 <&mmcc GFX3D_AXI_CLK>;
1399 reg = <0x07d00000 0x100000>;
1406 pcie: pci@1b500000 {
1407 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1408 reg = <0x1b500000 0x1000
1411 0x0ff00000 0x100000>;
1412 reg-names = "dbi", "elbi", "parf", "config";
1413 device_type = "pci";
1414 linux,pci-domain = <0>;
1415 bus-range = <0x00 0xff>;
1417 #address-cells = <3>;
1419 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1420 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1421 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1422 interrupt-names = "msi";
1423 #interrupt-cells = <1>;
1424 interrupt-map-mask = <0 0 0 0x7>;
1425 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1426 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1427 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1428 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1429 clocks = <&gcc PCIE_A_CLK>,
1431 <&gcc PCIE_PHY_REF_CLK>;
1432 clock-names = "core", "iface", "phy";
1433 resets = <&gcc PCIE_ACLK_RESET>,
1434 <&gcc PCIE_HCLK_RESET>,
1435 <&gcc PCIE_POR_RESET>,
1436 <&gcc PCIE_PCI_RESET>,
1437 <&gcc PCIE_PHY_RESET>;
1438 reset-names = "axi", "ahb", "por", "pci", "phy";
1439 status = "disabled";
1442 hdmi: hdmi-tx@4a00000 {
1443 compatible = "qcom,hdmi-tx-8960";
1444 pinctrl-names = "default";
1445 pinctrl-0 = <&hdmi_pinctrl>;
1446 reg = <0x04a00000 0x2f0>;
1447 reg-names = "core_physical";
1448 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1449 clocks = <&mmcc HDMI_APP_CLK>,
1450 <&mmcc HDMI_M_AHB_CLK>,
1451 <&mmcc HDMI_S_AHB_CLK>;
1452 clock-names = "core_clk",
1457 phy-names = "hdmi-phy";
1460 #address-cells = <1>;
1471 hdmi_out: endpoint {
1477 hdmi_phy: hdmi-phy@4a00400 {
1478 compatible = "qcom,hdmi-phy-8960";
1479 reg = <0x4a00400 0x60>,
1481 reg-names = "hdmi_phy",
1484 clocks = <&mmcc HDMI_S_AHB_CLK>;
1485 clock-names = "slave_iface_clk";
1490 compatible = "qcom,mdp4";
1491 reg = <0x05100000 0xf0000>;
1492 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1493 clocks = <&mmcc MDP_CLK>,
1494 <&mmcc MDP_AHB_CLK>,
1495 <&mmcc MDP_AXI_CLK>,
1496 <&mmcc MDP_LUT_CLK>,
1497 <&mmcc HDMI_TV_CLK>,
1499 clock-names = "core_clk",
1506 iommus = <&mdp_port0 0
1512 #address-cells = <1>;
1517 mdp_lvds_out: endpoint {
1523 mdp_dsi1_out: endpoint {
1529 mdp_dsi2_out: endpoint {
1535 mdp_dtv_out: endpoint {
1541 riva: riva-pil@3204000 {
1542 compatible = "qcom,riva-pil";
1544 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1545 reg-names = "ccu", "dxe", "pmu";
1547 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1548 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1549 interrupt-names = "wdog", "fatal";
1551 memory-region = <&wcnss_mem>;
1553 vddcx-supply = <&pm8921_s3>;
1554 vddmx-supply = <&pm8921_l24>;
1555 vddpx-supply = <&pm8921_s4>;
1557 status = "disabled";
1560 compatible = "qcom,wcn3660";
1562 clocks = <&cxo_board>;
1565 vddxo-supply = <&pm8921_l4>;
1566 vddrfa-supply = <&pm8921_s2>;
1567 vddpa-supply = <&pm8921_l10>;
1568 vdddig-supply = <&pm8921_lvs2>;
1572 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1574 qcom,ipc = <&l2cc 8 25>;
1575 qcom,smd-edge = <6>;
1580 compatible = "qcom,wcnss";
1581 qcom,smd-channels = "WCNSS_CTRL";
1583 qcom,mmio = <&riva>;
1586 compatible = "qcom,wcnss-bt";
1590 compatible = "qcom,wcnss-wlan";
1592 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1593 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1594 interrupt-names = "tx", "rx";
1596 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1597 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1604 compatible = "coresight-etb10", "arm,primecell";
1605 reg = <0x1a01000 0x1000>;
1607 clocks = <&rpmcc RPM_QDSS_CLK>;
1608 clock-names = "apb_pclk";
1613 remote-endpoint = <&replicator_out0>;
1619 compatible = "arm,coresight-tpiu", "arm,primecell";
1620 reg = <0x1a03000 0x1000>;
1622 clocks = <&rpmcc RPM_QDSS_CLK>;
1623 clock-names = "apb_pclk";
1628 remote-endpoint = <&replicator_out1>;
1634 compatible = "arm,coresight-replicator";
1636 clocks = <&rpmcc RPM_QDSS_CLK>;
1637 clock-names = "apb_pclk";
1640 #address-cells = <1>;
1645 replicator_out0: endpoint {
1646 remote-endpoint = <&etb_in>;
1651 replicator_out1: endpoint {
1652 remote-endpoint = <&tpiu_in>;
1657 replicator_in: endpoint {
1659 remote-endpoint = <&funnel_out>;
1666 compatible = "arm,coresight-funnel", "arm,primecell";
1667 reg = <0x1a04000 0x1000>;
1669 clocks = <&rpmcc RPM_QDSS_CLK>;
1670 clock-names = "apb_pclk";
1673 #address-cells = <1>;
1677 * Not described input ports:
1678 * 2 - connected to STM component
1685 funnel_in0: endpoint {
1687 remote-endpoint = <&etm0_out>;
1692 funnel_in1: endpoint {
1694 remote-endpoint = <&etm1_out>;
1699 funnel_in4: endpoint {
1701 remote-endpoint = <&etm2_out>;
1706 funnel_in5: endpoint {
1708 remote-endpoint = <&etm3_out>;
1713 funnel_out: endpoint {
1714 remote-endpoint = <&replicator_in>;
1721 compatible = "arm,coresight-etm3x", "arm,primecell";
1722 reg = <0x1a1c000 0x1000>;
1724 clocks = <&rpmcc RPM_QDSS_CLK>;
1725 clock-names = "apb_pclk";
1730 etm0_out: endpoint {
1731 remote-endpoint = <&funnel_in0>;
1737 compatible = "arm,coresight-etm3x", "arm,primecell";
1738 reg = <0x1a1d000 0x1000>;
1740 clocks = <&rpmcc RPM_QDSS_CLK>;
1741 clock-names = "apb_pclk";
1746 etm1_out: endpoint {
1747 remote-endpoint = <&funnel_in1>;
1753 compatible = "arm,coresight-etm3x", "arm,primecell";
1754 reg = <0x1a1e000 0x1000>;
1756 clocks = <&rpmcc RPM_QDSS_CLK>;
1757 clock-names = "apb_pclk";
1762 etm2_out: endpoint {
1763 remote-endpoint = <&funnel_in4>;
1769 compatible = "arm,coresight-etm3x", "arm,primecell";
1770 reg = <0x1a1f000 0x1000>;
1772 clocks = <&rpmcc RPM_QDSS_CLK>;
1773 clock-names = "apb_pclk";
1778 etm3_out: endpoint {
1779 remote-endpoint = <&funnel_in5>;
1785 #include "qcom-apq8064-pins.dtsi"