3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 model = "Qualcomm APQ8064";
13 compatible = "qcom,apq8064";
14 interrupt-parent = <&intc>;
21 smem_region: smem@80000000 {
22 reg = <0x80000000 0x200000>;
26 wcnss_mem: wcnss@8f000000 {
27 reg = <0x8f000000 0x700000>;
37 compatible = "qcom,krait";
38 enable-method = "qcom,kpss-acc-v1";
41 next-level-cache = <&L2>;
44 cpu-idle-states = <&CPU_SPC>;
48 compatible = "qcom,krait";
49 enable-method = "qcom,kpss-acc-v1";
52 next-level-cache = <&L2>;
55 cpu-idle-states = <&CPU_SPC>;
59 compatible = "qcom,krait";
60 enable-method = "qcom,kpss-acc-v1";
63 next-level-cache = <&L2>;
66 cpu-idle-states = <&CPU_SPC>;
70 compatible = "qcom,krait";
71 enable-method = "qcom,kpss-acc-v1";
74 next-level-cache = <&L2>;
77 cpu-idle-states = <&CPU_SPC>;
87 compatible = "qcom,idle-state-spc",
89 entry-latency-us = <400>;
90 exit-latency-us = <900>;
91 min-residency-us = <3000>;
98 polling-delay-passive = <250>;
99 polling-delay = <1000>;
101 thermal-sensors = <&gcc 7>;
102 coefficients = <1199 0>;
106 temperature = <75000>;
111 temperature = <110000>;
119 polling-delay-passive = <250>;
120 polling-delay = <1000>;
122 thermal-sensors = <&gcc 8>;
123 coefficients = <1132 0>;
127 temperature = <75000>;
132 temperature = <110000>;
140 polling-delay-passive = <250>;
141 polling-delay = <1000>;
143 thermal-sensors = <&gcc 9>;
144 coefficients = <1199 0>;
148 temperature = <75000>;
153 temperature = <110000>;
161 polling-delay-passive = <250>;
162 polling-delay = <1000>;
164 thermal-sensors = <&gcc 10>;
165 coefficients = <1132 0>;
169 temperature = <75000>;
174 temperature = <110000>;
183 compatible = "qcom,krait-pmu";
184 interrupts = <1 10 0x304>;
188 cxo_board: cxo_board {
189 compatible = "fixed-clock";
191 clock-frequency = <19200000>;
195 compatible = "fixed-clock";
197 clock-frequency = <27000000>;
201 compatible = "fixed-clock";
203 clock-frequency = <32768>;
207 sfpb_mutex: hwmutex {
208 compatible = "qcom,sfpb-mutex";
209 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
214 compatible = "qcom,smem";
215 memory-region = <&smem_region>;
217 hwlocks = <&sfpb_mutex 3>;
221 compatible = "qcom,smd";
224 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
226 qcom,ipc = <&l2cc 8 3>;
233 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
235 qcom,ipc = <&l2cc 8 15>;
242 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
244 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
251 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
253 qcom,ipc = <&l2cc 8 25>;
261 compatible = "qcom,smsm";
263 #address-cells = <1>;
266 qcom,ipc-1 = <&l2cc 8 4>;
267 qcom,ipc-2 = <&l2cc 8 14>;
268 qcom,ipc-3 = <&l2cc 8 23>;
269 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
273 #qcom,smem-state-cells = <1>;
276 modem_smsm: modem@1 {
278 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
280 interrupt-controller;
281 #interrupt-cells = <2>;
286 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
288 interrupt-controller;
289 #interrupt-cells = <2>;
292 wcnss_smsm: wcnss@3 {
294 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
296 interrupt-controller;
297 #interrupt-cells = <2>;
302 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
304 interrupt-controller;
305 #interrupt-cells = <2>;
311 compatible = "qcom,scm-apq8064";
313 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
314 clock-names = "core";
319 #address-cells = <1>;
322 compatible = "simple-bus";
324 tlmm_pinmux: pinctrl@800000 {
325 compatible = "qcom,apq8064-pinctrl";
326 reg = <0x800000 0x4000>;
330 interrupt-controller;
331 #interrupt-cells = <2>;
332 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&ps_hold>;
338 sfpb_wrapper_mutex: syscon@1200000 {
339 compatible = "syscon";
340 reg = <0x01200000 0x8000>;
343 intc: interrupt-controller@2000000 {
344 compatible = "qcom,msm-qgic2";
345 interrupt-controller;
346 #interrupt-cells = <3>;
347 reg = <0x02000000 0x1000>,
352 compatible = "qcom,kpss-timer",
353 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
354 interrupts = <1 1 0x301>,
357 reg = <0x0200a000 0x100>;
358 clock-frequency = <27000000>,
360 cpu-offset = <0x80000>;
363 acc0: clock-controller@2088000 {
364 compatible = "qcom,kpss-acc-v1";
365 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
368 acc1: clock-controller@2098000 {
369 compatible = "qcom,kpss-acc-v1";
370 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
373 acc2: clock-controller@20a8000 {
374 compatible = "qcom,kpss-acc-v1";
375 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
378 acc3: clock-controller@20b8000 {
379 compatible = "qcom,kpss-acc-v1";
380 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
383 saw0: power-controller@2089000 {
384 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
385 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
389 saw1: power-controller@2099000 {
390 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
391 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
395 saw2: power-controller@20a9000 {
396 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
397 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
401 saw3: power-controller@20b9000 {
402 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
403 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
407 sps_sic_non_secure: sps-sic-non-secure@12100000 {
408 compatible = "syscon";
409 reg = <0x12100000 0x10000>;
412 gsbi1: gsbi@12440000 {
414 compatible = "qcom,gsbi-v1.0.0";
416 reg = <0x12440000 0x100>;
417 clocks = <&gcc GSBI1_H_CLK>;
418 clock-names = "iface";
419 #address-cells = <1>;
423 syscon-tcsr = <&tcsr>;
425 gsbi1_serial: serial@12450000 {
426 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
427 reg = <0x12450000 0x100>,
429 interrupts = <0 193 0x0>;
430 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
431 clock-names = "core", "iface";
435 gsbi1_i2c: i2c@12460000 {
436 compatible = "qcom,i2c-qup-v1.1.1";
437 pinctrl-0 = <&i2c1_pins>;
438 pinctrl-1 = <&i2c1_pins_sleep>;
439 pinctrl-names = "default", "sleep";
440 reg = <0x12460000 0x1000>;
441 interrupts = <0 194 IRQ_TYPE_NONE>;
442 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
443 clock-names = "core", "iface";
444 #address-cells = <1>;
450 gsbi2: gsbi@12480000 {
452 compatible = "qcom,gsbi-v1.0.0";
454 reg = <0x12480000 0x100>;
455 clocks = <&gcc GSBI2_H_CLK>;
456 clock-names = "iface";
457 #address-cells = <1>;
461 syscon-tcsr = <&tcsr>;
463 gsbi2_i2c: i2c@124a0000 {
464 compatible = "qcom,i2c-qup-v1.1.1";
465 reg = <0x124a0000 0x1000>;
466 pinctrl-0 = <&i2c2_pins>;
467 pinctrl-1 = <&i2c2_pins_sleep>;
468 pinctrl-names = "default", "sleep";
469 interrupts = <0 196 IRQ_TYPE_NONE>;
470 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
471 clock-names = "core", "iface";
472 #address-cells = <1>;
477 gsbi3: gsbi@16200000 {
479 compatible = "qcom,gsbi-v1.0.0";
481 reg = <0x16200000 0x100>;
482 clocks = <&gcc GSBI3_H_CLK>;
483 clock-names = "iface";
484 #address-cells = <1>;
487 gsbi3_i2c: i2c@16280000 {
488 compatible = "qcom,i2c-qup-v1.1.1";
489 pinctrl-0 = <&i2c3_pins>;
490 pinctrl-1 = <&i2c3_pins_sleep>;
491 pinctrl-names = "default", "sleep";
492 reg = <0x16280000 0x1000>;
493 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
494 clocks = <&gcc GSBI3_QUP_CLK>,
496 clock-names = "core", "iface";
497 #address-cells = <1>;
502 gsbi4: gsbi@16300000 {
504 compatible = "qcom,gsbi-v1.0.0";
506 reg = <0x16300000 0x03>;
507 clocks = <&gcc GSBI4_H_CLK>;
508 clock-names = "iface";
509 #address-cells = <1>;
513 gsbi4_i2c: i2c@16380000 {
514 compatible = "qcom,i2c-qup-v1.1.1";
515 pinctrl-0 = <&i2c4_pins>;
516 pinctrl-1 = <&i2c4_pins_sleep>;
517 pinctrl-names = "default", "sleep";
518 reg = <0x16380000 0x1000>;
519 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
520 clocks = <&gcc GSBI4_QUP_CLK>,
522 clock-names = "core", "iface";
526 gsbi5: gsbi@1a200000 {
528 compatible = "qcom,gsbi-v1.0.0";
530 reg = <0x1a200000 0x03>;
531 clocks = <&gcc GSBI5_H_CLK>;
532 clock-names = "iface";
533 #address-cells = <1>;
537 gsbi5_serial: serial@1a240000 {
538 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
539 reg = <0x1a240000 0x100>,
541 interrupts = <0 154 0x0>;
542 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
543 clock-names = "core", "iface";
547 gsbi5_spi: spi@1a280000 {
548 compatible = "qcom,spi-qup-v1.1.1";
549 reg = <0x1a280000 0x1000>;
550 interrupts = <0 155 0>;
551 pinctrl-0 = <&spi5_default>;
552 pinctrl-1 = <&spi5_sleep>;
553 pinctrl-names = "default", "sleep";
554 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
555 clock-names = "core", "iface";
557 #address-cells = <1>;
562 gsbi6: gsbi@16500000 {
564 compatible = "qcom,gsbi-v1.0.0";
566 reg = <0x16500000 0x03>;
567 clocks = <&gcc GSBI6_H_CLK>;
568 clock-names = "iface";
569 #address-cells = <1>;
573 gsbi6_serial: serial@16540000 {
574 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
575 reg = <0x16540000 0x100>,
577 interrupts = <0 156 0x0>;
578 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
579 clock-names = "core", "iface";
583 gsbi6_i2c: i2c@16580000 {
584 compatible = "qcom,i2c-qup-v1.1.1";
585 pinctrl-0 = <&i2c6_pins>;
586 pinctrl-1 = <&i2c6_pins_sleep>;
587 pinctrl-names = "default", "sleep";
588 reg = <0x16580000 0x1000>;
589 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
590 clocks = <&gcc GSBI6_QUP_CLK>,
592 clock-names = "core", "iface";
596 gsbi7: gsbi@16600000 {
598 compatible = "qcom,gsbi-v1.0.0";
600 reg = <0x16600000 0x100>;
601 clocks = <&gcc GSBI7_H_CLK>;
602 clock-names = "iface";
603 #address-cells = <1>;
606 syscon-tcsr = <&tcsr>;
608 gsbi7_serial: serial@16640000 {
609 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
610 reg = <0x16640000 0x1000>,
612 interrupts = <0 158 0x0>;
613 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
614 clock-names = "core", "iface";
618 gsbi7_i2c: i2c@16680000 {
619 compatible = "qcom,i2c-qup-v1.1.1";
620 pinctrl-0 = <&i2c7_pins>;
621 pinctrl-1 = <&i2c7_pins_sleep>;
622 pinctrl-names = "default", "sleep";
623 reg = <0x16680000 0x1000>;
624 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
625 clocks = <&gcc GSBI7_QUP_CLK>,
627 clock-names = "core", "iface";
633 compatible = "qcom,prng";
634 reg = <0x1a500000 0x200>;
635 clocks = <&gcc PRNG_CLK>;
636 clock-names = "core";
640 compatible = "qcom,ssbi";
641 reg = <0x00c00000 0x1000>;
642 qcom,controller-type = "pmic-arbiter";
645 compatible = "qcom,pm8821";
646 interrupt-parent = <&tlmm_pinmux>;
647 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
648 #interrupt-cells = <2>;
649 interrupt-controller;
650 #address-cells = <1>;
653 pm8821_mpps: mpps@50 {
654 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
656 interrupts = <24 IRQ_TYPE_NONE>,
667 compatible = "qcom,ssbi";
668 reg = <0x00500000 0x1000>;
669 qcom,controller-type = "pmic-arbiter";
672 compatible = "qcom,pm8921";
673 interrupt-parent = <&tlmm_pinmux>;
675 #interrupt-cells = <2>;
676 interrupt-controller;
677 #address-cells = <1>;
680 pm8921_gpio: gpio@150 {
682 compatible = "qcom,pm8921-gpio",
685 interrupts = <192 IRQ_TYPE_NONE>,
734 pm8921_mpps: mpps@50 {
735 compatible = "qcom,pm8921-mpp",
756 compatible = "qcom,pm8921-rtc";
757 interrupt-parent = <&pmicintc>;
764 compatible = "qcom,pm8921-pwrkey";
766 interrupt-parent = <&pmicintc>;
767 interrupts = <50 1>, <51 1>;
774 qfprom: qfprom@700000 {
775 compatible = "qcom,qfprom";
776 reg = <0x00700000 0x1000>;
777 #address-cells = <1>;
783 tsens_backup: backup_calib {
788 gcc: clock-controller@900000 {
789 compatible = "qcom,gcc-apq8064";
790 reg = <0x00900000 0x4000>;
791 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
792 nvmem-cell-names = "calib", "calib_backup";
795 #thermal-sensor-cells = <1>;
798 lcc: clock-controller@28000000 {
799 compatible = "qcom,lcc-apq8064";
800 reg = <0x28000000 0x1000>;
805 mmcc: clock-controller@4000000 {
806 compatible = "qcom,mmcc-apq8064";
807 reg = <0x4000000 0x1000>;
812 l2cc: clock-controller@2011000 {
813 compatible = "syscon";
814 reg = <0x2011000 0x1000>;
818 compatible = "qcom,rpm-apq8064";
819 reg = <0x108000 0x1000>;
820 qcom,ipc = <&l2cc 0x8 2>;
822 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
823 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
824 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
825 interrupt-names = "ack", "err", "wakeup";
827 rpmcc: clock-controller {
828 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
833 compatible = "qcom,rpm-pm8921-regulators";
869 pm8921_lvs1: lvs1 {};
870 pm8921_lvs2: lvs2 {};
871 pm8921_lvs3: lvs3 {};
872 pm8921_lvs4: lvs4 {};
873 pm8921_lvs5: lvs5 {};
874 pm8921_lvs6: lvs6 {};
875 pm8921_lvs7: lvs7 {};
877 pm8921_usb_switch: usb-switch {};
879 pm8921_hdmi_switch: hdmi-switch {
887 usb1_phy: phy@12500000 {
888 compatible = "qcom,usb-otg-ci";
889 reg = <0x12500000 0x400>;
890 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
893 clocks = <&gcc USB_HS1_XCVR_CLK>,
894 <&gcc USB_HS1_H_CLK>;
895 clock-names = "core", "iface";
897 resets = <&gcc USB_HS1_RESET>;
898 reset-names = "link";
901 usb3_phy: phy@12520000 {
902 compatible = "qcom,usb-otg-ci";
903 reg = <0x12520000 0x400>;
904 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
908 clocks = <&gcc USB_HS3_XCVR_CLK>,
909 <&gcc USB_HS3_H_CLK>;
910 clock-names = "core", "iface";
912 resets = <&gcc USB_HS3_RESET>;
913 reset-names = "link";
916 usb4_phy: phy@12530000 {
917 compatible = "qcom,usb-otg-ci";
918 reg = <0x12530000 0x400>;
919 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
923 clocks = <&gcc USB_HS4_XCVR_CLK>,
924 <&gcc USB_HS4_H_CLK>;
925 clock-names = "core", "iface";
927 resets = <&gcc USB_HS4_RESET>;
928 reset-names = "link";
931 gadget1: gadget@12500000 {
932 compatible = "qcom,ci-hdrc";
933 reg = <0x12500000 0x400>;
935 dr_mode = "peripheral";
936 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
937 usb-phy = <&usb1_phy>;
941 compatible = "qcom,ehci-host";
942 reg = <0x12500000 0x400>;
943 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
945 usb-phy = <&usb1_phy>;
949 compatible = "qcom,ehci-host";
950 reg = <0x12520000 0x400>;
951 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
953 usb-phy = <&usb3_phy>;
957 compatible = "qcom,ehci-host";
958 reg = <0x12530000 0x400>;
959 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
961 usb-phy = <&usb4_phy>;
964 sata_phy0: phy@1b400000 {
965 compatible = "qcom,apq8064-sata-phy";
967 reg = <0x1b400000 0x200>;
968 reg-names = "phy_mem";
969 clocks = <&gcc SATA_PHY_CFG_CLK>;
974 sata0: sata@29000000 {
975 compatible = "qcom,apq8064-ahci", "generic-ahci";
977 reg = <0x29000000 0x180>;
978 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
980 clocks = <&gcc SFAB_SATA_S_H_CLK>,
983 <&gcc SATA_RXOOB_CLK>,
984 <&gcc SATA_PMALIVE_CLK>;
985 clock-names = "slave_iface",
991 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
992 <&gcc SATA_PMALIVE_CLK>;
993 assigned-clock-rates = <100000000>, <100000000>;
996 phy-names = "sata-phy";
997 ports-implemented = <0x1>;
1000 /* Temporary fixed regulator */
1001 sdcc1bam:dma@12402000{
1002 compatible = "qcom,bam-v1.3.0";
1003 reg = <0x12402000 0x8000>;
1004 interrupts = <0 98 0>;
1005 clocks = <&gcc SDC1_H_CLK>;
1006 clock-names = "bam_clk";
1011 sdcc3bam:dma@12182000{
1012 compatible = "qcom,bam-v1.3.0";
1013 reg = <0x12182000 0x8000>;
1014 interrupts = <0 96 0>;
1015 clocks = <&gcc SDC3_H_CLK>;
1016 clock-names = "bam_clk";
1021 sdcc4bam:dma@121c2000{
1022 compatible = "qcom,bam-v1.3.0";
1023 reg = <0x121c2000 0x8000>;
1024 interrupts = <0 95 0>;
1025 clocks = <&gcc SDC4_H_CLK>;
1026 clock-names = "bam_clk";
1032 compatible = "simple-bus";
1033 #address-cells = <1>;
1036 sdcc1: sdcc@12400000 {
1037 status = "disabled";
1038 compatible = "arm,pl18x", "arm,primecell";
1039 pinctrl-names = "default";
1040 pinctrl-0 = <&sdcc1_pins>;
1041 arm,primecell-periphid = <0x00051180>;
1042 reg = <0x12400000 0x2000>;
1043 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1044 interrupt-names = "cmd_irq";
1045 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1046 clock-names = "mclk", "apb_pclk";
1048 max-frequency = <96000000>;
1052 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1053 dma-names = "tx", "rx";
1056 sdcc3: sdcc@12180000 {
1057 compatible = "arm,pl18x", "arm,primecell";
1058 arm,primecell-periphid = <0x00051180>;
1059 status = "disabled";
1060 reg = <0x12180000 0x2000>;
1061 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1062 interrupt-names = "cmd_irq";
1063 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1064 clock-names = "mclk", "apb_pclk";
1068 max-frequency = <192000000>;
1070 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1071 dma-names = "tx", "rx";
1074 sdcc4: sdcc@121c0000 {
1075 compatible = "arm,pl18x", "arm,primecell";
1076 arm,primecell-periphid = <0x00051180>;
1077 status = "disabled";
1078 reg = <0x121c0000 0x2000>;
1079 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1080 interrupt-names = "cmd_irq";
1081 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1082 clock-names = "mclk", "apb_pclk";
1086 max-frequency = <48000000>;
1087 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1088 dma-names = "tx", "rx";
1089 pinctrl-names = "default";
1090 pinctrl-0 = <&sdc4_gpios>;
1094 tcsr: syscon@1a400000 {
1095 compatible = "qcom,tcsr-apq8064", "syscon";
1096 reg = <0x1a400000 0x100>;
1099 gpu: adreno-3xx@4300000 {
1100 compatible = "qcom,adreno-3xx";
1101 reg = <0x04300000 0x20000>;
1102 reg-names = "kgsl_3d0_reg_memory";
1103 interrupts = <GIC_SPI 80 0>;
1104 interrupt-names = "kgsl_3d0_irq";
1112 <&mmcc GFX3D_AHB_CLK>,
1113 <&mmcc GFX3D_AXI_CLK>,
1114 <&mmcc MMSS_IMEM_AHB_CLK>;
1115 qcom,chipid = <0x03020002>;
1182 qcom,gpu-pwrlevels {
1183 compatible = "qcom,gpu-pwrlevels";
1184 qcom,gpu-pwrlevel@0 {
1185 qcom,gpu-freq = <450000000>;
1187 qcom,gpu-pwrlevel@1 {
1188 qcom,gpu-freq = <27000000>;
1193 mmss_sfpb: syscon@5700000 {
1194 compatible = "syscon";
1195 reg = <0x5700000 0x70>;
1198 dsi0: mdss_dsi@4700000 {
1199 compatible = "qcom,mdss-dsi-ctrl";
1200 label = "MDSS DSI CTRL->0";
1201 #address-cells = <1>;
1203 interrupts = <GIC_SPI 82 0>;
1204 reg = <0x04700000 0x200>;
1205 reg-names = "dsi_ctrl";
1207 clocks = <&mmcc DSI_M_AHB_CLK>,
1208 <&mmcc DSI_S_AHB_CLK>,
1209 <&mmcc AMP_AHB_CLK>,
1211 <&mmcc DSI1_BYTE_CLK>,
1212 <&mmcc DSI_PIXEL_CLK>,
1213 <&mmcc DSI1_ESC_CLK>;
1214 clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
1215 "src_clk", "byte_clk", "pixel_clk",
1218 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1219 <&mmcc DSI1_ESC_SRC>,
1221 <&mmcc DSI_PIXEL_SRC>;
1222 assigned-clock-parents = <&dsi0_phy 0>,
1226 syscon-sfpb = <&mmss_sfpb>;
1229 #address-cells = <1>;
1240 dsi0_out: endpoint {
1247 dsi0_phy: dsi-phy@4700200 {
1248 compatible = "qcom,dsi-phy-28nm-8960";
1251 reg = <0x04700200 0x100>,
1254 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1255 clock-names = "iface_clk";
1256 clocks = <&mmcc DSI_M_AHB_CLK>;
1260 mdp_port0: iommu@7500000 {
1261 compatible = "qcom,apq8064-iommu";
1267 <&mmcc SMMU_AHB_CLK>,
1268 <&mmcc MDP_AXI_CLK>;
1269 reg = <0x07500000 0x100000>;
1276 mdp_port1: iommu@7600000 {
1277 compatible = "qcom,apq8064-iommu";
1283 <&mmcc SMMU_AHB_CLK>,
1284 <&mmcc MDP_AXI_CLK>;
1285 reg = <0x07600000 0x100000>;
1292 gfx3d: iommu@7c00000 {
1293 compatible = "qcom,apq8064-iommu";
1299 <&mmcc SMMU_AHB_CLK>,
1300 <&mmcc GFX3D_AXI_CLK>;
1301 reg = <0x07c00000 0x100000>;
1308 gfx3d1: iommu@7d00000 {
1309 compatible = "qcom,apq8064-iommu";
1315 <&mmcc SMMU_AHB_CLK>,
1316 <&mmcc GFX3D_AXI_CLK>;
1317 reg = <0x07d00000 0x100000>;
1324 pcie: pci@1b500000 {
1325 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1326 reg = <0x1b500000 0x1000
1329 0x0ff00000 0x100000>;
1330 reg-names = "dbi", "elbi", "parf", "config";
1331 device_type = "pci";
1332 linux,pci-domain = <0>;
1333 bus-range = <0x00 0xff>;
1335 #address-cells = <3>;
1337 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1338 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1339 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1340 interrupt-names = "msi";
1341 #interrupt-cells = <1>;
1342 interrupt-map-mask = <0 0 0 0x7>;
1343 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1344 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1345 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1346 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1347 clocks = <&gcc PCIE_A_CLK>,
1349 <&gcc PCIE_PHY_REF_CLK>;
1350 clock-names = "core", "iface", "phy";
1351 resets = <&gcc PCIE_ACLK_RESET>,
1352 <&gcc PCIE_HCLK_RESET>,
1353 <&gcc PCIE_POR_RESET>,
1354 <&gcc PCIE_PCI_RESET>,
1355 <&gcc PCIE_PHY_RESET>;
1356 reset-names = "axi", "ahb", "por", "pci", "phy";
1357 status = "disabled";
1360 hdmi: hdmi-tx@4a00000 {
1361 compatible = "qcom,hdmi-tx-8960";
1362 pinctrl-names = "default";
1363 pinctrl-0 = <&hdmi_pinctrl>;
1364 reg = <0x04a00000 0x2f0>;
1365 reg-names = "core_physical";
1366 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1367 clocks = <&mmcc HDMI_APP_CLK>,
1368 <&mmcc HDMI_M_AHB_CLK>,
1369 <&mmcc HDMI_S_AHB_CLK>;
1370 clock-names = "core_clk",
1375 phy-names = "hdmi-phy";
1378 #address-cells = <1>;
1389 hdmi_out: endpoint {
1395 hdmi_phy: hdmi-phy@4a00400 {
1396 compatible = "qcom,hdmi-phy-8960";
1397 reg = <0x4a00400 0x60>,
1399 reg-names = "hdmi_phy",
1402 clocks = <&mmcc HDMI_S_AHB_CLK>;
1403 clock-names = "slave_iface_clk";
1407 compatible = "qcom,mdp4";
1408 reg = <0x05100000 0xf0000>;
1409 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1410 clocks = <&mmcc MDP_CLK>,
1411 <&mmcc MDP_AHB_CLK>,
1412 <&mmcc MDP_AXI_CLK>,
1413 <&mmcc MDP_LUT_CLK>,
1414 <&mmcc HDMI_TV_CLK>,
1416 clock-names = "core_clk",
1423 iommus = <&mdp_port0 0
1429 #address-cells = <1>;
1434 mdp_lvds_out: endpoint {
1440 mdp_dsi1_out: endpoint {
1446 mdp_dsi2_out: endpoint {
1452 mdp_dtv_out: endpoint {
1458 riva: riva-pil@3204000 {
1459 compatible = "qcom,riva-pil";
1461 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1462 reg-names = "ccu", "dxe", "pmu";
1464 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1465 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1466 interrupt-names = "wdog", "fatal";
1468 memory-region = <&wcnss_mem>;
1470 vddcx-supply = <&pm8921_s3>;
1471 vddmx-supply = <&pm8921_l24>;
1472 vddpx-supply = <&pm8921_s4>;
1474 status = "disabled";
1477 compatible = "qcom,wcn3660";
1479 clocks = <&cxo_board>;
1482 vddxo-supply = <&pm8921_l4>;
1483 vddrfa-supply = <&pm8921_s2>;
1484 vddpa-supply = <&pm8921_l10>;
1485 vdddig-supply = <&pm8921_lvs2>;
1489 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1491 qcom,ipc = <&l2cc 8 25>;
1492 qcom,smd-edge = <6>;
1497 compatible = "qcom,wcnss";
1498 qcom,smd-channels = "WCNSS_CTRL";
1500 qcom,mmio = <&riva>;
1503 compatible = "qcom,wcnss-bt";
1507 compatible = "qcom,wcnss-wlan";
1509 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1510 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1511 interrupt-names = "tx", "rx";
1513 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1514 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1521 compatible = "coresight-etb10", "arm,primecell";
1522 reg = <0x1a01000 0x1000>;
1524 clocks = <&rpmcc RPM_QDSS_CLK>;
1525 clock-names = "apb_pclk";
1530 remote-endpoint = <&replicator_out0>;
1536 compatible = "arm,coresight-tpiu", "arm,primecell";
1537 reg = <0x1a03000 0x1000>;
1539 clocks = <&rpmcc RPM_QDSS_CLK>;
1540 clock-names = "apb_pclk";
1545 remote-endpoint = <&replicator_out1>;
1551 compatible = "arm,coresight-replicator";
1553 clocks = <&rpmcc RPM_QDSS_CLK>;
1554 clock-names = "apb_pclk";
1557 #address-cells = <1>;
1562 replicator_out0: endpoint {
1563 remote-endpoint = <&etb_in>;
1568 replicator_out1: endpoint {
1569 remote-endpoint = <&tpiu_in>;
1574 replicator_in: endpoint {
1576 remote-endpoint = <&funnel_out>;
1583 compatible = "arm,coresight-funnel", "arm,primecell";
1584 reg = <0x1a04000 0x1000>;
1586 clocks = <&rpmcc RPM_QDSS_CLK>;
1587 clock-names = "apb_pclk";
1590 #address-cells = <1>;
1594 * Not described input ports:
1595 * 2 - connected to STM component
1602 funnel_in0: endpoint {
1604 remote-endpoint = <&etm0_out>;
1609 funnel_in1: endpoint {
1611 remote-endpoint = <&etm1_out>;
1616 funnel_in4: endpoint {
1618 remote-endpoint = <&etm2_out>;
1623 funnel_in5: endpoint {
1625 remote-endpoint = <&etm3_out>;
1630 funnel_out: endpoint {
1631 remote-endpoint = <&replicator_in>;
1638 compatible = "arm,coresight-etm3x", "arm,primecell";
1639 reg = <0x1a1c000 0x1000>;
1641 clocks = <&rpmcc RPM_QDSS_CLK>;
1642 clock-names = "apb_pclk";
1647 etm0_out: endpoint {
1648 remote-endpoint = <&funnel_in0>;
1654 compatible = "arm,coresight-etm3x", "arm,primecell";
1655 reg = <0x1a1d000 0x1000>;
1657 clocks = <&rpmcc RPM_QDSS_CLK>;
1658 clock-names = "apb_pclk";
1663 etm1_out: endpoint {
1664 remote-endpoint = <&funnel_in1>;
1670 compatible = "arm,coresight-etm3x", "arm,primecell";
1671 reg = <0x1a1e000 0x1000>;
1673 clocks = <&rpmcc RPM_QDSS_CLK>;
1674 clock-names = "apb_pclk";
1679 etm2_out: endpoint {
1680 remote-endpoint = <&funnel_in4>;
1686 compatible = "arm,coresight-etm3x", "arm,primecell";
1687 reg = <0x1a1f000 0x1000>;
1689 clocks = <&rpmcc RPM_QDSS_CLK>;
1690 clock-names = "apb_pclk";
1695 etm3_out: endpoint {
1696 remote-endpoint = <&funnel_in5>;
1702 #include "qcom-apq8064-pins.dtsi"