3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,rpmcc.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 model = "Qualcomm APQ8064";
13 compatible = "qcom,apq8064";
14 interrupt-parent = <&intc>;
21 smem_region: smem@80000000 {
22 reg = <0x80000000 0x200000>;
26 wcnss_mem: wcnss@8f000000 {
27 reg = <0x8f000000 0x700000>;
37 compatible = "qcom,krait";
38 enable-method = "qcom,kpss-acc-v1";
41 next-level-cache = <&L2>;
44 cpu-idle-states = <&CPU_SPC>;
48 compatible = "qcom,krait";
49 enable-method = "qcom,kpss-acc-v1";
52 next-level-cache = <&L2>;
55 cpu-idle-states = <&CPU_SPC>;
59 compatible = "qcom,krait";
60 enable-method = "qcom,kpss-acc-v1";
63 next-level-cache = <&L2>;
66 cpu-idle-states = <&CPU_SPC>;
70 compatible = "qcom,krait";
71 enable-method = "qcom,kpss-acc-v1";
74 next-level-cache = <&L2>;
77 cpu-idle-states = <&CPU_SPC>;
87 compatible = "qcom,idle-state-spc",
89 entry-latency-us = <400>;
90 exit-latency-us = <900>;
91 min-residency-us = <3000>;
98 polling-delay-passive = <250>;
99 polling-delay = <1000>;
101 thermal-sensors = <&gcc 7>;
102 coefficients = <1199 0>;
106 temperature = <75000>;
111 temperature = <110000>;
119 polling-delay-passive = <250>;
120 polling-delay = <1000>;
122 thermal-sensors = <&gcc 8>;
123 coefficients = <1132 0>;
127 temperature = <75000>;
132 temperature = <110000>;
140 polling-delay-passive = <250>;
141 polling-delay = <1000>;
143 thermal-sensors = <&gcc 9>;
144 coefficients = <1199 0>;
148 temperature = <75000>;
153 temperature = <110000>;
161 polling-delay-passive = <250>;
162 polling-delay = <1000>;
164 thermal-sensors = <&gcc 10>;
165 coefficients = <1132 0>;
169 temperature = <75000>;
174 temperature = <110000>;
183 compatible = "qcom,krait-pmu";
184 interrupts = <1 10 0x304>;
188 cxo_board: cxo_board {
189 compatible = "fixed-clock";
191 clock-frequency = <19200000>;
195 compatible = "fixed-clock";
197 clock-frequency = <27000000>;
200 sleep_clk: sleep_clk {
201 compatible = "fixed-clock";
203 clock-frequency = <32768>;
207 sfpb_mutex: hwmutex {
208 compatible = "qcom,sfpb-mutex";
209 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
214 compatible = "qcom,smem";
215 memory-region = <&smem_region>;
217 hwlocks = <&sfpb_mutex 3>;
221 compatible = "qcom,smd";
224 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
226 qcom,ipc = <&l2cc 8 3>;
233 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
235 qcom,ipc = <&l2cc 8 15>;
242 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
244 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
251 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
253 qcom,ipc = <&l2cc 8 25>;
261 compatible = "qcom,smsm";
263 #address-cells = <1>;
266 qcom,ipc-1 = <&l2cc 8 4>;
267 qcom,ipc-2 = <&l2cc 8 14>;
268 qcom,ipc-3 = <&l2cc 8 23>;
269 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
273 #qcom,smem-state-cells = <1>;
276 modem_smsm: modem@1 {
278 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
280 interrupt-controller;
281 #interrupt-cells = <2>;
286 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
288 interrupt-controller;
289 #interrupt-cells = <2>;
292 wcnss_smsm: wcnss@3 {
294 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
296 interrupt-controller;
297 #interrupt-cells = <2>;
302 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
304 interrupt-controller;
305 #interrupt-cells = <2>;
311 compatible = "qcom,scm-apq8064";
313 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
314 clock-names = "core";
319 #address-cells = <1>;
322 compatible = "simple-bus";
324 tlmm_pinmux: pinctrl@800000 {
325 compatible = "qcom,apq8064-pinctrl";
326 reg = <0x800000 0x4000>;
330 interrupt-controller;
331 #interrupt-cells = <2>;
332 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&ps_hold>;
338 sfpb_wrapper_mutex: syscon@1200000 {
339 compatible = "syscon";
340 reg = <0x01200000 0x8000>;
343 intc: interrupt-controller@2000000 {
344 compatible = "qcom,msm-qgic2";
345 interrupt-controller;
346 #interrupt-cells = <3>;
347 reg = <0x02000000 0x1000>,
352 compatible = "qcom,kpss-timer",
353 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
354 interrupts = <1 1 0x301>,
357 reg = <0x0200a000 0x100>;
358 clock-frequency = <27000000>,
360 cpu-offset = <0x80000>;
363 acc0: clock-controller@2088000 {
364 compatible = "qcom,kpss-acc-v1";
365 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
368 acc1: clock-controller@2098000 {
369 compatible = "qcom,kpss-acc-v1";
370 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
373 acc2: clock-controller@20a8000 {
374 compatible = "qcom,kpss-acc-v1";
375 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
378 acc3: clock-controller@20b8000 {
379 compatible = "qcom,kpss-acc-v1";
380 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
383 saw0: power-controller@2089000 {
384 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
385 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
389 saw1: power-controller@2099000 {
390 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
391 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
395 saw2: power-controller@20a9000 {
396 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
397 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
401 saw3: power-controller@20b9000 {
402 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
403 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
407 sps_sic_non_secure: sps-sic-non-secure@12100000 {
408 compatible = "syscon";
409 reg = <0x12100000 0x10000>;
412 gsbi1: gsbi@12440000 {
414 compatible = "qcom,gsbi-v1.0.0";
416 reg = <0x12440000 0x100>;
417 clocks = <&gcc GSBI1_H_CLK>;
418 clock-names = "iface";
419 #address-cells = <1>;
423 syscon-tcsr = <&tcsr>;
425 gsbi1_serial: serial@12450000 {
426 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
427 reg = <0x12450000 0x100>,
429 interrupts = <0 193 0x0>;
430 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
431 clock-names = "core", "iface";
435 gsbi1_i2c: i2c@12460000 {
436 compatible = "qcom,i2c-qup-v1.1.1";
437 pinctrl-0 = <&i2c1_pins>;
438 pinctrl-1 = <&i2c1_pins_sleep>;
439 pinctrl-names = "default", "sleep";
440 reg = <0x12460000 0x1000>;
441 interrupts = <0 194 IRQ_TYPE_NONE>;
442 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
443 clock-names = "core", "iface";
444 #address-cells = <1>;
450 gsbi2: gsbi@12480000 {
452 compatible = "qcom,gsbi-v1.0.0";
454 reg = <0x12480000 0x100>;
455 clocks = <&gcc GSBI2_H_CLK>;
456 clock-names = "iface";
457 #address-cells = <1>;
461 syscon-tcsr = <&tcsr>;
463 gsbi2_i2c: i2c@124a0000 {
464 compatible = "qcom,i2c-qup-v1.1.1";
465 reg = <0x124a0000 0x1000>;
466 pinctrl-0 = <&i2c2_pins>;
467 pinctrl-1 = <&i2c2_pins_sleep>;
468 pinctrl-names = "default", "sleep";
469 interrupts = <0 196 IRQ_TYPE_NONE>;
470 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
471 clock-names = "core", "iface";
472 #address-cells = <1>;
477 gsbi3: gsbi@16200000 {
479 compatible = "qcom,gsbi-v1.0.0";
481 reg = <0x16200000 0x100>;
482 clocks = <&gcc GSBI3_H_CLK>;
483 clock-names = "iface";
484 #address-cells = <1>;
487 gsbi3_i2c: i2c@16280000 {
488 compatible = "qcom,i2c-qup-v1.1.1";
489 pinctrl-0 = <&i2c3_pins>;
490 pinctrl-1 = <&i2c3_pins_sleep>;
491 pinctrl-names = "default", "sleep";
492 reg = <0x16280000 0x1000>;
493 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
494 clocks = <&gcc GSBI3_QUP_CLK>,
496 clock-names = "core", "iface";
497 #address-cells = <1>;
502 gsbi4: gsbi@16300000 {
504 compatible = "qcom,gsbi-v1.0.0";
506 reg = <0x16300000 0x03>;
507 clocks = <&gcc GSBI4_H_CLK>;
508 clock-names = "iface";
509 #address-cells = <1>;
513 gsbi4_i2c: i2c@16380000 {
514 compatible = "qcom,i2c-qup-v1.1.1";
515 pinctrl-0 = <&i2c4_pins>;
516 pinctrl-1 = <&i2c4_pins_sleep>;
517 pinctrl-names = "default", "sleep";
518 reg = <0x16380000 0x1000>;
519 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
520 clocks = <&gcc GSBI4_QUP_CLK>,
522 clock-names = "core", "iface";
526 gsbi5: gsbi@1a200000 {
528 compatible = "qcom,gsbi-v1.0.0";
530 reg = <0x1a200000 0x03>;
531 clocks = <&gcc GSBI5_H_CLK>;
532 clock-names = "iface";
533 #address-cells = <1>;
537 gsbi5_serial: serial@1a240000 {
538 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
539 reg = <0x1a240000 0x100>,
541 interrupts = <0 154 0x0>;
542 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
543 clock-names = "core", "iface";
547 gsbi5_spi: spi@1a280000 {
548 compatible = "qcom,spi-qup-v1.1.1";
549 reg = <0x1a280000 0x1000>;
550 interrupts = <0 155 0>;
551 pinctrl-0 = <&spi5_default>;
552 pinctrl-1 = <&spi5_sleep>;
553 pinctrl-names = "default", "sleep";
554 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
555 clock-names = "core", "iface";
557 #address-cells = <1>;
562 gsbi6: gsbi@16500000 {
564 compatible = "qcom,gsbi-v1.0.0";
566 reg = <0x16500000 0x03>;
567 clocks = <&gcc GSBI6_H_CLK>;
568 clock-names = "iface";
569 #address-cells = <1>;
573 gsbi6_serial: serial@16540000 {
574 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
575 reg = <0x16540000 0x100>,
577 interrupts = <0 156 0x0>;
578 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
579 clock-names = "core", "iface";
583 gsbi6_i2c: i2c@16580000 {
584 compatible = "qcom,i2c-qup-v1.1.1";
585 pinctrl-0 = <&i2c6_pins>;
586 pinctrl-1 = <&i2c6_pins_sleep>;
587 pinctrl-names = "default", "sleep";
588 reg = <0x16580000 0x1000>;
589 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
590 clocks = <&gcc GSBI6_QUP_CLK>,
592 clock-names = "core", "iface";
597 gsbi7: gsbi@16600000 {
599 compatible = "qcom,gsbi-v1.0.0";
601 reg = <0x16600000 0x100>;
602 clocks = <&gcc GSBI7_H_CLK>;
603 clock-names = "iface";
604 #address-cells = <1>;
607 syscon-tcsr = <&tcsr>;
609 gsbi7_serial: serial@16640000 {
610 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
611 reg = <0x16640000 0x1000>,
613 interrupts = <0 158 0x0>;
614 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
615 clock-names = "core", "iface";
619 gsbi7_i2c: i2c@16680000 {
620 compatible = "qcom,i2c-qup-v1.1.1";
621 pinctrl-0 = <&i2c7_pins>;
622 pinctrl-1 = <&i2c7_pins_sleep>;
623 pinctrl-names = "default", "sleep";
624 reg = <0x16680000 0x1000>;
625 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
626 clocks = <&gcc GSBI7_QUP_CLK>,
628 clock-names = "core", "iface";
634 compatible = "qcom,prng";
635 reg = <0x1a500000 0x200>;
636 clocks = <&gcc PRNG_CLK>;
637 clock-names = "core";
641 compatible = "qcom,ssbi";
642 reg = <0x00c00000 0x1000>;
643 qcom,controller-type = "pmic-arbiter";
646 compatible = "qcom,pm8821";
647 interrupt-parent = <&tlmm_pinmux>;
648 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
649 #interrupt-cells = <2>;
650 interrupt-controller;
651 #address-cells = <1>;
654 pm8821_mpps: mpps@50 {
655 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
657 interrupts = <24 IRQ_TYPE_NONE>,
668 compatible = "qcom,ssbi";
669 reg = <0x00500000 0x1000>;
670 qcom,controller-type = "pmic-arbiter";
673 compatible = "qcom,pm8921";
674 interrupt-parent = <&tlmm_pinmux>;
676 #interrupt-cells = <2>;
677 interrupt-controller;
678 #address-cells = <1>;
681 pm8921_gpio: gpio@150 {
683 compatible = "qcom,pm8921-gpio",
686 interrupts = <192 IRQ_TYPE_NONE>,
735 pm8921_mpps: mpps@50 {
736 compatible = "qcom,pm8921-mpp",
757 compatible = "qcom,pm8921-rtc";
758 interrupt-parent = <&pmicintc>;
765 compatible = "qcom,pm8921-pwrkey";
767 interrupt-parent = <&pmicintc>;
768 interrupts = <50 1>, <51 1>;
775 qfprom: qfprom@700000 {
776 compatible = "qcom,qfprom";
777 reg = <0x00700000 0x1000>;
778 #address-cells = <1>;
784 tsens_backup: backup_calib {
789 gcc: clock-controller@900000 {
790 compatible = "qcom,gcc-apq8064";
791 reg = <0x00900000 0x4000>;
792 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
793 nvmem-cell-names = "calib", "calib_backup";
796 #thermal-sensor-cells = <1>;
799 lcc: clock-controller@28000000 {
800 compatible = "qcom,lcc-apq8064";
801 reg = <0x28000000 0x1000>;
806 mmcc: clock-controller@4000000 {
807 compatible = "qcom,mmcc-apq8064";
808 reg = <0x4000000 0x1000>;
813 l2cc: clock-controller@2011000 {
814 compatible = "syscon";
815 reg = <0x2011000 0x1000>;
819 compatible = "qcom,rpm-apq8064";
820 reg = <0x108000 0x1000>;
821 qcom,ipc = <&l2cc 0x8 2>;
823 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
824 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
825 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
826 interrupt-names = "ack", "err", "wakeup";
828 rpmcc: clock-controller {
829 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
834 compatible = "qcom,rpm-pm8921-regulators";
870 pm8921_lvs1: lvs1 {};
871 pm8921_lvs2: lvs2 {};
872 pm8921_lvs3: lvs3 {};
873 pm8921_lvs4: lvs4 {};
874 pm8921_lvs5: lvs5 {};
875 pm8921_lvs6: lvs6 {};
876 pm8921_lvs7: lvs7 {};
878 pm8921_usb_switch: usb-switch {};
880 pm8921_hdmi_switch: hdmi-switch {
889 compatible = "qcom,ci-hdrc";
890 reg = <0x12500000 0x200>,
892 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
894 clock-names = "core", "iface";
895 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
896 assigned-clock-rates = <60000000>;
897 resets = <&gcc USB_HS1_RESET>;
898 reset-names = "core";
900 ahb-burst-config = <0>;
901 phys = <&usb_hs1_phy>;
902 phy-names = "usb-phy";
908 compatible = "qcom,usb-hs-phy-apq8064",
910 clocks = <&sleep_clk>, <&cxo_board>;
911 clock-names = "sleep", "ref";
920 compatible = "qcom,ci-hdrc";
921 reg = <0x12520000 0x200>,
923 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
924 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
925 clock-names = "core", "iface";
926 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
927 assigned-clock-rates = <60000000>;
928 resets = <&gcc USB_HS3_RESET>;
929 reset-names = "core";
931 ahb-burst-config = <0>;
932 phys = <&usb_hs3_phy>;
933 phy-names = "usb-phy";
939 compatible = "qcom,usb-hs-phy-apq8064",
942 clocks = <&sleep_clk>, <&cxo_board>;
943 clock-names = "sleep", "ref";
951 compatible = "qcom,ci-hdrc";
952 reg = <0x12530000 0x200>,
954 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
956 clock-names = "core", "iface";
957 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
958 assigned-clock-rates = <60000000>;
959 resets = <&gcc USB_HS4_RESET>;
960 reset-names = "core";
962 ahb-burst-config = <0>;
963 phys = <&usb_hs4_phy>;
964 phy-names = "usb-phy";
970 compatible = "qcom,usb-hs-phy-apq8064",
973 clocks = <&sleep_clk>, <&cxo_board>;
974 clock-names = "sleep", "ref";
981 sata_phy0: phy@1b400000 {
982 compatible = "qcom,apq8064-sata-phy";
984 reg = <0x1b400000 0x200>;
985 reg-names = "phy_mem";
986 clocks = <&gcc SATA_PHY_CFG_CLK>;
991 sata0: sata@29000000 {
992 compatible = "qcom,apq8064-ahci", "generic-ahci";
994 reg = <0x29000000 0x180>;
995 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
997 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1000 <&gcc SATA_RXOOB_CLK>,
1001 <&gcc SATA_PMALIVE_CLK>;
1002 clock-names = "slave_iface",
1008 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1009 <&gcc SATA_PMALIVE_CLK>;
1010 assigned-clock-rates = <100000000>, <100000000>;
1012 phys = <&sata_phy0>;
1013 phy-names = "sata-phy";
1014 ports-implemented = <0x1>;
1017 /* Temporary fixed regulator */
1018 sdcc1bam:dma@12402000{
1019 compatible = "qcom,bam-v1.3.0";
1020 reg = <0x12402000 0x8000>;
1021 interrupts = <0 98 0>;
1022 clocks = <&gcc SDC1_H_CLK>;
1023 clock-names = "bam_clk";
1028 sdcc3bam:dma@12182000{
1029 compatible = "qcom,bam-v1.3.0";
1030 reg = <0x12182000 0x8000>;
1031 interrupts = <0 96 0>;
1032 clocks = <&gcc SDC3_H_CLK>;
1033 clock-names = "bam_clk";
1038 sdcc4bam:dma@121c2000{
1039 compatible = "qcom,bam-v1.3.0";
1040 reg = <0x121c2000 0x8000>;
1041 interrupts = <0 95 0>;
1042 clocks = <&gcc SDC4_H_CLK>;
1043 clock-names = "bam_clk";
1049 compatible = "simple-bus";
1050 #address-cells = <1>;
1053 sdcc1: sdcc@12400000 {
1054 status = "disabled";
1055 compatible = "arm,pl18x", "arm,primecell";
1056 pinctrl-names = "default";
1057 pinctrl-0 = <&sdcc1_pins>;
1058 arm,primecell-periphid = <0x00051180>;
1059 reg = <0x12400000 0x2000>;
1060 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1061 interrupt-names = "cmd_irq";
1062 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1063 clock-names = "mclk", "apb_pclk";
1065 max-frequency = <96000000>;
1069 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1070 dma-names = "tx", "rx";
1073 sdcc3: sdcc@12180000 {
1074 compatible = "arm,pl18x", "arm,primecell";
1075 arm,primecell-periphid = <0x00051180>;
1076 status = "disabled";
1077 reg = <0x12180000 0x2000>;
1078 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1079 interrupt-names = "cmd_irq";
1080 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1081 clock-names = "mclk", "apb_pclk";
1085 max-frequency = <192000000>;
1087 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1088 dma-names = "tx", "rx";
1091 sdcc4: sdcc@121c0000 {
1092 compatible = "arm,pl18x", "arm,primecell";
1093 arm,primecell-periphid = <0x00051180>;
1094 status = "disabled";
1095 reg = <0x121c0000 0x2000>;
1096 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1097 interrupt-names = "cmd_irq";
1098 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1099 clock-names = "mclk", "apb_pclk";
1103 max-frequency = <48000000>;
1104 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1105 dma-names = "tx", "rx";
1106 pinctrl-names = "default";
1107 pinctrl-0 = <&sdc4_gpios>;
1111 tcsr: syscon@1a400000 {
1112 compatible = "qcom,tcsr-apq8064", "syscon";
1113 reg = <0x1a400000 0x100>;
1116 gpu: adreno-3xx@4300000 {
1117 compatible = "qcom,adreno-3xx";
1118 reg = <0x04300000 0x20000>;
1119 reg-names = "kgsl_3d0_reg_memory";
1120 interrupts = <GIC_SPI 80 0>;
1121 interrupt-names = "kgsl_3d0_irq";
1129 <&mmcc GFX3D_AHB_CLK>,
1130 <&mmcc GFX3D_AXI_CLK>,
1131 <&mmcc MMSS_IMEM_AHB_CLK>;
1132 qcom,chipid = <0x03020002>;
1199 qcom,gpu-pwrlevels {
1200 compatible = "qcom,gpu-pwrlevels";
1201 qcom,gpu-pwrlevel@0 {
1202 qcom,gpu-freq = <450000000>;
1204 qcom,gpu-pwrlevel@1 {
1205 qcom,gpu-freq = <27000000>;
1210 mmss_sfpb: syscon@5700000 {
1211 compatible = "syscon";
1212 reg = <0x5700000 0x70>;
1215 dsi0: mdss_dsi@4700000 {
1216 compatible = "qcom,mdss-dsi-ctrl";
1217 label = "MDSS DSI CTRL->0";
1218 #address-cells = <1>;
1220 interrupts = <GIC_SPI 82 0>;
1221 reg = <0x04700000 0x200>;
1222 reg-names = "dsi_ctrl";
1224 clocks = <&mmcc DSI_M_AHB_CLK>,
1225 <&mmcc DSI_S_AHB_CLK>,
1226 <&mmcc AMP_AHB_CLK>,
1228 <&mmcc DSI1_BYTE_CLK>,
1229 <&mmcc DSI_PIXEL_CLK>,
1230 <&mmcc DSI1_ESC_CLK>;
1231 clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
1232 "src_clk", "byte_clk", "pixel_clk",
1235 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1236 <&mmcc DSI1_ESC_SRC>,
1238 <&mmcc DSI_PIXEL_SRC>;
1239 assigned-clock-parents = <&dsi0_phy 0>,
1243 syscon-sfpb = <&mmss_sfpb>;
1246 #address-cells = <1>;
1257 dsi0_out: endpoint {
1264 dsi0_phy: dsi-phy@4700200 {
1265 compatible = "qcom,dsi-phy-28nm-8960";
1269 reg = <0x04700200 0x100>,
1272 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1273 clock-names = "iface_clk";
1274 clocks = <&mmcc DSI_M_AHB_CLK>;
1278 mdp_port0: iommu@7500000 {
1279 compatible = "qcom,apq8064-iommu";
1285 <&mmcc SMMU_AHB_CLK>,
1286 <&mmcc MDP_AXI_CLK>;
1287 reg = <0x07500000 0x100000>;
1294 mdp_port1: iommu@7600000 {
1295 compatible = "qcom,apq8064-iommu";
1301 <&mmcc SMMU_AHB_CLK>,
1302 <&mmcc MDP_AXI_CLK>;
1303 reg = <0x07600000 0x100000>;
1310 gfx3d: iommu@7c00000 {
1311 compatible = "qcom,apq8064-iommu";
1317 <&mmcc SMMU_AHB_CLK>,
1318 <&mmcc GFX3D_AXI_CLK>;
1319 reg = <0x07c00000 0x100000>;
1326 gfx3d1: iommu@7d00000 {
1327 compatible = "qcom,apq8064-iommu";
1333 <&mmcc SMMU_AHB_CLK>,
1334 <&mmcc GFX3D_AXI_CLK>;
1335 reg = <0x07d00000 0x100000>;
1342 pcie: pci@1b500000 {
1343 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1344 reg = <0x1b500000 0x1000
1347 0x0ff00000 0x100000>;
1348 reg-names = "dbi", "elbi", "parf", "config";
1349 device_type = "pci";
1350 linux,pci-domain = <0>;
1351 bus-range = <0x00 0xff>;
1353 #address-cells = <3>;
1355 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1356 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
1357 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
1358 interrupt-names = "msi";
1359 #interrupt-cells = <1>;
1360 interrupt-map-mask = <0 0 0 0x7>;
1361 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1362 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1363 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1364 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1365 clocks = <&gcc PCIE_A_CLK>,
1367 <&gcc PCIE_PHY_REF_CLK>;
1368 clock-names = "core", "iface", "phy";
1369 resets = <&gcc PCIE_ACLK_RESET>,
1370 <&gcc PCIE_HCLK_RESET>,
1371 <&gcc PCIE_POR_RESET>,
1372 <&gcc PCIE_PCI_RESET>,
1373 <&gcc PCIE_PHY_RESET>;
1374 reset-names = "axi", "ahb", "por", "pci", "phy";
1375 status = "disabled";
1378 hdmi: hdmi-tx@4a00000 {
1379 compatible = "qcom,hdmi-tx-8960";
1380 pinctrl-names = "default";
1381 pinctrl-0 = <&hdmi_pinctrl>;
1382 reg = <0x04a00000 0x2f0>;
1383 reg-names = "core_physical";
1384 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1385 clocks = <&mmcc HDMI_APP_CLK>,
1386 <&mmcc HDMI_M_AHB_CLK>,
1387 <&mmcc HDMI_S_AHB_CLK>;
1388 clock-names = "core_clk",
1393 phy-names = "hdmi-phy";
1396 #address-cells = <1>;
1407 hdmi_out: endpoint {
1413 hdmi_phy: hdmi-phy@4a00400 {
1414 compatible = "qcom,hdmi-phy-8960";
1415 reg = <0x4a00400 0x60>,
1417 reg-names = "hdmi_phy",
1420 clocks = <&mmcc HDMI_S_AHB_CLK>;
1421 clock-names = "slave_iface_clk";
1426 compatible = "qcom,mdp4";
1427 reg = <0x05100000 0xf0000>;
1428 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&mmcc MDP_CLK>,
1430 <&mmcc MDP_AHB_CLK>,
1431 <&mmcc MDP_AXI_CLK>,
1432 <&mmcc MDP_LUT_CLK>,
1433 <&mmcc HDMI_TV_CLK>,
1435 clock-names = "core_clk",
1442 iommus = <&mdp_port0 0
1448 #address-cells = <1>;
1453 mdp_lvds_out: endpoint {
1459 mdp_dsi1_out: endpoint {
1465 mdp_dsi2_out: endpoint {
1471 mdp_dtv_out: endpoint {
1477 riva: riva-pil@3204000 {
1478 compatible = "qcom,riva-pil";
1480 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1481 reg-names = "ccu", "dxe", "pmu";
1483 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1484 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1485 interrupt-names = "wdog", "fatal";
1487 memory-region = <&wcnss_mem>;
1489 vddcx-supply = <&pm8921_s3>;
1490 vddmx-supply = <&pm8921_l24>;
1491 vddpx-supply = <&pm8921_s4>;
1493 status = "disabled";
1496 compatible = "qcom,wcn3660";
1498 clocks = <&cxo_board>;
1501 vddxo-supply = <&pm8921_l4>;
1502 vddrfa-supply = <&pm8921_s2>;
1503 vddpa-supply = <&pm8921_l10>;
1504 vdddig-supply = <&pm8921_lvs2>;
1508 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1510 qcom,ipc = <&l2cc 8 25>;
1511 qcom,smd-edge = <6>;
1516 compatible = "qcom,wcnss";
1517 qcom,smd-channels = "WCNSS_CTRL";
1519 qcom,mmio = <&riva>;
1522 compatible = "qcom,wcnss-bt";
1526 compatible = "qcom,wcnss-wlan";
1528 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1530 interrupt-names = "tx", "rx";
1532 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1533 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1540 compatible = "coresight-etb10", "arm,primecell";
1541 reg = <0x1a01000 0x1000>;
1543 clocks = <&rpmcc RPM_QDSS_CLK>;
1544 clock-names = "apb_pclk";
1549 remote-endpoint = <&replicator_out0>;
1555 compatible = "arm,coresight-tpiu", "arm,primecell";
1556 reg = <0x1a03000 0x1000>;
1558 clocks = <&rpmcc RPM_QDSS_CLK>;
1559 clock-names = "apb_pclk";
1564 remote-endpoint = <&replicator_out1>;
1570 compatible = "arm,coresight-replicator";
1572 clocks = <&rpmcc RPM_QDSS_CLK>;
1573 clock-names = "apb_pclk";
1576 #address-cells = <1>;
1581 replicator_out0: endpoint {
1582 remote-endpoint = <&etb_in>;
1587 replicator_out1: endpoint {
1588 remote-endpoint = <&tpiu_in>;
1593 replicator_in: endpoint {
1595 remote-endpoint = <&funnel_out>;
1602 compatible = "arm,coresight-funnel", "arm,primecell";
1603 reg = <0x1a04000 0x1000>;
1605 clocks = <&rpmcc RPM_QDSS_CLK>;
1606 clock-names = "apb_pclk";
1609 #address-cells = <1>;
1613 * Not described input ports:
1614 * 2 - connected to STM component
1621 funnel_in0: endpoint {
1623 remote-endpoint = <&etm0_out>;
1628 funnel_in1: endpoint {
1630 remote-endpoint = <&etm1_out>;
1635 funnel_in4: endpoint {
1637 remote-endpoint = <&etm2_out>;
1642 funnel_in5: endpoint {
1644 remote-endpoint = <&etm3_out>;
1649 funnel_out: endpoint {
1650 remote-endpoint = <&replicator_in>;
1657 compatible = "arm,coresight-etm3x", "arm,primecell";
1658 reg = <0x1a1c000 0x1000>;
1660 clocks = <&rpmcc RPM_QDSS_CLK>;
1661 clock-names = "apb_pclk";
1666 etm0_out: endpoint {
1667 remote-endpoint = <&funnel_in0>;
1673 compatible = "arm,coresight-etm3x", "arm,primecell";
1674 reg = <0x1a1d000 0x1000>;
1676 clocks = <&rpmcc RPM_QDSS_CLK>;
1677 clock-names = "apb_pclk";
1682 etm1_out: endpoint {
1683 remote-endpoint = <&funnel_in1>;
1689 compatible = "arm,coresight-etm3x", "arm,primecell";
1690 reg = <0x1a1e000 0x1000>;
1692 clocks = <&rpmcc RPM_QDSS_CLK>;
1693 clock-names = "apb_pclk";
1698 etm2_out: endpoint {
1699 remote-endpoint = <&funnel_in4>;
1705 compatible = "arm,coresight-etm3x", "arm,primecell";
1706 reg = <0x1a1f000 0x1000>;
1708 clocks = <&rpmcc RPM_QDSS_CLK>;
1709 clock-names = "apb_pclk";
1714 etm3_out: endpoint {
1715 remote-endpoint = <&funnel_in5>;
1721 #include "qcom-apq8064-pins.dtsi"