1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Marvell Technology Group Ltd.
4 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
7 #include <dt-bindings/clock/marvell,pxa910.h>
24 compatible = "simple-bus";
25 interrupt-parent = <&intc>;
29 compatible = "marvell,tauros2-cache";
30 marvell,tauros2-cache-features = <0x3>;
33 axi@d4200000 { /* AXI */
34 compatible = "mrvl,axi-bus", "simple-bus";
37 reg = <0xd4200000 0x00200000>;
40 intc: interrupt-controller@d4282000 {
41 compatible = "mrvl,mmp-intc";
43 #interrupt-cells = <1>;
44 reg = <0xd4282000 0x1000>;
45 mrvl,intc-nr-irqs = <64>;
50 apb@d4000000 { /* APB */
51 compatible = "mrvl,apb-bus", "simple-bus";
54 reg = <0xd4000000 0x00200000>;
57 timer0: timer@d4014000 {
58 compatible = "mrvl,mmp-timer";
59 reg = <0xd4014000 0x100>;
63 timer1: timer@d4016000 {
64 compatible = "mrvl,mmp-timer";
65 reg = <0xd4016000 0x100>;
70 uart1: uart@d4017000 {
71 compatible = "mrvl,mmp-uart";
72 reg = <0xd4017000 0x1000>;
74 clocks = <&soc_clocks PXA910_CLK_UART0>;
75 resets = <&soc_clocks PXA910_CLK_UART0>;
79 uart2: uart@d4018000 {
80 compatible = "mrvl,mmp-uart";
81 reg = <0xd4018000 0x1000>;
83 clocks = <&soc_clocks PXA910_CLK_UART1>;
84 resets = <&soc_clocks PXA910_CLK_UART1>;
88 uart3: uart@d4036000 {
89 compatible = "mrvl,mmp-uart";
90 reg = <0xd4036000 0x1000>;
92 clocks = <&soc_clocks PXA910_CLK_UART2>;
93 resets = <&soc_clocks PXA910_CLK_UART2>;
98 compatible = "marvell,mmp-gpio";
101 reg = <0xd4019000 0x1000>;
105 interrupt-names = "gpio_mux";
106 clocks = <&soc_clocks PXA910_CLK_GPIO>;
107 resets = <&soc_clocks PXA910_CLK_GPIO>;
108 interrupt-controller;
109 #interrupt-cells = <1>;
112 gcb0: gpio@d4019000 {
113 reg = <0xd4019000 0x4>;
116 gcb1: gpio@d4019004 {
117 reg = <0xd4019004 0x4>;
120 gcb2: gpio@d4019008 {
121 reg = <0xd4019008 0x4>;
124 gcb3: gpio@d4019100 {
125 reg = <0xd4019100 0x4>;
129 twsi1: i2c@d4011000 {
130 compatible = "mrvl,mmp-twsi";
131 #address-cells = <1>;
133 reg = <0xd4011000 0x1000>;
135 clocks = <&soc_clocks PXA910_CLK_TWSI0>;
136 resets = <&soc_clocks PXA910_CLK_TWSI0>;
141 twsi2: i2c@d4037000 {
142 compatible = "mrvl,mmp-twsi";
143 #address-cells = <1>;
145 reg = <0xd4037000 0x1000>;
147 clocks = <&soc_clocks PXA910_CLK_TWSI1>;
148 resets = <&soc_clocks PXA910_CLK_TWSI1>;
153 compatible = "mrvl,mmp-rtc";
154 reg = <0xd4010000 0x1000>;
156 interrupt-names = "rtc 1Hz", "rtc alarm";
157 clocks = <&soc_clocks PXA910_CLK_RTC>;
158 resets = <&soc_clocks PXA910_CLK_RTC>;
164 compatible = "marvell,pxa910-clock";
165 reg = <0xd4050000 0x1000>,
169 reg-names = "mpmu", "apmu", "apbc", "apbcp";