1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Actions Semi S500 SoC
5 * Copyright (c) 2016-2017 Andreas Färber
8 #include <dt-bindings/clock/actions,s500-cmu.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/owl-s500-powergate.h>
12 #include <dt-bindings/reset/actions,s500-reset.h>
15 compatible = "actions,s500";
16 interrupt-parent = <&gic>;
32 compatible = "arm,cortex-a9";
34 enable-method = "actions,s500-smp";
39 compatible = "arm,cortex-a9";
41 enable-method = "actions,s500-smp";
46 compatible = "arm,cortex-a9";
48 enable-method = "actions,s500-smp";
49 power-domains = <&sps S500_PD_CPU2>;
54 compatible = "arm,cortex-a9";
56 enable-method = "actions,s500-smp";
57 power-domains = <&sps S500_PD_CPU3>;
62 compatible = "arm,cortex-a9-pmu";
63 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
67 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
71 compatible = "fixed-clock";
72 clock-frequency = <24000000>;
77 compatible = "fixed-clock";
78 clock-frequency = <32768>;
83 compatible = "simple-bus";
89 compatible = "arm,cortex-a9-scu";
90 reg = <0xb0020000 0x100>;
93 global_timer: timer@b0020200 {
94 compatible = "arm,cortex-a9-global-timer";
95 reg = <0xb0020200 0x100>;
96 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
100 twd_timer: timer@b0020600 {
101 compatible = "arm,cortex-a9-twd-timer";
102 reg = <0xb0020600 0x20>;
103 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
107 twd_wdt: wdt@b0020620 {
108 compatible = "arm,cortex-a9-twd-wdt";
109 reg = <0xb0020620 0xe0>;
110 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
114 gic: interrupt-controller@b0021000 {
115 compatible = "arm,cortex-a9-gic";
116 reg = <0xb0021000 0x1000>,
118 interrupt-controller;
119 #interrupt-cells = <3>;
122 l2: cache-controller@b0022000 {
123 compatible = "arm,pl310-cache";
124 reg = <0xb0022000 0x1000>;
127 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
128 arm,tag-latency = <3 3 2>;
129 arm,data-latency = <5 3 3>;
132 uart0: serial@b0120000 {
133 compatible = "actions,s500-uart", "actions,owl-uart";
134 reg = <0xb0120000 0x2000>;
135 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&cmu CLK_UART0>;
140 uart1: serial@b0122000 {
141 compatible = "actions,s500-uart", "actions,owl-uart";
142 reg = <0xb0122000 0x2000>;
143 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&cmu CLK_UART1>;
148 uart2: serial@b0124000 {
149 compatible = "actions,s500-uart", "actions,owl-uart";
150 reg = <0xb0124000 0x2000>;
151 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&cmu CLK_UART2>;
156 uart3: serial@b0126000 {
157 compatible = "actions,s500-uart", "actions,owl-uart";
158 reg = <0xb0126000 0x2000>;
159 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&cmu CLK_UART3>;
164 uart4: serial@b0128000 {
165 compatible = "actions,s500-uart", "actions,owl-uart";
166 reg = <0xb0128000 0x2000>;
167 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&cmu CLK_UART4>;
172 uart5: serial@b012a000 {
173 compatible = "actions,s500-uart", "actions,owl-uart";
174 reg = <0xb012a000 0x2000>;
175 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&cmu CLK_UART5>;
180 uart6: serial@b012c000 {
181 compatible = "actions,s500-uart", "actions,owl-uart";
182 reg = <0xb012c000 0x2000>;
183 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&cmu CLK_UART6>;
188 cmu: clock-controller@b0160000 {
189 compatible = "actions,s500-cmu";
190 reg = <0xb0160000 0x8000>;
191 clocks = <&hosc>, <&losc>;
197 compatible = "actions,s500-i2c";
198 reg = <0xb0170000 0x4000>;
199 clocks = <&cmu CLK_I2C0>;
200 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
201 #address-cells = <1>;
207 compatible = "actions,s500-i2c";
208 reg = <0xb0174000 0x4000>;
209 clocks = <&cmu CLK_I2C1>;
210 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
211 #address-cells = <1>;
217 compatible = "actions,s500-i2c";
218 reg = <0xb0178000 0x4000>;
219 clocks = <&cmu CLK_I2C2>;
220 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
221 #address-cells = <1>;
227 compatible = "actions,s500-i2c";
228 reg = <0xb017c000 0x4000>;
229 clocks = <&cmu CLK_I2C3>;
230 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
231 #address-cells = <1>;
236 sirq: interrupt-controller@b01b0200 {
237 compatible = "actions,s500-sirq";
238 reg = <0xb01b0200 0x4>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
241 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
242 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
243 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
246 timer: timer@b0168000 {
247 compatible = "actions,s500-timer";
248 reg = <0xb0168000 0x8000>;
249 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
253 interrupt-names = "2hz0", "2hz1", "timer0", "timer1";
256 sps: power-controller@b01b0100 {
257 compatible = "actions,s500-sps";
258 reg = <0xb01b0100 0x100>;
259 #power-domain-cells = <1>;
262 pinctrl: pinctrl@b01b0000 {
263 compatible = "actions,s500-pinctrl";
264 reg = <0xb01b0000 0x40>, /* GPIO */
265 <0xb01b0040 0x10>, /* Multiplexing Control */
266 <0xb01b0060 0x18>, /* PAD Control */
267 <0xb01b0080 0xc>; /* PAD Drive Capacity */
268 clocks = <&cmu CLK_GPIO>;
270 gpio-ranges = <&pinctrl 0 0 132>;
272 interrupt-controller;
273 #interrupt-cells = <2>;
274 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* GPIOA */
275 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* GPIOB */
276 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* GPIOC */
277 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, /* GPIOD */
278 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; /* GPIOE */
281 dma: dma-controller@b0260000 {
282 compatible = "actions,s500-dma";
283 reg = <0xb0260000 0xd00>;
284 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&cmu CLK_DMAC>;
292 power-domains = <&sps S500_PD_DMA>;
296 compatible = "actions,s500-mmc", "actions,owl-mmc";
297 reg = <0xb0230000 0x38>;
298 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&cmu CLK_SD0>;
300 resets = <&cmu RESET_SD0>;
307 compatible = "actions,s500-mmc", "actions,owl-mmc";
308 reg = <0xb0234000 0x38>;
309 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&cmu CLK_SD1>;
311 resets = <&cmu RESET_SD1>;
318 compatible = "actions,s500-mmc", "actions,owl-mmc";
319 reg = <0xb0238000 0x38>;
320 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&cmu CLK_SD2>;
322 resets = <&cmu RESET_SD2>;