arch/arm/boot/dts/omap5.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   4  *
   5  * Based on "omap4.dtsi"
   6  */
   7
   8 #include <dt-bindings/bus/ti-sysc.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/omap.h>
  12 #include <dt-bindings/clock/omap5.h>
  13
  14 / {
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         compatible = "ti,omap5";
  19         interrupt-parent = <&wakeupgen>;
  20         chosen { };
  21
  22         aliases {
  23                 i2c0 = &i2c1;
  24                 i2c1 = &i2c2;
  25                 i2c2 = &i2c3;
  26                 i2c3 = &i2c4;
  27                 i2c4 = &i2c5;
  28                 serial0 = &uart1;
  29                 serial1 = &uart2;
  30                 serial2 = &uart3;
  31                 serial3 = &uart4;
  32                 serial4 = &uart5;
  33                 serial5 = &uart6;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu0: cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0x0>;
  44
  45                         operating-points = <
  46                                 /* kHz    uV */
  47                                 1000000 1060000
  48                                 1500000 1250000
  49                         >;
  50
  51                         clocks = <&dpll_mpu_ck>;
  52                         clock-names = "cpu";
  53
  54                         clock-latency = <300000>; /* From omap-cpufreq driver */
  55
  56                         /* cooling options */
  57                         #cooling-cells = <2>; /* min followed by max */
  58                 };
  59                 cpu@1 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a15";
  62                         reg = <0x1>;
  63
  64                         operating-points = <
  65                                 /* kHz    uV */
  66                                 1000000 1060000
  67                                 1500000 1250000
  68                         >;
  69
  70                         clocks = <&dpll_mpu_ck>;
  71                         clock-names = "cpu";
  72
  73                         clock-latency = <300000>; /* From omap-cpufreq driver */
  74
  75                         /* cooling options */
  76                         #cooling-cells = <2>; /* min followed by max */
  77                 };
  78         };
  79
  80         thermal-zones {
  81                 #include "omap4-cpu-thermal.dtsi"
  82                 #include "omap5-gpu-thermal.dtsi"
  83                 #include "omap5-core-thermal.dtsi"
  84         };
  85
  86         timer {
  87                 compatible = "arm,armv7-timer";
  88                 /* PPI secure/nonsecure IRQ */
  89                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  90                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  91                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  92                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  93                 interrupt-parent = <&gic>;
  94         };
  95
  96         pmu {
  97                 compatible = "arm,cortex-a15-pmu";
  98                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  99                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 100         };
 101
 102         gic: interrupt-controller@48211000 {
 103                 compatible = "arm,cortex-a15-gic";
 104                 interrupt-controller;
 105                 #interrupt-cells = <3>;
 106                 reg = <0 0x48211000 0 0x1000>,
 107                       <0 0x48212000 0 0x2000>,
 108                       <0 0x48214000 0 0x2000>,
 109                       <0 0x48216000 0 0x2000>;
 110                 interrupt-parent = <&gic>;
 111         };
 112
 113         wakeupgen: interrupt-controller@48281000 {
 114                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
 115                 interrupt-controller;
 116                 #interrupt-cells = <3>;
 117                 reg = <0 0x48281000 0 0x1000>;
 118                 interrupt-parent = <&gic>;
 119         };
 120
 121         /*
 122          * The soc node represents the soc top level view. It is used for IPs
 123          * that are not memory mapped in the MPU view or for the MPU itself.
 124          */
 125         soc {
 126                 compatible = "ti,omap-infra";
 127                 mpu {
 128                         compatible = "ti,omap4-mpu";
 129                         ti,hwmods = "mpu";
 130                         sram = <&ocmcram>;
 131                 };
 132         };
 133
 134         /*
 135          * XXX: Use a flat representation of the OMAP3 interconnect.
 136          * The real OMAP interconnect network is quite complex.
 137          * Since it will not bring real advantage to represent that in DT for
 138          * the moment, just use a fake OCP bus entry to represent the whole bus
 139          * hierarchy.
 140          */
 141         ocp {
 142                 compatible = "ti,omap5-l3-noc", "simple-bus";
 143                 #address-cells = <1>;
 144                 #size-cells = <1>;
 145                 ranges = <0 0 0 0xc0000000>;
 146                 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
 147                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 148                 reg = <0 0x44000000 0 0x2000>,
 149                       <0 0x44800000 0 0x3000>,
 150                       <0 0x45000000 0 0x4000>;
 151                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 152                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 153
 154                 l4_wkup: interconnect@4ae00000 {
 155                 };
 156
 157                 l4_cfg: interconnect@4a000000 {
 158                 };
 159
 160                 l4_per: interconnect@48000000 {
 161                 };
 162
 163                 l4_abe: interconnect@40100000 {
 164                 };
 165
 166                 ocmcram: sram@40300000 {
 167                         compatible = "mmio-sram";
 168                         reg = <0x40300000 0x20000>; /* 128k */
 169                 };
 170
 171                 gpmc: gpmc@50000000 {
 172                         compatible = "ti,omap4430-gpmc";
 173                         reg = <0x50000000 0x1000>;
 174                         #address-cells = <2>;
 175                         #size-cells = <1>;
 176                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 177                         dmas = <&sdma 4>;
 178                         dma-names = "rxtx";
 179                         gpmc,num-cs = <8>;
 180                         gpmc,num-waitpins = <4>;
 181                         ti,hwmods = "gpmc";
 182                         clocks = <&l3_iclk_div>;
 183                         clock-names = "fck";
 184                         interrupt-controller;
 185                         #interrupt-cells = <2>;
 186                         gpio-controller;
 187                         #gpio-cells = <2>;
 188                 };
 189
 190                 target-module@55082000 {
 191                         compatible = "ti,sysc-omap2", "ti,sysc";
 192                         reg = <0x55082000 0x4>,
 193                               <0x55082010 0x4>,
 194                               <0x55082014 0x4>;
 195                         reg-names = "rev", "sysc", "syss";
 196                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 197                                         <SYSC_IDLE_NO>,
 198                                         <SYSC_IDLE_SMART>;
 199                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 200                                          SYSC_OMAP2_SOFTRESET |
 201                                          SYSC_OMAP2_AUTOIDLE)>;
 202                         clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
 203                         clock-names = "fck";
 204                         resets = <&prm_core 2>;
 205                         reset-names = "rstctrl";
 206                         ranges = <0x0 0x55082000 0x100>;
 207                         #size-cells = <1>;
 208                         #address-cells = <1>;
 209
 210                         mmu_ipu: mmu@0 {
 211                                 compatible = "ti,omap4-iommu";
 212                                 reg = <0x0 0x100>;
 213                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 214                                 #iommu-cells = <0>;
 215                                 ti,iommu-bus-err-back;
 216                         };
 217                 };
 218
 219                 dmm@4e000000 {
 220                         compatible = "ti,omap5-dmm";
 221                         reg = <0x4e000000 0x800>;
 222                         interrupts = <0 113 0x4>;
 223                         ti,hwmods = "dmm";
 224                 };
 225
 226                 emif1: emif@4c000000 {
 227                         compatible      = "ti,emif-4d5";
 228                         ti,hwmods       = "emif1";
 229                         ti,no-idle-on-init;
 230                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 231                         reg = <0x4c000000 0x400>;
 232                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 233                         hw-caps-read-idle-ctrl;
 234                         hw-caps-ll-interface;
 235                         hw-caps-temp-alert;
 236                 };
 237
 238                 emif2: emif@4d000000 {
 239                         compatible      = "ti,emif-4d5";
 240                         ti,hwmods       = "emif2";
 241                         ti,no-idle-on-init;
 242                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 243                         reg = <0x4d000000 0x400>;
 244                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 245                         hw-caps-read-idle-ctrl;
 246                         hw-caps-ll-interface;
 247                         hw-caps-temp-alert;
 248                 };
 249
 250                 aes1_target: target-module@4b501000 {
 251                         compatible = "ti,sysc-omap2", "ti,sysc";
 252                         reg = <0x4b501080 0x4>,
 253                               <0x4b501084 0x4>,
 254                               <0x4b501088 0x4>;
 255                         reg-names = "rev", "sysc", "syss";
 256                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 257                                          SYSC_OMAP2_AUTOIDLE)>;
 258                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 259                                         <SYSC_IDLE_NO>,
 260                                         <SYSC_IDLE_SMART>,
 261                                         <SYSC_IDLE_SMART_WKUP>;
 262                         ti,syss-mask = <1>;
 263                         /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
 264                         clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>;
 265                         clock-names = "fck";
 266                         #address-cells = <1>;
 267                         #size-cells = <1>;
 268                         ranges = <0x0 0x4b501000 0x1000>;
 269
 270                         aes1: aes@0 {
 271                                 compatible = "ti,omap4-aes";
 272                                 reg = <0 0xa0>;
 273                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 274                                 dmas = <&sdma 111>, <&sdma 110>;
 275                                 dma-names = "tx", "rx";
 276                         };
 277                 };
 278
 279                 aes2_target: target-module@4b701000 {
 280                         compatible = "ti,sysc-omap2", "ti,sysc";
 281                         reg = <0x4b701080 0x4>,
 282                               <0x4b701084 0x4>,
 283                               <0x4b701088 0x4>;
 284                         reg-names = "rev", "sysc", "syss";
 285                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 286                                          SYSC_OMAP2_AUTOIDLE)>;
 287                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 288                                         <SYSC_IDLE_NO>,
 289                                         <SYSC_IDLE_SMART>,
 290                                         <SYSC_IDLE_SMART_WKUP>;
 291                         ti,syss-mask = <1>;
 292                         /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
 293                         clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>;
 294                         clock-names = "fck";
 295                         #address-cells = <1>;
 296                         #size-cells = <1>;
 297                         ranges = <0x0 0x4b701000 0x1000>;
 298
 299                         aes2: aes@0 {
 300                                 compatible = "ti,omap4-aes";
 301                                 reg = <0 0xa0>;
 302                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 303                                 dmas = <&sdma 114>, <&sdma 113>;
 304                                 dma-names = "tx", "rx";
 305                         };
 306                 };
 307
 308                 sham_target: target-module@4b100000 {
 309                         compatible = "ti,sysc-omap3-sham", "ti,sysc";
 310                         reg = <0x4b100100 0x4>,
 311                               <0x4b100110 0x4>,
 312                               <0x4b100114 0x4>;
 313                         reg-names = "rev", "sysc", "syss";
 314                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 315                                          SYSC_OMAP2_AUTOIDLE)>;
 316                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 317                                         <SYSC_IDLE_NO>,
 318                                         <SYSC_IDLE_SMART>;
 319                         ti,syss-mask = <1>;
 320                         /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
 321                         clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>;
 322                         clock-names = "fck";
 323                         #address-cells = <1>;
 324                         #size-cells = <1>;
 325                         ranges = <0x0 0x4b100000 0x1000>;
 326
 327                         sham: sham@0 {
 328                                 compatible = "ti,omap4-sham";
 329                                 reg = <0 0x300>;
 330                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 331                                 dmas = <&sdma 119>;
 332                                 dma-names = "rx";
 333                         };
 334                 };
 335
 336                 bandgap: bandgap@4a0021e0 {
 337                         reg = <0x4a0021e0 0xc
 338                                0x4a00232c 0xc
 339                                0x4a002380 0x2c
 340                                0x4a0023C0 0x3c>;
 341                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 342                         compatible = "ti,omap5430-bandgap";
 343
 344                         #thermal-sensor-cells = <1>;
 345                 };
 346
 347                 /* OCP2SCP3 */
 348                 sata: sata@4a141100 {
 349                         compatible = "snps,dwc-ahci";
 350                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
 351                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 352                         phys = <&sata_phy>;
 353                         phy-names = "sata-phy";
 354                         clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
 355                         ti,hwmods = "sata";
 356                         ports-implemented = <0x1>;
 357                 };
 358
 359                 target-module@56000000 {
 360                         compatible = "ti,sysc-omap4", "ti,sysc";
 361                         reg = <0x5600fe00 0x4>,
 362                               <0x5600fe10 0x4>;
 363                         reg-names = "rev", "sysc";
 364                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 365                                         <SYSC_IDLE_NO>,
 366                                         <SYSC_IDLE_SMART>;
 367                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 368                                         <SYSC_IDLE_NO>,
 369                                         <SYSC_IDLE_SMART>;
 370                         clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
 371                         clock-names = "fck";
 372                         #address-cells = <1>;
 373                         #size-cells = <1>;
 374                         ranges = <0 0x56000000 0x2000000>;
 375
 376                         /*
 377                          * Closed source PowerVR driver, no child device
 378                          * binding or driver in mainline
 379                          */
 380                 };
 381
 382                 target-module@58000000 {
 383                         compatible = "ti,sysc-omap2", "ti,sysc";
 384                         reg = <0x58000000 4>,
 385                               <0x58000014 4>;
 386                         reg-names = "rev", "syss";
 387                         ti,syss-mask = <1>;
 388                         clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
 389                                  <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
 390                                  <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
 391                                  <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
 392                         clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
 393                         #address-cells = <1>;
 394                         #size-cells = <1>;
 395                         ranges = <0 0x58000000 0x1000000>;
 396
 397                         dss: dss@0 {
 398                                 compatible = "ti,omap5-dss";
 399                                 reg = <0 0x80>;
 400                                 status = "disabled";
 401                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
 402                                 clock-names = "fck";
 403                                 #address-cells = <1>;
 404                                 #size-cells = <1>;
 405                                 ranges = <0 0 0x1000000>;
 406
 407                                 target-module@1000 {
 408                                         compatible = "ti,sysc-omap2", "ti,sysc";
 409                                         reg = <0x1000 0x4>,
 410                                               <0x1010 0x4>,
 411                                               <0x1014 0x4>;
 412                                         reg-names = "rev", "sysc", "syss";
 413                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 414                                                         <SYSC_IDLE_NO>,
 415                                                         <SYSC_IDLE_SMART>;
 416                                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 417                                                         <SYSC_IDLE_NO>,
 418                                                         <SYSC_IDLE_SMART>;
 419                                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 420                                                          SYSC_OMAP2_ENAWAKEUP |
 421                                                          SYSC_OMAP2_SOFTRESET |
 422                                                          SYSC_OMAP2_AUTOIDLE)>;
 423                                         ti,syss-mask = <1>;
 424                                         clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
 425                                         clock-names = "fck";
 426                                         #address-cells = <1>;
 427                                         #size-cells = <1>;
 428                                         ranges = <0 0x1000 0x1000>;
 429
 430                                         dispc@0 {
 431                                                 compatible = "ti,omap5-dispc";
 432                                                 reg = <0 0x1000>;
 433                                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 434                                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
 435                                                 clock-names = "fck";
 436                                         };
 437                                 };
 438
 439                                 target-module@2000 {
 440                                         compatible = "ti,sysc-omap2", "ti,sysc";
 441                                         reg = <0x2000 0x4>,
 442                                               <0x2010 0x4>,
 443                                               <0x2014 0x4>;
 444                                         reg-names = "rev", "sysc", "syss";
 445                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 446                                                         <SYSC_IDLE_NO>,
 447                                                         <SYSC_IDLE_SMART>;
 448                                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 449                                                          SYSC_OMAP2_AUTOIDLE)>;
 450                                         ti,syss-mask = <1>;
 451                                         clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
 452                                         clock-names = "fck";
 453                                         #address-cells = <1>;
 454                                         #size-cells = <1>;
 455                                         ranges = <0 0x2000 0x1000>;
 456
 457                                         rfbi: encoder@0  {
 458                                                 compatible = "ti,omap5-rfbi";
 459                                                 reg = <0 0x100>;
 460                                                 status = "disabled";
 461                                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
 462                                                 clock-names = "fck", "ick";
 463                                         };
 464                                 };
 465
 466                                 target-module@5000 {
 467                                         compatible = "ti,sysc-omap2", "ti,sysc";
 468                                         reg = <0x5000 0x4>,
 469                                               <0x5010 0x4>,
 470                                               <0x5014 0x4>;
 471                                         reg-names = "rev", "sysc", "syss";
 472                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 473                                                         <SYSC_IDLE_NO>,
 474                                                         <SYSC_IDLE_SMART>;
 475                                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 476                                                          SYSC_OMAP2_ENAWAKEUP |
 477                                                          SYSC_OMAP2_SOFTRESET |
 478                                                          SYSC_OMAP2_AUTOIDLE)>;
 479                                         ti,syss-mask = <1>;
 480                                         #address-cells = <1>;
 481                                         #size-cells = <1>;
 482                                         ranges = <0 0x5000 0x1000>;
 483
 484                                         dsi1: encoder@0 {
 485                                                 compatible = "ti,omap5-dsi";
 486                                                 reg = <0 0x200>,
 487                                                       <0x200 0x40>,
 488                                                       <0x300 0x40>;
 489                                                 reg-names = "proto", "phy", "pll";
 490                                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 491                                                 status = "disabled";
 492                                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
 493                                                 clock-names = "fck";
 494                                         };
 495                                 };
 496
 497                                 target-module@9000 {
 498                                         compatible = "ti,sysc-omap2", "ti,sysc";
 499                                         reg = <0x9000 0x4>,
 500                                               <0x9010 0x4>,
 501                                               <0x9014 0x4>;
 502                                         reg-names = "rev", "sysc", "syss";
 503                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 504                                                         <SYSC_IDLE_NO>,
 505                                                         <SYSC_IDLE_SMART>;
 506                                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 507                                                          SYSC_OMAP2_ENAWAKEUP |
 508                                                          SYSC_OMAP2_SOFTRESET |
 509                                                          SYSC_OMAP2_AUTOIDLE)>;
 510                                         ti,syss-mask = <1>;
 511                                         #address-cells = <1>;
 512                                         #size-cells = <1>;
 513                                         ranges = <0 0x9000 0x1000>;
 514
 515                                         dsi2: encoder@0 {
 516                                                 compatible = "ti,omap5-dsi";
 517                                                 reg = <0 0x200>,
 518                                                       <0x200 0x40>,
 519                                                       <0x300 0x40>;
 520                                                 reg-names = "proto", "phy", "pll";
 521                                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 522                                                 status = "disabled";
 523                                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
 524                                                 clock-names = "fck";
 525                                         };
 526                                 };
 527
 528                                 target-module@40000 {
 529                                         compatible = "ti,sysc-omap4", "ti,sysc";
 530                                         reg = <0x40000 0x4>,
 531                                               <0x40010 0x4>;
 532                                         reg-names = "rev", "sysc";
 533                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 534                                                         <SYSC_IDLE_NO>,
 535                                                         <SYSC_IDLE_SMART>,
 536                                                         <SYSC_IDLE_SMART_WKUP>;
 537                                         ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
 538                                         clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
 539                                                  <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
 540                                         clock-names = "fck", "dss_clk";
 541                                         #address-cells = <1>;
 542                                         #size-cells = <1>;
 543                                         ranges = <0 0x40000 0x40000>;
 544
 545                                         hdmi: encoder@0 {
 546                                                 compatible = "ti,omap5-hdmi";
 547                                                 reg = <0 0x200>,
 548                                                       <0x200 0x80>,
 549                                                       <0x300 0x80>,
 550                                                       <0x20000 0x19000>;
 551                                                 reg-names = "wp", "pll", "phy", "core";
 552                                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 553                                                 status = "disabled";
 554                                                 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
 555                                                          <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
 556                                                 clock-names = "fck", "sys_clk";
 557                                                 dmas = <&sdma 76>;
 558                                                 dma-names = "audio_tx";
 559                                         };
 560                                 };
 561                         };
 562                 };
 563
 564                 abb_mpu: regulator-abb-mpu {
 565                         compatible = "ti,abb-v2";
 566                         regulator-name = "abb_mpu";
 567                         #address-cells = <0>;
 568                         #size-cells = <0>;
 569                         clocks = <&sys_clkin>;
 570                         ti,settling-time = <50>;
 571                         ti,clock-cycles = <16>;
 572
 573                         reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
 574                               <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
 575                         reg-names = "base-address", "int-address",
 576                                     "efuse-address", "ldo-address";
 577                         ti,tranxdone-status-mask = <0x80>;
 578                         /* LDOVBBMPU_MUX_CTRL */
 579                         ti,ldovbb-override-mask = <0x400>;
 580                         /* LDOVBBMPU_VSET_OUT */
 581                         ti,ldovbb-vset-mask = <0x1F>;
 582
 583                         /*
 584                          * NOTE: only FBB mode used but actual vset will
 585                          * determine final biasing
 586                          */
 587                         ti,abb_info = <
 588                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 589                         1060000         0       0x0     0 0x02000000 0x01F00000
 590                         1250000         0       0x4     0 0x02000000 0x01F00000
 591                         >;
 592                 };
 593
 594                 abb_mm: regulator-abb-mm {
 595                         compatible = "ti,abb-v2";
 596                         regulator-name = "abb_mm";
 597                         #address-cells = <0>;
 598                         #size-cells = <0>;
 599                         clocks = <&sys_clkin>;
 600                         ti,settling-time = <50>;
 601                         ti,clock-cycles = <16>;
 602
 603                         reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
 604                               <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
 605                         reg-names = "base-address", "int-address",
 606                                     "efuse-address", "ldo-address";
 607                         ti,tranxdone-status-mask = <0x80000000>;
 608                         /* LDOVBBMM_MUX_CTRL */
 609                         ti,ldovbb-override-mask = <0x400>;
 610                         /* LDOVBBMM_VSET_OUT */
 611                         ti,ldovbb-vset-mask = <0x1F>;
 612
 613                         /*
 614                          * NOTE: only FBB mode used but actual vset will
 615                          * determine final biasing
 616                          */
 617                         ti,abb_info = <
 618                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 619                         1025000         0       0x0     0 0x02000000 0x01F00000
 620                         1120000         0       0x4     0 0x02000000 0x01F00000
 621                         >;
 622                 };
 623         };
 624 };
 625
 626 &cpu_thermal {
 627         polling-delay = <500>; /* milliseconds */
 628         coefficients = <65 (-1791)>;
 629 };
 630
 631 #include "omap5-l4.dtsi"
 632 #include "omap54xx-clocks.dtsi"
 633
 634 &gpu_thermal {
 635         coefficients = <117 (-2992)>;
 636 };
 637
 638 &core_thermal {
 639         coefficients = <0 2000>;
 640 };
 641
 642 #include "omap5-l4-abe.dtsi"
 643 #include "omap54xx-clocks.dtsi"
 644
 645 &prm {
 646         prm_dsp: prm@400 {
 647                 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
 648                 reg = <0x400 0x100>;
 649                 #reset-cells = <1>;
 650         };
 651
 652         prm_core: prm@700 {
 653                 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
 654                 reg = <0x700 0x100>;
 655                 #reset-cells = <1>;
 656         };
 657
 658         prm_iva: prm@1200 {
 659                 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
 660                 reg = <0x1200 0x100>;
 661                 #reset-cells = <1>;
 662         };
 663
 664         prm_device: prm@1c00 {
 665                 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
 666                 reg = <0x1c00 0x100>;
 667                 #reset-cells = <1>;
 668         };
 669 };
 670
 671 /* Preferred always-on timer for clockevent */
 672 &timer1_target {
 673         ti,no-reset-on-init;
 674         ti,no-idle;
 675         timer@0 {
 676                 assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
 677                 assigned-clock-parents = <&sys_32k_ck>;
 678         };
 679 };