1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 * Based on "omap4.dtsi"
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
12 #include <dt-bindings/clock/omap5.h>
18 compatible = "ti,omap5";
19 interrupt-parent = <&wakeupgen>;
49 compatible = "arm,cortex-a15";
58 clocks = <&dpll_mpu_ck>;
61 clock-latency = <300000>; /* From omap-cpufreq driver */
64 #cooling-cells = <2>; /* min followed by max */
68 compatible = "arm,cortex-a15";
77 clocks = <&dpll_mpu_ck>;
80 clock-latency = <300000>; /* From omap-cpufreq driver */
83 #cooling-cells = <2>; /* min followed by max */
88 #include "omap4-cpu-thermal.dtsi"
89 #include "omap5-gpu-thermal.dtsi"
90 #include "omap5-core-thermal.dtsi"
94 compatible = "arm,armv7-timer";
95 /* PPI secure/nonsecure IRQ */
96 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
97 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
98 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
99 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
100 interrupt-parent = <&gic>;
104 compatible = "arm,cortex-a15-pmu";
105 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
110 * Needed early by omap4_sram_init() for barrier, do not move to l3
111 * interconnect as simple-pm-bus probes at module_init() time.
113 ocmcram: sram@40300000 {
114 compatible = "mmio-sram";
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
118 gic: interrupt-controller@48211000 {
119 compatible = "arm,cortex-a15-gic";
120 interrupt-controller;
121 #interrupt-cells = <3>;
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
126 interrupt-parent = <&gic>;
129 wakeupgen: interrupt-controller@48281000 {
130 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
131 interrupt-controller;
132 #interrupt-cells = <3>;
133 reg = <0 0x48281000 0 0x1000>;
134 interrupt-parent = <&gic>;
138 * XXX: Use a flat representation of the OMAP3 interconnect.
139 * The real OMAP interconnect network is quite complex.
140 * Since it will not bring real advantage to represent that in DT for
141 * the moment, just use a fake OCP bus entry to represent the whole bus
145 compatible = "simple-pm-bus";
146 power-domains = <&prm_core>;
147 clocks = <&l3main1_clkctrl OMAP5_L3_MAIN_1_CLKCTRL 0>,
148 <&l3main2_clkctrl OMAP5_L3_MAIN_2_CLKCTRL 0>,
149 <&l3instr_clkctrl OMAP5_L3_MAIN_3_CLKCTRL 0>;
150 #address-cells = <1>;
152 ranges = <0 0 0 0xc0000000>;
153 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
156 compatible = "ti,omap5-l3-noc";
157 reg = <0x44000000 0x2000>,
160 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
164 l4_wkup: interconnect@4ae00000 {
167 l4_cfg: interconnect@4a000000 {
170 l4_per: interconnect@48000000 {
173 target-module@48210000 {
174 compatible = "ti,sysc-omap4-simple", "ti,sysc";
175 power-domains = <&prm_mpu>;
176 clocks = <&mpu_clkctrl OMAP5_MPU_CLKCTRL 0>;
178 #address-cells = <1>;
180 ranges = <0 0x48210000 0x1f0000>;
183 compatible = "ti,omap4-mpu";
188 l4_abe: interconnect@40100000 {
191 target-module@50000000 {
192 compatible = "ti,sysc-omap2", "ti,sysc";
193 reg = <0x50000000 4>,
196 reg-names = "rev", "sysc", "syss";
197 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
202 clocks = <&l3main2_clkctrl OMAP5_L3_MAIN_2_GPMC_CLKCTRL 0>;
204 #address-cells = <1>;
206 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
207 <0x00000000 0x00000000 0x40000000>; /* data */
209 gpmc: gpmc@50000000 {
210 compatible = "ti,omap4430-gpmc";
211 reg = <0x50000000 0x1000>;
212 #address-cells = <2>;
214 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
218 gpmc,num-waitpins = <4>;
220 interrupt-controller;
221 #interrupt-cells = <2>;
227 target-module@55082000 {
228 compatible = "ti,sysc-omap2", "ti,sysc";
229 reg = <0x55082000 0x4>,
232 reg-names = "rev", "sysc", "syss";
233 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
236 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
237 SYSC_OMAP2_SOFTRESET |
238 SYSC_OMAP2_AUTOIDLE)>;
239 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
241 resets = <&prm_core 2>;
242 reset-names = "rstctrl";
243 ranges = <0x0 0x55082000 0x100>;
245 #address-cells = <1>;
248 compatible = "ti,omap4-iommu";
250 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
252 ti,iommu-bus-err-back;
257 compatible = "ti,omap5-dsp";
258 ti,bootreg = <&scm_conf 0x304 0>;
260 resets = <&prm_dsp 0>;
261 clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
262 firmware-name = "omap5-dsp-fw.xe64T";
263 mboxes = <&mailbox &mbox_dsp>;
268 compatible = "ti,omap5-ipu";
269 reg = <0x55020000 0x10000>;
272 resets = <&prm_core 0>, <&prm_core 1>;
273 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
274 firmware-name = "omap5-ipu-fw.xem4";
275 mboxes = <&mailbox &mbox_ipu>;
279 target-module@4e000000 {
280 compatible = "ti,sysc-omap2", "ti,sysc";
281 reg = <0x4e000000 0x4>,
283 reg-names = "rev", "sysc";
284 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
287 ranges = <0x0 0x4e000000 0x2000000>;
289 #address-cells = <1>;
292 compatible = "ti,omap5-dmm";
294 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
298 target-module@4c000000 {
299 compatible = "ti,sysc-omap4-simple", "ti,sysc";
300 reg = <0x4c000000 0x4>;
302 clocks = <&emif_clkctrl OMAP5_EMIF1_CLKCTRL 0>;
305 #address-cells = <1>;
307 ranges = <0x0 0x4c000000 0x1000000>;
310 compatible = "ti,emif-4d5";
312 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
313 phy-type = <2>; /* DDR PHY type: Intelli PHY */
314 hw-caps-read-idle-ctrl;
315 hw-caps-ll-interface;
320 target-module@4d000000 {
321 compatible = "ti,sysc-omap4-simple", "ti,sysc";
322 reg = <0x4d000000 0x4>;
324 clocks = <&emif_clkctrl OMAP5_EMIF2_CLKCTRL 0>;
327 #address-cells = <1>;
329 ranges = <0x0 0x4d000000 0x1000000>;
332 compatible = "ti,emif-4d5";
334 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
335 phy-type = <2>; /* DDR PHY type: Intelli PHY */
336 hw-caps-read-idle-ctrl;
337 hw-caps-ll-interface;
342 aes1_target: target-module@4b501000 {
343 compatible = "ti,sysc-omap2", "ti,sysc";
344 reg = <0x4b501080 0x4>,
347 reg-names = "rev", "sysc", "syss";
348 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
349 SYSC_OMAP2_AUTOIDLE)>;
350 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
353 <SYSC_IDLE_SMART_WKUP>;
355 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
356 clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>;
358 #address-cells = <1>;
360 ranges = <0x0 0x4b501000 0x1000>;
363 compatible = "ti,omap4-aes";
365 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
366 dmas = <&sdma 111>, <&sdma 110>;
367 dma-names = "tx", "rx";
371 aes2_target: target-module@4b701000 {
372 compatible = "ti,sysc-omap2", "ti,sysc";
373 reg = <0x4b701080 0x4>,
376 reg-names = "rev", "sysc", "syss";
377 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
378 SYSC_OMAP2_AUTOIDLE)>;
379 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
382 <SYSC_IDLE_SMART_WKUP>;
384 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
385 clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>;
387 #address-cells = <1>;
389 ranges = <0x0 0x4b701000 0x1000>;
392 compatible = "ti,omap4-aes";
394 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
395 dmas = <&sdma 114>, <&sdma 113>;
396 dma-names = "tx", "rx";
400 sham_target: target-module@4b100000 {
401 compatible = "ti,sysc-omap3-sham", "ti,sysc";
402 reg = <0x4b100100 0x4>,
405 reg-names = "rev", "sysc", "syss";
406 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
407 SYSC_OMAP2_AUTOIDLE)>;
408 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
412 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
413 clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>;
415 #address-cells = <1>;
417 ranges = <0x0 0x4b100000 0x1000>;
420 compatible = "ti,omap4-sham";
422 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
428 bandgap: bandgap@4a0021e0 {
429 reg = <0x4a0021e0 0xc
433 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
434 compatible = "ti,omap5430-bandgap";
436 #thermal-sensor-cells = <1>;
439 target-module@56000000 {
440 compatible = "ti,sysc-omap4", "ti,sysc";
441 reg = <0x5600fe00 0x4>,
443 reg-names = "rev", "sysc";
444 ti,sysc-midle = <SYSC_IDLE_FORCE>,
447 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
450 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
452 #address-cells = <1>;
454 ranges = <0 0x56000000 0x2000000>;
457 * Closed source PowerVR driver, no child device
458 * binding or driver in mainline
462 target-module@58000000 {
463 compatible = "ti,sysc-omap2", "ti,sysc";
464 reg = <0x58000000 4>,
466 reg-names = "rev", "syss";
468 power-domains = <&prm_dss>;
469 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
470 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
471 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
472 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
473 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
474 #address-cells = <1>;
476 ranges = <0 0x58000000 0x1000000>;
479 compatible = "ti,omap5-dss";
482 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
484 #address-cells = <1>;
486 ranges = <0 0 0x1000000>;
489 compatible = "ti,sysc-omap2", "ti,sysc";
493 reg-names = "rev", "sysc", "syss";
494 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
497 ti,sysc-midle = <SYSC_IDLE_FORCE>,
500 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
501 SYSC_OMAP2_ENAWAKEUP |
502 SYSC_OMAP2_SOFTRESET |
503 SYSC_OMAP2_AUTOIDLE)>;
505 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
507 #address-cells = <1>;
509 ranges = <0 0x1000 0x1000>;
512 compatible = "ti,omap5-dispc";
514 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
521 compatible = "ti,sysc-omap2", "ti,sysc";
525 reg-names = "rev", "sysc", "syss";
526 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
529 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
530 SYSC_OMAP2_AUTOIDLE)>;
532 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
534 #address-cells = <1>;
536 ranges = <0 0x2000 0x1000>;
539 compatible = "ti,omap5-rfbi";
542 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
543 clock-names = "fck", "ick";
548 compatible = "ti,sysc-omap2", "ti,sysc";
552 reg-names = "rev", "sysc", "syss";
553 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
556 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
557 SYSC_OMAP2_ENAWAKEUP |
558 SYSC_OMAP2_SOFTRESET |
559 SYSC_OMAP2_AUTOIDLE)>;
561 #address-cells = <1>;
563 ranges = <0 0x4000 0x1000>;
566 compatible = "ti,omap5-dsi";
570 reg-names = "proto", "phy", "pll";
571 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
574 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
575 clock-names = "fck", "sys_clk";
577 #address-cells = <1>;
583 compatible = "ti,sysc-omap2", "ti,sysc";
587 reg-names = "rev", "sysc", "syss";
588 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
591 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
592 SYSC_OMAP2_ENAWAKEUP |
593 SYSC_OMAP2_SOFTRESET |
594 SYSC_OMAP2_AUTOIDLE)>;
596 #address-cells = <1>;
598 ranges = <0 0x9000 0x1000>;
601 compatible = "ti,omap5-dsi";
605 reg-names = "proto", "phy", "pll";
606 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
609 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
610 clock-names = "fck", "sys_clk";
612 #address-cells = <1>;
617 target-module@40000 {
618 compatible = "ti,sysc-omap4", "ti,sysc";
621 reg-names = "rev", "sysc";
622 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
625 <SYSC_IDLE_SMART_WKUP>;
626 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
627 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
628 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
629 clock-names = "fck", "dss_clk";
630 #address-cells = <1>;
632 ranges = <0 0x40000 0x40000>;
635 compatible = "ti,omap5-hdmi";
640 reg-names = "wp", "pll", "phy", "core";
641 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
644 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
645 clock-names = "fck", "sys_clk";
647 dma-names = "audio_tx";
653 abb_mpu: regulator-abb-mpu {
654 compatible = "ti,abb-v2";
655 regulator-name = "abb_mpu";
656 #address-cells = <0>;
658 clocks = <&sys_clkin>;
659 ti,settling-time = <50>;
660 ti,clock-cycles = <16>;
662 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
663 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
664 reg-names = "base-address", "int-address",
665 "efuse-address", "ldo-address";
666 ti,tranxdone-status-mask = <0x80>;
667 /* LDOVBBMPU_MUX_CTRL */
668 ti,ldovbb-override-mask = <0x400>;
669 /* LDOVBBMPU_VSET_OUT */
670 ti,ldovbb-vset-mask = <0x1F>;
673 * NOTE: only FBB mode used but actual vset will
674 * determine final biasing
677 /*uV ABB efuse rbb_m fbb_m vset_m*/
678 1060000 0 0x0 0 0x02000000 0x01F00000
679 1250000 0 0x4 0 0x02000000 0x01F00000
683 abb_mm: regulator-abb-mm {
684 compatible = "ti,abb-v2";
685 regulator-name = "abb_mm";
686 #address-cells = <0>;
688 clocks = <&sys_clkin>;
689 ti,settling-time = <50>;
690 ti,clock-cycles = <16>;
692 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
693 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
694 reg-names = "base-address", "int-address",
695 "efuse-address", "ldo-address";
696 ti,tranxdone-status-mask = <0x80000000>;
697 /* LDOVBBMM_MUX_CTRL */
698 ti,ldovbb-override-mask = <0x400>;
699 /* LDOVBBMM_VSET_OUT */
700 ti,ldovbb-vset-mask = <0x1F>;
703 * NOTE: only FBB mode used but actual vset will
704 * determine final biasing
707 /*uV ABB efuse rbb_m fbb_m vset_m*/
708 1025000 0 0x0 0 0x02000000 0x01F00000
709 1120000 0 0x4 0 0x02000000 0x01F00000
716 polling-delay = <500>; /* milliseconds */
717 coefficients = <65 (-1791)>;
720 #include "omap5-l4.dtsi"
721 #include "omap54xx-clocks.dtsi"
724 coefficients = <117 (-2992)>;
728 coefficients = <0 2000>;
731 #include "omap5-l4-abe.dtsi"
732 #include "omap54xx-clocks.dtsi"
736 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
738 #power-domain-cells = <0>;
742 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
745 #power-domain-cells = <0>;
749 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
751 #power-domain-cells = <0>;
754 prm_coreaon: prm@600 {
755 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
757 #power-domain-cells = <0>;
761 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
764 #power-domain-cells = <0>;
768 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
769 reg = <0x1200 0x100>;
771 #power-domain-cells = <0>;
775 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
776 reg = <0x1300 0x100>;
777 #power-domain-cells = <0>;
781 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
782 reg = <0x1400 0x100>;
783 #power-domain-cells = <0>;
787 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
788 reg = <0x1500 0x100>;
789 #power-domain-cells = <0>;
792 prm_l3init: prm@1600 {
793 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
794 reg = <0x1600 0x100>;
795 #power-domain-cells = <0>;
798 prm_custefuse: prm@1700 {
799 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
800 reg = <0x1700 0x100>;
801 #power-domain-cells = <0>;
804 prm_wkupaon: prm@1800 {
805 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
806 reg = <0x1800 0x100>;
807 #power-domain-cells = <0>;
811 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
812 reg = <0x1a00 0x100>;
813 #power-domain-cells = <0>;
816 prm_device: prm@1c00 {
817 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
818 reg = <0x1c00 0x100>;
823 /* Preferred always-on timer for clockevent */
828 assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
829 assigned-clock-parents = <&sys_32k_ck>;