1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 #include <dt-bindings/bus/ti-sysc.h>
7 #include <dt-bindings/clock/omap4.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/omap.h>
11 #include <dt-bindings/clock/omap4.h>
14 compatible = "ti,omap4430", "ti,omap4";
15 interrupt-parent = <&wakeupgen>;
36 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
41 clocks = <&dpll_mpu_ck>;
44 clock-latency = <300000>; /* From omap-cpufreq driver */
47 compatible = "arm,cortex-a9";
49 next-level-cache = <&L2>;
55 * Note that 4430 needs cross trigger interface (CTI) supported
56 * before we can configure the interrupts. This means sampling
57 * events are not supported for pmu. Note that 4460 does not use
58 * CTI, see also 4460.dtsi.
61 compatible = "arm,cortex-a9-pmu";
62 ti,hwmods = "debugss";
65 gic: interrupt-controller@48241000 {
66 compatible = "arm,cortex-a9-gic";
68 #interrupt-cells = <3>;
69 reg = <0x48241000 0x1000>,
71 interrupt-parent = <&gic>;
74 L2: l2-cache-controller@48242000 {
75 compatible = "arm,pl310-cache";
76 reg = <0x48242000 0x1000>;
81 local-timer@48240600 {
82 compatible = "arm,cortex-a9-twd-timer";
83 clocks = <&mpu_periphclk>;
84 reg = <0x48240600 0x20>;
85 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
86 interrupt-parent = <&gic>;
89 wakeupgen: interrupt-controller@48281000 {
90 compatible = "ti,omap4-wugen-mpu";
92 #interrupt-cells = <3>;
93 reg = <0x48281000 0x1000>;
94 interrupt-parent = <&gic>;
98 * The soc node represents the soc top level view. It is used for IPs
99 * that are not memory mapped in the MPU view or for the MPU itself.
102 compatible = "ti,omap-infra";
104 compatible = "ti,omap4-mpu";
110 compatible = "ti,omap3-c64";
114 compatible = "ti,ivahd";
120 * XXX: Use a flat representation of the OMAP4 interconnect.
121 * The real OMAP interconnect network is quite complex.
122 * Since it will not bring real advantage to represent that in DT for
123 * the moment, just use a fake OCP bus entry to represent the whole bus
127 compatible = "ti,omap4-l3-noc", "simple-bus";
128 #address-cells = <1>;
131 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
132 reg = <0x44000000 0x1000>,
135 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
138 l4_wkup: interconnect@4a300000 {
141 l4_cfg: interconnect@4a000000 {
144 l4_per: interconnect@48000000 {
147 l4_abe: interconnect@40100000 {
150 ocmcram: sram@40304000 {
151 compatible = "mmio-sram";
152 reg = <0x40304000 0xa000>; /* 40k */
155 gpmc: gpmc@50000000 {
156 compatible = "ti,omap4430-gpmc";
157 reg = <0x50000000 0x1000>;
158 #address-cells = <2>;
160 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
164 gpmc,num-waitpins = <4>;
167 clocks = <&l3_div_ck>;
169 interrupt-controller;
170 #interrupt-cells = <2>;
175 target-module@52000000 {
176 compatible = "ti,sysc-omap4", "ti,sysc";
178 reg = <0x52000000 0x4>,
180 reg-names = "rev", "sysc";
181 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
182 ti,sysc-midle = <SYSC_IDLE_FORCE>,
185 <SYSC_IDLE_SMART_WKUP>;
186 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
189 <SYSC_IDLE_SMART_WKUP>;
190 ti,sysc-delay-us = <2>;
191 clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
193 #address-cells = <1>;
195 ranges = <0 0x52000000 0x1000000>;
197 /* No child device binding, driver in staging */
200 target-module@55082000 {
201 compatible = "ti,sysc-omap2", "ti,sysc";
202 reg = <0x55082000 0x4>,
205 reg-names = "rev", "sysc", "syss";
206 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
209 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
210 SYSC_OMAP2_SOFTRESET |
211 SYSC_OMAP2_AUTOIDLE)>;
212 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
214 resets = <&prm_core 2>;
215 reset-names = "rstctrl";
216 ranges = <0x0 0x55082000 0x100>;
218 #address-cells = <1>;
221 compatible = "ti,omap4-iommu";
223 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
225 ti,iommu-bus-err-back;
229 target-module@4012c000 {
230 compatible = "ti,sysc-omap4", "ti,sysc";
231 reg = <0x4012c000 0x4>,
233 reg-names = "rev", "sysc";
234 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
235 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
238 <SYSC_IDLE_SMART_WKUP>;
239 clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
241 #address-cells = <1>;
243 ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
244 <0x4902c000 0x4902c000 0x1000>; /* L3 */
246 /* No child device binding or driver in mainline */
250 compatible = "ti,omap4-dmm";
251 reg = <0x4e000000 0x800>;
252 interrupts = <0 113 0x4>;
256 emif1: emif@4c000000 {
257 compatible = "ti,emif-4d";
258 reg = <0x4c000000 0x100>;
259 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
263 hw-caps-read-idle-ctrl;
264 hw-caps-ll-interface;
268 emif2: emif@4d000000 {
269 compatible = "ti,emif-4d";
270 reg = <0x4d000000 0x100>;
271 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
275 hw-caps-read-idle-ctrl;
276 hw-caps-ll-interface;
280 aes1_target: target-module@4b501000 {
281 compatible = "ti,sysc-omap2", "ti,sysc";
282 reg = <0x4b501080 0x4>,
285 reg-names = "rev", "sysc", "syss";
286 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
287 SYSC_OMAP2_AUTOIDLE)>;
288 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
291 <SYSC_IDLE_SMART_WKUP>;
293 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
294 clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
296 #address-cells = <1>;
298 ranges = <0x0 0x4b501000 0x1000>;
301 compatible = "ti,omap4-aes";
303 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
304 dmas = <&sdma 111>, <&sdma 110>;
305 dma-names = "tx", "rx";
309 aes2_target: target-module@4b701000 {
310 compatible = "ti,sysc-omap2", "ti,sysc";
311 reg = <0x4b701080 0x4>,
314 reg-names = "rev", "sysc", "syss";
315 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
316 SYSC_OMAP2_AUTOIDLE)>;
317 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
320 <SYSC_IDLE_SMART_WKUP>;
322 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
323 clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
325 #address-cells = <1>;
327 ranges = <0x0 0x4b701000 0x1000>;
330 compatible = "ti,omap4-aes";
332 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
333 dmas = <&sdma 114>, <&sdma 113>;
334 dma-names = "tx", "rx";
338 sham_target: target-module@4b100000 {
339 compatible = "ti,sysc-omap3-sham", "ti,sysc";
340 reg = <0x4b100100 0x4>,
343 reg-names = "rev", "sysc", "syss";
344 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
345 SYSC_OMAP2_AUTOIDLE)>;
346 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
350 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
351 clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
353 #address-cells = <1>;
355 ranges = <0x0 0x4b100000 0x1000>;
358 compatible = "ti,omap4-sham";
360 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
366 abb_mpu: regulator-abb-mpu {
367 compatible = "ti,abb-v2";
368 regulator-name = "abb_mpu";
369 #address-cells = <0>;
371 ti,tranxdone-status-mask = <0x80>;
372 clocks = <&sys_clkin_ck>;
373 ti,settling-time = <50>;
374 ti,clock-cycles = <16>;
379 abb_iva: regulator-abb-iva {
380 compatible = "ti,abb-v2";
381 regulator-name = "abb_iva";
382 #address-cells = <0>;
384 ti,tranxdone-status-mask = <0x80000000>;
385 clocks = <&sys_clkin_ck>;
386 ti,settling-time = <50>;
387 ti,clock-cycles = <16>;
392 target-module@56000000 {
393 compatible = "ti,sysc-omap4", "ti,sysc";
394 reg = <0x5600fe00 0x4>,
396 reg-names = "rev", "sysc";
397 ti,sysc-midle = <SYSC_IDLE_FORCE>,
400 <SYSC_IDLE_SMART_WKUP>;
401 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
404 <SYSC_IDLE_SMART_WKUP>;
405 clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
407 #address-cells = <1>;
409 ranges = <0 0x56000000 0x2000000>;
412 * Closed source PowerVR driver, no child device
413 * binding or driver in mainline
418 * DSS is only using l3 mapping without l4 as noted in the TRM
419 * "10.1.3 DSS Register Manual" for omap4460.
421 target-module@58000000 {
422 compatible = "ti,sysc-omap2", "ti,sysc";
423 reg = <0x58000000 4>,
425 reg-names = "rev", "syss";
427 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
428 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
429 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
430 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
431 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
432 #address-cells = <1>;
434 ranges = <0 0x58000000 0x1000000>;
437 compatible = "ti,omap4-dss";
440 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
442 #address-cells = <1>;
444 ranges = <0 0 0x1000000>;
447 compatible = "ti,sysc-omap2", "ti,sysc";
451 reg-names = "rev", "sysc", "syss";
452 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
455 ti,sysc-midle = <SYSC_IDLE_FORCE>,
458 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
459 SYSC_OMAP2_ENAWAKEUP |
460 SYSC_OMAP2_SOFTRESET |
461 SYSC_OMAP2_AUTOIDLE)>;
463 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
464 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
465 clock-names = "fck", "sys_clk";
466 #address-cells = <1>;
468 ranges = <0 0x1000 0x1000>;
471 compatible = "ti,omap4-dispc";
473 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
474 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
480 compatible = "ti,sysc-omap2", "ti,sysc";
484 reg-names = "rev", "sysc", "syss";
485 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
488 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
489 SYSC_OMAP2_AUTOIDLE)>;
491 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
492 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
493 clock-names = "fck", "sys_clk";
494 #address-cells = <1>;
496 ranges = <0 0x2000 0x1000>;
501 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
502 clock-names = "fck", "ick";
507 compatible = "ti,sysc-omap2", "ti,sysc";
510 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
511 clock-names = "sys_clk";
512 #address-cells = <1>;
514 ranges = <0 0x3000 0x1000>;
517 compatible = "ti,omap4-venc";
520 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
526 compatible = "ti,sysc-omap2", "ti,sysc";
530 reg-names = "rev", "sysc", "syss";
531 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
534 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
535 SYSC_OMAP2_ENAWAKEUP |
536 SYSC_OMAP2_SOFTRESET |
537 SYSC_OMAP2_AUTOIDLE)>;
539 #address-cells = <1>;
541 ranges = <0 0x4000 0x1000>;
544 compatible = "ti,omap4-dsi";
548 reg-names = "proto", "phy", "pll";
549 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
552 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
553 clock-names = "fck", "sys_clk";
558 compatible = "ti,sysc-omap2", "ti,sysc";
562 reg-names = "rev", "sysc", "syss";
563 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
566 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
567 SYSC_OMAP2_ENAWAKEUP |
568 SYSC_OMAP2_SOFTRESET |
569 SYSC_OMAP2_AUTOIDLE)>;
571 #address-cells = <1>;
573 ranges = <0 0x5000 0x1000>;
576 compatible = "ti,omap4-dsi";
580 reg-names = "proto", "phy", "pll";
581 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
584 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
585 clock-names = "fck", "sys_clk";
590 compatible = "ti,sysc-omap4", "ti,sysc";
593 reg-names = "rev", "sysc";
595 * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
596 * but HDMI audio will fail with them.
598 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
600 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
601 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
602 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
603 clock-names = "fck", "dss_clk";
604 #address-cells = <1>;
606 ranges = <0 0x6000 0x2000>;
609 compatible = "ti,omap4-hdmi";
614 reg-names = "wp", "pll", "phy", "core";
615 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
618 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
619 clock-names = "fck", "sys_clk";
621 dma-names = "audio_tx";
629 #include "omap4-l4.dtsi"
630 #include "omap4-l4-abe.dtsi"
631 #include "omap44xx-clocks.dtsi"
635 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
641 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
647 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
652 prm_device: prm@1b00 {
653 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";