1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
6 #include <dt-bindings/bus/ti-sysc.h>
7 #include <dt-bindings/clock/omap4.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/omap.h>
11 #include <dt-bindings/clock/omap4.h>
14 compatible = "ti,omap4430", "ti,omap4";
15 interrupt-parent = <&wakeupgen>;
38 compatible = "arm,cortex-a9";
40 next-level-cache = <&L2>;
43 clocks = <&dpll_mpu_ck>;
46 clock-latency = <300000>; /* From omap-cpufreq driver */
49 compatible = "arm,cortex-a9";
51 next-level-cache = <&L2>;
57 * Note that 4430 needs cross trigger interface (CTI) supported
58 * before we can configure the interrupts. This means sampling
59 * events are not supported for pmu. Note that 4460 does not use
60 * CTI, see also 4460.dtsi.
63 compatible = "arm,cortex-a9-pmu";
64 ti,hwmods = "debugss";
67 gic: interrupt-controller@48241000 {
68 compatible = "arm,cortex-a9-gic";
70 #interrupt-cells = <3>;
71 reg = <0x48241000 0x1000>,
73 interrupt-parent = <&gic>;
76 L2: cache-controller@48242000 {
77 compatible = "arm,pl310-cache";
78 reg = <0x48242000 0x1000>;
83 local-timer@48240600 {
84 compatible = "arm,cortex-a9-twd-timer";
85 clocks = <&mpu_periphclk>;
86 reg = <0x48240600 0x20>;
87 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
88 interrupt-parent = <&gic>;
91 wakeupgen: interrupt-controller@48281000 {
92 compatible = "ti,omap4-wugen-mpu";
94 #interrupt-cells = <3>;
95 reg = <0x48281000 0x1000>;
96 interrupt-parent = <&gic>;
100 * The soc node represents the soc top level view. It is used for IPs
101 * that are not memory mapped in the MPU view or for the MPU itself.
104 compatible = "ti,omap-infra";
106 compatible = "ti,omap4-mpu";
112 compatible = "ti,ivahd";
118 * XXX: Use a flat representation of the OMAP4 interconnect.
119 * The real OMAP interconnect network is quite complex.
120 * Since it will not bring real advantage to represent that in DT for
121 * the moment, just use a fake OCP bus entry to represent the whole bus
125 compatible = "ti,omap4-l3-noc", "simple-bus";
126 #address-cells = <1>;
129 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
130 reg = <0x44000000 0x1000>,
133 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
136 l4_wkup: interconnect@4a300000 {
139 l4_cfg: interconnect@4a000000 {
142 l4_per: interconnect@48000000 {
145 l4_abe: interconnect@40100000 {
148 ocmcram: sram@40304000 {
149 compatible = "mmio-sram";
150 reg = <0x40304000 0xa000>; /* 40k */
153 gpmc: gpmc@50000000 {
154 compatible = "ti,omap4430-gpmc";
155 reg = <0x50000000 0x1000>;
156 #address-cells = <2>;
158 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
162 gpmc,num-waitpins = <4>;
165 clocks = <&l3_div_ck>;
167 interrupt-controller;
168 #interrupt-cells = <2>;
173 target-module@52000000 {
174 compatible = "ti,sysc-omap4", "ti,sysc";
176 reg = <0x52000000 0x4>,
178 reg-names = "rev", "sysc";
179 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
180 ti,sysc-midle = <SYSC_IDLE_FORCE>,
183 <SYSC_IDLE_SMART_WKUP>;
184 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
187 <SYSC_IDLE_SMART_WKUP>;
188 ti,sysc-delay-us = <2>;
189 clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
191 #address-cells = <1>;
193 ranges = <0 0x52000000 0x1000000>;
195 /* No child device binding, driver in staging */
198 target-module@55082000 {
199 compatible = "ti,sysc-omap2", "ti,sysc";
200 reg = <0x55082000 0x4>,
203 reg-names = "rev", "sysc", "syss";
204 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
207 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
208 SYSC_OMAP2_SOFTRESET |
209 SYSC_OMAP2_AUTOIDLE)>;
210 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
212 resets = <&prm_core 2>;
213 reset-names = "rstctrl";
214 ranges = <0x0 0x55082000 0x100>;
216 #address-cells = <1>;
219 compatible = "ti,omap4-iommu";
221 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
223 ti,iommu-bus-err-back;
227 target-module@4012c000 {
228 compatible = "ti,sysc-omap4", "ti,sysc";
229 reg = <0x4012c000 0x4>,
231 reg-names = "rev", "sysc";
232 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
233 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
236 <SYSC_IDLE_SMART_WKUP>;
237 clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
239 #address-cells = <1>;
241 ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
242 <0x4902c000 0x4902c000 0x1000>; /* L3 */
244 /* No child device binding or driver in mainline */
248 compatible = "ti,omap4-dmm";
249 reg = <0x4e000000 0x800>;
250 interrupts = <0 113 0x4>;
254 emif1: emif@4c000000 {
255 compatible = "ti,emif-4d";
256 reg = <0x4c000000 0x100>;
257 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
261 hw-caps-read-idle-ctrl;
262 hw-caps-ll-interface;
266 emif2: emif@4d000000 {
267 compatible = "ti,emif-4d";
268 reg = <0x4d000000 0x100>;
269 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
273 hw-caps-read-idle-ctrl;
274 hw-caps-ll-interface;
279 compatible = "ti,omap4-dsp";
280 ti,bootreg = <&scm_conf 0x304 0>;
282 resets = <&prm_tesla 0>;
283 clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
284 firmware-name = "omap4-dsp-fw.xe64T";
285 mboxes = <&mailbox &mbox_dsp>;
290 compatible = "ti,omap4-ipu";
291 reg = <0x55020000 0x10000>;
294 resets = <&prm_core 0>, <&prm_core 1>;
295 clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
296 firmware-name = "omap4-ipu-fw.xem3";
297 mboxes = <&mailbox &mbox_ipu>;
301 aes1_target: target-module@4b501000 {
302 compatible = "ti,sysc-omap2", "ti,sysc";
303 reg = <0x4b501080 0x4>,
306 reg-names = "rev", "sysc", "syss";
307 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
308 SYSC_OMAP2_AUTOIDLE)>;
309 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
312 <SYSC_IDLE_SMART_WKUP>;
314 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
315 clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
317 #address-cells = <1>;
319 ranges = <0x0 0x4b501000 0x1000>;
322 compatible = "ti,omap4-aes";
324 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
325 dmas = <&sdma 111>, <&sdma 110>;
326 dma-names = "tx", "rx";
330 aes2_target: target-module@4b701000 {
331 compatible = "ti,sysc-omap2", "ti,sysc";
332 reg = <0x4b701080 0x4>,
335 reg-names = "rev", "sysc", "syss";
336 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
337 SYSC_OMAP2_AUTOIDLE)>;
338 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
341 <SYSC_IDLE_SMART_WKUP>;
343 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
344 clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
346 #address-cells = <1>;
348 ranges = <0x0 0x4b701000 0x1000>;
351 compatible = "ti,omap4-aes";
353 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
354 dmas = <&sdma 114>, <&sdma 113>;
355 dma-names = "tx", "rx";
359 sham_target: target-module@4b100000 {
360 compatible = "ti,sysc-omap3-sham", "ti,sysc";
361 reg = <0x4b100100 0x4>,
364 reg-names = "rev", "sysc", "syss";
365 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
366 SYSC_OMAP2_AUTOIDLE)>;
367 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
371 /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
372 clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
374 #address-cells = <1>;
376 ranges = <0x0 0x4b100000 0x1000>;
379 compatible = "ti,omap4-sham";
381 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
387 abb_mpu: regulator-abb-mpu {
388 compatible = "ti,abb-v2";
389 regulator-name = "abb_mpu";
390 #address-cells = <0>;
392 ti,tranxdone-status-mask = <0x80>;
393 clocks = <&sys_clkin_ck>;
394 ti,settling-time = <50>;
395 ti,clock-cycles = <16>;
400 abb_iva: regulator-abb-iva {
401 compatible = "ti,abb-v2";
402 regulator-name = "abb_iva";
403 #address-cells = <0>;
405 ti,tranxdone-status-mask = <0x80000000>;
406 clocks = <&sys_clkin_ck>;
407 ti,settling-time = <50>;
408 ti,clock-cycles = <16>;
413 sgx_module: target-module@56000000 {
414 compatible = "ti,sysc-omap4", "ti,sysc";
415 reg = <0x5600fe00 0x4>,
417 reg-names = "rev", "sysc";
418 ti,sysc-midle = <SYSC_IDLE_FORCE>,
421 <SYSC_IDLE_SMART_WKUP>;
422 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
425 <SYSC_IDLE_SMART_WKUP>;
426 clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
428 #address-cells = <1>;
430 ranges = <0 0x56000000 0x2000000>;
433 * Closed source PowerVR driver, no child device
434 * binding or driver in mainline
439 * DSS is only using l3 mapping without l4 as noted in the TRM
440 * "10.1.3 DSS Register Manual" for omap4460.
442 target-module@58000000 {
443 compatible = "ti,sysc-omap2", "ti,sysc";
444 reg = <0x58000000 4>,
446 reg-names = "rev", "syss";
448 power-domains = <&prm_dss>;
449 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
450 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
451 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
452 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
453 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
454 #address-cells = <1>;
456 ranges = <0 0x58000000 0x1000000>;
459 compatible = "ti,omap4-dss";
462 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
464 #address-cells = <1>;
466 ranges = <0 0 0x1000000>;
469 compatible = "ti,sysc-omap2", "ti,sysc";
473 reg-names = "rev", "sysc", "syss";
474 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
477 ti,sysc-midle = <SYSC_IDLE_FORCE>,
480 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
481 SYSC_OMAP2_ENAWAKEUP |
482 SYSC_OMAP2_SOFTRESET |
483 SYSC_OMAP2_AUTOIDLE)>;
485 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
486 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
487 clock-names = "fck", "sys_clk";
488 #address-cells = <1>;
490 ranges = <0 0x1000 0x1000>;
493 compatible = "ti,omap4-dispc";
495 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
502 compatible = "ti,sysc-omap2", "ti,sysc";
506 reg-names = "rev", "sysc", "syss";
507 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
510 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
511 SYSC_OMAP2_AUTOIDLE)>;
513 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
514 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
515 clock-names = "fck", "sys_clk";
516 #address-cells = <1>;
518 ranges = <0 0x2000 0x1000>;
523 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
524 clock-names = "fck", "ick";
529 compatible = "ti,sysc-omap2", "ti,sysc";
532 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
533 clock-names = "sys_clk";
534 #address-cells = <1>;
536 ranges = <0 0x3000 0x1000>;
539 compatible = "ti,omap4-venc";
542 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
548 compatible = "ti,sysc-omap2", "ti,sysc";
552 reg-names = "rev", "sysc", "syss";
553 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
556 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
557 SYSC_OMAP2_ENAWAKEUP |
558 SYSC_OMAP2_SOFTRESET |
559 SYSC_OMAP2_AUTOIDLE)>;
561 #address-cells = <1>;
563 ranges = <0 0x4000 0x1000>;
566 compatible = "ti,omap4-dsi";
570 reg-names = "proto", "phy", "pll";
571 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
574 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
575 clock-names = "fck", "sys_clk";
577 #address-cells = <1>;
583 compatible = "ti,sysc-omap2", "ti,sysc";
587 reg-names = "rev", "sysc", "syss";
588 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
591 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
592 SYSC_OMAP2_ENAWAKEUP |
593 SYSC_OMAP2_SOFTRESET |
594 SYSC_OMAP2_AUTOIDLE)>;
596 #address-cells = <1>;
598 ranges = <0 0x5000 0x1000>;
601 compatible = "ti,omap4-dsi";
605 reg-names = "proto", "phy", "pll";
606 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
609 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
610 clock-names = "fck", "sys_clk";
612 #address-cells = <1>;
618 compatible = "ti,sysc-omap4", "ti,sysc";
621 reg-names = "rev", "sysc";
623 * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
624 * but HDMI audio will fail with them.
626 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
628 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
629 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
630 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
631 clock-names = "fck", "dss_clk";
632 #address-cells = <1>;
634 ranges = <0 0x6000 0x2000>;
637 compatible = "ti,omap4-hdmi";
642 reg-names = "wp", "pll", "phy", "core";
643 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
646 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
647 clock-names = "fck", "sys_clk";
649 dma-names = "audio_tx";
657 #include "omap4-l4.dtsi"
658 #include "omap4-l4-abe.dtsi"
659 #include "omap44xx-clocks.dtsi"
663 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
665 #power-domain-cells = <0>;
669 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
672 #power-domain-cells = <0>;
676 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
678 #power-domain-cells = <0>;
681 prm_always_on_core: prm@600 {
682 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
684 #power-domain-cells = <0>;
688 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
691 #power-domain-cells = <0>;
695 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
698 #power-domain-cells = <0>;
702 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
703 reg = <0x1000 0x100>;
704 #power-domain-cells = <0>;
708 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
709 reg = <0x1100 0x100>;
710 #power-domain-cells = <0>;
714 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
715 reg = <0x1200 0x100>;
716 #power-domain-cells = <0>;
719 prm_l3init: prm@1300 {
720 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
721 reg = <0x1300 0x100>;
722 #power-domain-cells = <0>;
725 prm_l4per: prm@1400 {
726 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
727 reg = <0x1400 0x100>;
728 #power-domain-cells = <0>;
731 prm_cefuse: prm@1600 {
732 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
733 reg = <0x1600 0x100>;
734 #power-domain-cells = <0>;
738 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
739 reg = <0x1700 0x100>;
740 #power-domain-cells = <0>;
744 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
745 reg = <0x1900 0x100>;
746 #power-domain-cells = <0>;
750 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
752 #power-domain-cells = <0>;
755 prm_device: prm@1b00 {
756 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
762 /* Preferred always-on timer for clockevent */
767 assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
768 assigned-clock-parents = <&sys_32k_ck>;