arch/arm/boot/dts/omap4.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5
   6 #include <dt-bindings/bus/ti-sysc.h>
   7 #include <dt-bindings/clock/omap4.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/pinctrl/omap.h>
  11 #include <dt-bindings/clock/omap4.h>
  12
  13 / {
  14         compatible = "ti,omap4430", "ti,omap4";
  15         interrupt-parent = <&wakeupgen>;
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18         chosen { };
  19
  20         aliases {
  21                 i2c0 = &i2c1;
  22                 i2c1 = &i2c2;
  23                 i2c2 = &i2c3;
  24                 i2c3 = &i2c4;
  25                 mmc0 = &mmc1;
  26                 mmc1 = &mmc2;
  27                 mmc2 = &mmc3;
  28                 mmc3 = &mmc4;
  29                 mmc4 = &mmc5;
  30                 serial0 = &uart1;
  31                 serial1 = &uart2;
  32                 serial2 = &uart3;
  33                 serial3 = &uart4;
  34                 rproc0 = &dsp;
  35                 rproc1 = &ipu;
  36         };
  37
  38         cpus {
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 cpu@0 {
  43                         compatible = "arm,cortex-a9";
  44                         device_type = "cpu";
  45                         next-level-cache = <&L2>;
  46                         reg = <0x0>;
  47
  48                         clocks = <&dpll_mpu_ck>;
  49                         clock-names = "cpu";
  50
  51                         clock-latency = <300000>; /* From omap-cpufreq driver */
  52                 };
  53                 cpu@1 {
  54                         compatible = "arm,cortex-a9";
  55                         device_type = "cpu";
  56                         next-level-cache = <&L2>;
  57                         reg = <0x1>;
  58                 };
  59         };
  60
  61         /*
  62          * Note that 4430 needs cross trigger interface (CTI) supported
  63          * before we can configure the interrupts. This means sampling
  64          * events are not supported for pmu. Note that 4460 does not use
  65          * CTI, see also 4460.dtsi.
  66          */
  67         pmu {
  68                 compatible = "arm,cortex-a9-pmu";
  69                 ti,hwmods = "debugss";
  70         };
  71
  72         gic: interrupt-controller@48241000 {
  73                 compatible = "arm,cortex-a9-gic";
  74                 interrupt-controller;
  75                 #interrupt-cells = <3>;
  76                 reg = <0x48241000 0x1000>,
  77                       <0x48240100 0x0100>;
  78                 interrupt-parent = <&gic>;
  79         };
  80
  81         L2: cache-controller@48242000 {
  82                 compatible = "arm,pl310-cache";
  83                 reg = <0x48242000 0x1000>;
  84                 cache-unified;
  85                 cache-level = <2>;
  86         };
  87
  88         local-timer@48240600 {
  89                 compatible = "arm,cortex-a9-twd-timer";
  90                 clocks = <&mpu_periphclk>;
  91                 reg = <0x48240600 0x20>;
  92                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
  93                 interrupt-parent = <&gic>;
  94         };
  95
  96         wakeupgen: interrupt-controller@48281000 {
  97                 compatible = "ti,omap4-wugen-mpu";
  98                 interrupt-controller;
  99                 #interrupt-cells = <3>;
 100                 reg = <0x48281000 0x1000>;
 101                 interrupt-parent = <&gic>;
 102         };
 103
 104         /*
 105          * The soc node represents the soc top level view. It is used for IPs
 106          * that are not memory mapped in the MPU view or for the MPU itself.
 107          */
 108         soc {
 109                 compatible = "ti,omap-infra";
 110                 mpu {
 111                         compatible = "ti,omap4-mpu";
 112                         ti,hwmods = "mpu";
 113                         sram = <&ocmcram>;
 114                 };
 115         };
 116
 117         /*
 118          * XXX: Use a flat representation of the OMAP4 interconnect.
 119          * The real OMAP interconnect network is quite complex.
 120          * Since it will not bring real advantage to represent that in DT for
 121          * the moment, just use a fake OCP bus entry to represent the whole bus
 122          * hierarchy.
 123          */
 124         ocp {
 125                 compatible = "ti,omap4-l3-noc", "simple-bus";
 126                 #address-cells = <1>;
 127                 #size-cells = <1>;
 128                 ranges;
 129                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 130                 reg = <0x44000000 0x1000>,
 131                       <0x44800000 0x2000>,
 132                       <0x45000000 0x1000>;
 133                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 134                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 135
 136                 l4_wkup: interconnect@4a300000 {
 137                 };
 138
 139                 l4_cfg: interconnect@4a000000 {
 140                 };
 141
 142                 l4_per: interconnect@48000000 {
 143                 };
 144
 145                 l4_abe: interconnect@40100000 {
 146                 };
 147
 148                 ocmcram: sram@40304000 {
 149                         compatible = "mmio-sram";
 150                         reg = <0x40304000 0xa000>; /* 40k */
 151                 };
 152
 153                 target-module@50000000 {
 154                         compatible = "ti,sysc-omap2", "ti,sysc";
 155                         reg = <0x50000000 4>,
 156                               <0x50000010 4>,
 157                               <0x50000014 4>;
 158                         reg-names = "rev", "sysc", "syss";
 159                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 160                                         <SYSC_IDLE_NO>,
 161                                         <SYSC_IDLE_SMART>;
 162                         ti,syss-mask = <1>;
 163                         ti,no-idle-on-init;
 164                         clocks = <&l3_2_clkctrl OMAP4_GPMC_CLKCTRL 0>;
 165                         clock-names = "fck";
 166                         #address-cells = <1>;
 167                         #size-cells = <1>;
 168                         ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
 169                                  <0x00000000 0x00000000 0x40000000>; /* data */
 170
 171                         gpmc: gpmc@50000000 {
 172                                 compatible = "ti,omap4430-gpmc";
 173                                 reg = <0x50000000 0x1000>;
 174                                 #address-cells = <2>;
 175                                 #size-cells = <1>;
 176                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 177                                 dmas = <&sdma 4>;
 178                                 dma-names = "rxtx";
 179                                 gpmc,num-cs = <8>;
 180                                 gpmc,num-waitpins = <4>;
 181                                 clocks = <&l3_div_ck>;
 182                                 clock-names = "fck";
 183                                 interrupt-controller;
 184                                 #interrupt-cells = <2>;
 185                                 gpio-controller;
 186                                 #gpio-cells = <2>;
 187                         };
 188                 };
 189
 190                 target-module@52000000 {
 191                         compatible = "ti,sysc-omap4", "ti,sysc";
 192                         ti,hwmods = "iss";
 193                         reg = <0x52000000 0x4>,
 194                               <0x52000010 0x4>;
 195                         reg-names = "rev", "sysc";
 196                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 197                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 198                                         <SYSC_IDLE_NO>,
 199                                         <SYSC_IDLE_SMART>,
 200                                         <SYSC_IDLE_SMART_WKUP>;
 201                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 202                                         <SYSC_IDLE_NO>,
 203                                         <SYSC_IDLE_SMART>,
 204                                         <SYSC_IDLE_SMART_WKUP>;
 205                         ti,sysc-delay-us = <2>;
 206                         power-domains = <&prm_cam>;
 207                         clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
 208                         clock-names = "fck";
 209                         #address-cells = <1>;
 210                         #size-cells = <1>;
 211                         ranges = <0 0x52000000 0x1000000>;
 212
 213                         /* No child device binding, driver in staging */
 214                 };
 215
 216                 target-module@55082000 {
 217                         compatible = "ti,sysc-omap2", "ti,sysc";
 218                         reg = <0x55082000 0x4>,
 219                               <0x55082010 0x4>,
 220                               <0x55082014 0x4>;
 221                         reg-names = "rev", "sysc", "syss";
 222                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 223                                         <SYSC_IDLE_NO>,
 224                                         <SYSC_IDLE_SMART>;
 225                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 226                                          SYSC_OMAP2_SOFTRESET |
 227                                          SYSC_OMAP2_AUTOIDLE)>;
 228                         clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
 229                         clock-names = "fck";
 230                         resets = <&prm_core 2>;
 231                         reset-names = "rstctrl";
 232                         ranges = <0x0 0x55082000 0x100>;
 233                         #size-cells = <1>;
 234                         #address-cells = <1>;
 235
 236                         mmu_ipu: mmu@0 {
 237                                 compatible = "ti,omap4-iommu";
 238                                 reg = <0x0 0x100>;
 239                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 240                                 #iommu-cells = <0>;
 241                                 ti,iommu-bus-err-back;
 242                         };
 243                 };
 244
 245                 target-module@4012c000 {
 246                         compatible = "ti,sysc-omap4", "ti,sysc";
 247                         reg = <0x4012c000 0x4>,
 248                               <0x4012c010 0x4>;
 249                         reg-names = "rev", "sysc";
 250                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 251                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 252                                         <SYSC_IDLE_NO>,
 253                                         <SYSC_IDLE_SMART>,
 254                                         <SYSC_IDLE_SMART_WKUP>;
 255                         clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
 256                         clock-names = "fck";
 257                         #address-cells = <1>;
 258                         #size-cells = <1>;
 259                         ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
 260                                  <0x4902c000 0x4902c000 0x1000>; /* L3 */
 261
 262                         /* No child device binding or driver in mainline */
 263                 };
 264
 265                 dmm@4e000000 {
 266                         compatible = "ti,omap4-dmm";
 267                         reg = <0x4e000000 0x800>;
 268                         interrupts = <0 113 0x4>;
 269                         ti,hwmods = "dmm";
 270                 };
 271
 272                 emif1: emif@4c000000 {
 273                         compatible = "ti,emif-4d";
 274                         reg = <0x4c000000 0x100>;
 275                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 276                         ti,hwmods = "emif1";
 277                         ti,no-idle-on-init;
 278                         phy-type = <1>;
 279                         hw-caps-read-idle-ctrl;
 280                         hw-caps-ll-interface;
 281                         hw-caps-temp-alert;
 282                 };
 283
 284                 emif2: emif@4d000000 {
 285                         compatible = "ti,emif-4d";
 286                         reg = <0x4d000000 0x100>;
 287                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 288                         ti,hwmods = "emif2";
 289                         ti,no-idle-on-init;
 290                         phy-type = <1>;
 291                         hw-caps-read-idle-ctrl;
 292                         hw-caps-ll-interface;
 293                         hw-caps-temp-alert;
 294                 };
 295
 296                 dsp: dsp {
 297                         compatible = "ti,omap4-dsp";
 298                         ti,bootreg = <&scm_conf 0x304 0>;
 299                         iommus = <&mmu_dsp>;
 300                         resets = <&prm_tesla 0>;
 301                         clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
 302                         firmware-name = "omap4-dsp-fw.xe64T";
 303                         mboxes = <&mailbox &mbox_dsp>;
 304                         status = "disabled";
 305                 };
 306
 307                 ipu: ipu@55020000 {
 308                         compatible = "ti,omap4-ipu";
 309                         reg = <0x55020000 0x10000>;
 310                         reg-names = "l2ram";
 311                         iommus = <&mmu_ipu>;
 312                         resets = <&prm_core 0>, <&prm_core 1>;
 313                         clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
 314                         firmware-name = "omap4-ipu-fw.xem3";
 315                         mboxes = <&mailbox &mbox_ipu>;
 316                         status = "disabled";
 317                 };
 318
 319                 aes1_target: target-module@4b501000 {
 320                         compatible = "ti,sysc-omap2", "ti,sysc";
 321                         reg = <0x4b501080 0x4>,
 322                               <0x4b501084 0x4>,
 323                               <0x4b501088 0x4>;
 324                         reg-names = "rev", "sysc", "syss";
 325                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 326                                          SYSC_OMAP2_AUTOIDLE)>;
 327                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 328                                         <SYSC_IDLE_NO>,
 329                                         <SYSC_IDLE_SMART>,
 330                                         <SYSC_IDLE_SMART_WKUP>;
 331                         ti,syss-mask = <1>;
 332                         /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
 333                         clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
 334                         clock-names = "fck";
 335                         #address-cells = <1>;
 336                         #size-cells = <1>;
 337                         ranges = <0x0 0x4b501000 0x1000>;
 338
 339                         aes1: aes@0 {
 340                                 compatible = "ti,omap4-aes";
 341                                 reg = <0 0xa0>;
 342                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 343                                 dmas = <&sdma 111>, <&sdma 110>;
 344                                 dma-names = "tx", "rx";
 345                         };
 346                 };
 347
 348                 aes2_target: target-module@4b701000 {
 349                         compatible = "ti,sysc-omap2", "ti,sysc";
 350                         reg = <0x4b701080 0x4>,
 351                               <0x4b701084 0x4>,
 352                               <0x4b701088 0x4>;
 353                         reg-names = "rev", "sysc", "syss";
 354                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 355                                          SYSC_OMAP2_AUTOIDLE)>;
 356                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 357                                         <SYSC_IDLE_NO>,
 358                                         <SYSC_IDLE_SMART>,
 359                                         <SYSC_IDLE_SMART_WKUP>;
 360                         ti,syss-mask = <1>;
 361                         /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
 362                         clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
 363                         clock-names = "fck";
 364                         #address-cells = <1>;
 365                         #size-cells = <1>;
 366                         ranges = <0x0 0x4b701000 0x1000>;
 367
 368                         aes2: aes@0 {
 369                                 compatible = "ti,omap4-aes";
 370                                 reg = <0 0xa0>;
 371                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 372                                 dmas = <&sdma 114>, <&sdma 113>;
 373                                 dma-names = "tx", "rx";
 374                         };
 375                 };
 376
 377                 sham_target: target-module@4b100000 {
 378                         compatible = "ti,sysc-omap3-sham", "ti,sysc";
 379                         reg = <0x4b100100 0x4>,
 380                               <0x4b100110 0x4>,
 381                               <0x4b100114 0x4>;
 382                         reg-names = "rev", "sysc", "syss";
 383                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 384                                          SYSC_OMAP2_AUTOIDLE)>;
 385                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 386                                         <SYSC_IDLE_NO>,
 387                                         <SYSC_IDLE_SMART>;
 388                         ti,syss-mask = <1>;
 389                         /* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
 390                         clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
 391                         clock-names = "fck";
 392                         #address-cells = <1>;
 393                         #size-cells = <1>;
 394                         ranges = <0x0 0x4b100000 0x1000>;
 395
 396                         sham: sham@0 {
 397                                 compatible = "ti,omap4-sham";
 398                                 reg = <0 0x300>;
 399                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 400                                 dmas = <&sdma 119>;
 401                                 dma-names = "rx";
 402                         };
 403                 };
 404
 405                 abb_mpu: regulator-abb-mpu {
 406                         compatible = "ti,abb-v2";
 407                         regulator-name = "abb_mpu";
 408                         #address-cells = <0>;
 409                         #size-cells = <0>;
 410                         ti,tranxdone-status-mask = <0x80>;
 411                         clocks = <&sys_clkin_ck>;
 412                         ti,settling-time = <50>;
 413                         ti,clock-cycles = <16>;
 414
 415                         status = "disabled";
 416                 };
 417
 418                 abb_iva: regulator-abb-iva {
 419                         compatible = "ti,abb-v2";
 420                         regulator-name = "abb_iva";
 421                         #address-cells = <0>;
 422                         #size-cells = <0>;
 423                         ti,tranxdone-status-mask = <0x80000000>;
 424                         clocks = <&sys_clkin_ck>;
 425                         ti,settling-time = <50>;
 426                         ti,clock-cycles = <16>;
 427
 428                         status = "disabled";
 429                 };
 430
 431                 sgx_module: target-module@56000000 {
 432                         compatible = "ti,sysc-omap4", "ti,sysc";
 433                         reg = <0x5600fe00 0x4>,
 434                               <0x5600fe10 0x4>;
 435                         reg-names = "rev", "sysc";
 436                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 437                                         <SYSC_IDLE_NO>,
 438                                         <SYSC_IDLE_SMART>,
 439                                         <SYSC_IDLE_SMART_WKUP>;
 440                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 441                                         <SYSC_IDLE_NO>,
 442                                         <SYSC_IDLE_SMART>,
 443                                         <SYSC_IDLE_SMART_WKUP>;
 444                         power-domains = <&prm_gfx>;
 445                         clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
 446                         clock-names = "fck";
 447                         #address-cells = <1>;
 448                         #size-cells = <1>;
 449                         ranges = <0 0x56000000 0x2000000>;
 450
 451                         /*
 452                          * Closed source PowerVR driver, no child device
 453                          * binding or driver in mainline
 454                          */
 455                 };
 456
 457                 /*
 458                  * DSS is only using l3 mapping without l4 as noted in the TRM
 459                  * "10.1.3 DSS Register Manual" for omap4460.
 460                  */
 461                 target-module@58000000 {
 462                         compatible = "ti,sysc-omap2", "ti,sysc";
 463                         reg = <0x58000000 4>,
 464                               <0x58000014 4>;
 465                         reg-names = "rev", "syss";
 466                         ti,syss-mask = <1>;
 467                         power-domains = <&prm_dss>;
 468                         clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
 469                                  <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
 470                                  <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
 471                                  <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
 472                         clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
 473                         #address-cells = <1>;
 474                         #size-cells = <1>;
 475                         ranges = <0 0x58000000 0x1000000>;
 476
 477                         dss: dss@0 {
 478                                 compatible = "ti,omap4-dss";
 479                                 reg = <0 0x80>;
 480                                 status = "disabled";
 481                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
 482                                 clock-names = "fck";
 483                                 #address-cells = <1>;
 484                                 #size-cells = <1>;
 485                                 ranges = <0 0 0x1000000>;
 486
 487                                 target-module@1000 {
 488                                         compatible = "ti,sysc-omap2", "ti,sysc";
 489                                         reg = <0x1000 0x4>,
 490                                               <0x1010 0x4>,
 491                                               <0x1014 0x4>;
 492                                         reg-names = "rev", "sysc", "syss";
 493                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 494                                                         <SYSC_IDLE_NO>,
 495                                                         <SYSC_IDLE_SMART>;
 496                                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 497                                                         <SYSC_IDLE_NO>,
 498                                                         <SYSC_IDLE_SMART>;
 499                                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 500                                                          SYSC_OMAP2_ENAWAKEUP |
 501                                                          SYSC_OMAP2_SOFTRESET |
 502                                                          SYSC_OMAP2_AUTOIDLE)>;
 503                                         ti,syss-mask = <1>;
 504                                         clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
 505                                                  <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 506                                         clock-names = "fck", "sys_clk";
 507                                         #address-cells = <1>;
 508                                         #size-cells = <1>;
 509                                         ranges = <0 0x1000 0x1000>;
 510
 511                                         dispc@0 {
 512                                                 compatible = "ti,omap4-dispc";
 513                                                 reg = <0 0x1000>;
 514                                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 515                                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
 516                                                 clock-names = "fck";
 517                                         };
 518                                 };
 519
 520                                 target-module@2000 {
 521                                         compatible = "ti,sysc-omap2", "ti,sysc";
 522                                         reg = <0x2000 0x4>,
 523                                               <0x2010 0x4>,
 524                                               <0x2014 0x4>;
 525                                         reg-names = "rev", "sysc", "syss";
 526                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 527                                                         <SYSC_IDLE_NO>,
 528                                                         <SYSC_IDLE_SMART>;
 529                                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 530                                                          SYSC_OMAP2_AUTOIDLE)>;
 531                                         ti,syss-mask = <1>;
 532                                         clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
 533                                                  <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 534                                         clock-names = "fck", "sys_clk";
 535                                         #address-cells = <1>;
 536                                         #size-cells = <1>;
 537                                         ranges = <0 0x2000 0x1000>;
 538
 539                                         rfbi: encoder@0  {
 540                                                 reg = <0 0x1000>;
 541                                                 status = "disabled";
 542                                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
 543                                                 clock-names = "fck", "ick";
 544                                         };
 545                                 };
 546
 547                                 target-module@3000 {
 548                                         compatible = "ti,sysc-omap2", "ti,sysc";
 549                                         reg = <0x3000 0x4>;
 550                                         reg-names = "rev";
 551                                         clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 552                                         clock-names = "sys_clk";
 553                                         #address-cells = <1>;
 554                                         #size-cells = <1>;
 555                                         ranges = <0 0x3000 0x1000>;
 556
 557                                         venc: encoder@0 {
 558                                                 compatible = "ti,omap4-venc";
 559                                                 reg = <0 0x1000>;
 560                                                 status = "disabled";
 561                                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
 562                                                 clock-names = "fck";
 563                                         };
 564                                 };
 565
 566                                 target-module@4000 {
 567                                         compatible = "ti,sysc-omap2", "ti,sysc";
 568                                         reg = <0x4000 0x4>,
 569                                               <0x4010 0x4>,
 570                                               <0x4014 0x4>;
 571                                         reg-names = "rev", "sysc", "syss";
 572                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 573                                                         <SYSC_IDLE_NO>,
 574                                                         <SYSC_IDLE_SMART>;
 575                                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 576                                                          SYSC_OMAP2_ENAWAKEUP |
 577                                                          SYSC_OMAP2_SOFTRESET |
 578                                                          SYSC_OMAP2_AUTOIDLE)>;
 579                                         ti,syss-mask = <1>;
 580                                         #address-cells = <1>;
 581                                         #size-cells = <1>;
 582                                         ranges = <0 0x4000 0x1000>;
 583
 584                                         dsi1: encoder@0 {
 585                                                 compatible = "ti,omap4-dsi";
 586                                                 reg = <0 0x200>,
 587                                                       <0x200 0x40>,
 588                                                       <0x300 0x20>;
 589                                                 reg-names = "proto", "phy", "pll";
 590                                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 591                                                 status = "disabled";
 592                                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
 593                                                          <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 594                                                 clock-names = "fck", "sys_clk";
 595
 596                                                 #address-cells = <1>;
 597                                                 #size-cells = <0>;
 598                                         };
 599                                 };
 600
 601                                 target-module@5000 {
 602                                         compatible = "ti,sysc-omap2", "ti,sysc";
 603                                         reg = <0x5000 0x4>,
 604                                               <0x5010 0x4>,
 605                                               <0x5014 0x4>;
 606                                         reg-names = "rev", "sysc", "syss";
 607                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 608                                                         <SYSC_IDLE_NO>,
 609                                                         <SYSC_IDLE_SMART>;
 610                                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 611                                                          SYSC_OMAP2_ENAWAKEUP |
 612                                                          SYSC_OMAP2_SOFTRESET |
 613                                                          SYSC_OMAP2_AUTOIDLE)>;
 614                                         ti,syss-mask = <1>;
 615                                         #address-cells = <1>;
 616                                         #size-cells = <1>;
 617                                         ranges = <0 0x5000 0x1000>;
 618
 619                                         dsi2: encoder@0 {
 620                                                 compatible = "ti,omap4-dsi";
 621                                                 reg = <0 0x200>,
 622                                                       <0x200 0x40>,
 623                                                       <0x300 0x20>;
 624                                                 reg-names = "proto", "phy", "pll";
 625                                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 626                                                 status = "disabled";
 627                                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
 628                                                          <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 629                                                 clock-names = "fck", "sys_clk";
 630
 631                                                 #address-cells = <1>;
 632                                                 #size-cells = <0>;
 633                                         };
 634                                 };
 635
 636                                 target-module@6000 {
 637                                         compatible = "ti,sysc-omap4", "ti,sysc";
 638                                         reg = <0x6000 0x4>,
 639                                               <0x6010 0x4>;
 640                                         reg-names = "rev", "sysc";
 641                                         /*
 642                                          * Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
 643                                          * but HDMI audio will fail with them.
 644                                          */
 645                                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 646                                                         <SYSC_IDLE_NO>;
 647                                         ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
 648                                         clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
 649                                                  <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
 650                                         clock-names = "fck", "dss_clk";
 651                                         #address-cells = <1>;
 652                                         #size-cells = <1>;
 653                                         ranges = <0 0x6000 0x2000>;
 654
 655                                         hdmi: encoder@0 {
 656                                         compatible = "ti,omap4-hdmi";
 657                                                 reg = <0 0x200>,
 658                                                       <0x200 0x100>,
 659                                                       <0x300 0x100>,
 660                                                       <0x400 0x1000>;
 661                                                 reg-names = "wp", "pll", "phy", "core";
 662                                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 663                                                 status = "disabled";
 664                                                 clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
 665                                                          <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
 666                                                 clock-names = "fck", "sys_clk";
 667                                                 dmas = <&sdma 76>;
 668                                                 dma-names = "audio_tx";
 669                                         };
 670                                 };
 671                         };
 672                 };
 673
 674                 iva_hd_target: target-module@5a000000 {
 675                         compatible = "ti,sysc-omap4", "ti,sysc";
 676                         reg = <0x5a05a400 0x4>,
 677                               <0x5a05a410 0x4>;
 678                         reg-names = "rev", "sysc";
 679                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 680                                         <SYSC_IDLE_NO>,
 681                                         <SYSC_IDLE_SMART>;
 682                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 683                                         <SYSC_IDLE_NO>,
 684                                         <SYSC_IDLE_SMART>;
 685                         power-domains = <&prm_ivahd>;
 686                         resets = <&prm_ivahd 2>;
 687                         reset-names = "rstctrl";
 688                         clocks = <&ivahd_clkctrl OMAP4_IVA_CLKCTRL 0>;
 689                         clock-names = "fck";
 690                         #address-cells = <1>;
 691                         #size-cells = <1>;
 692                         ranges = <0x5a000000 0x5a000000 0x1000000>,
 693                                  <0x5b000000 0x5b000000 0x1000000>;
 694
 695                         iva {
 696                                 compatible = "ti,ivahd";
 697                         };
 698                 };
 699         };
 700 };
 701
 702 #include "omap4-l4.dtsi"
 703 #include "omap4-l4-abe.dtsi"
 704 #include "omap44xx-clocks.dtsi"
 705
 706 &prm {
 707         prm_mpu: prm@300 {
 708                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 709                 reg = <0x300 0x100>;
 710                 #power-domain-cells = <0>;
 711         };
 712
 713         prm_tesla: prm@400 {
 714                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 715                 reg = <0x400 0x100>;
 716                 #reset-cells = <1>;
 717                 #power-domain-cells = <0>;
 718         };
 719
 720         prm_abe: prm@500 {
 721                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 722                 reg = <0x500 0x100>;
 723                 #power-domain-cells = <0>;
 724         };
 725
 726         prm_always_on_core: prm@600 {
 727                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 728                 reg = <0x600 0x100>;
 729                 #power-domain-cells = <0>;
 730         };
 731
 732         prm_core: prm@700 {
 733                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 734                 reg = <0x700 0x100>;
 735                 #reset-cells = <1>;
 736                 #power-domain-cells = <0>;
 737         };
 738
 739         prm_ivahd: prm@f00 {
 740                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 741                 reg = <0xf00 0x100>;
 742                 #reset-cells = <1>;
 743                 #power-domain-cells = <0>;
 744         };
 745
 746         prm_cam: prm@1000 {
 747                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 748                 reg = <0x1000 0x100>;
 749                 #power-domain-cells = <0>;
 750         };
 751
 752         prm_dss: prm@1100 {
 753                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 754                 reg = <0x1100 0x100>;
 755                 #power-domain-cells = <0>;
 756         };
 757
 758         prm_gfx: prm@1200 {
 759                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 760                 reg = <0x1200 0x100>;
 761                 #power-domain-cells = <0>;
 762         };
 763
 764         prm_l3init: prm@1300 {
 765                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 766                 reg = <0x1300 0x100>;
 767                 #power-domain-cells = <0>;
 768         };
 769
 770         prm_l4per: prm@1400 {
 771                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 772                 reg = <0x1400 0x100>;
 773                 #power-domain-cells = <0>;
 774         };
 775
 776         prm_cefuse: prm@1600 {
 777                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 778                 reg = <0x1600 0x100>;
 779                 #power-domain-cells = <0>;
 780         };
 781
 782         prm_wkup: prm@1700 {
 783                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 784                 reg = <0x1700 0x100>;
 785                 #power-domain-cells = <0>;
 786         };
 787
 788         prm_emu: prm@1900 {
 789                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 790                 reg = <0x1900 0x100>;
 791                 #power-domain-cells = <0>;
 792         };
 793
 794         prm_dss: prm@1100 {
 795                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 796                 reg = <0x1100 0x40>;
 797                 #power-domain-cells = <0>;
 798         };
 799
 800         prm_device: prm@1b00 {
 801                 compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
 802                 reg = <0x1b00 0x40>;
 803                 #reset-cells = <1>;
 804         };
 805 };
 806
 807 /* Preferred always-on timer for clockevent */
 808 &timer1_target {
 809         ti,no-reset-on-init;
 810         ti,no-idle;
 811         timer@0 {
 812                 assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
 813                 assigned-clock-parents = <&sys_32k_ck>;
 814         };
 815 };