arch/arm/boot/dts/omap36xx.dtsi

   1 /*
   2  * Device Tree Source for OMAP3 SoC
   3  *
   4  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/bus/ti-sysc.h>
  12 #include <dt-bindings/media/omap3-isp.h>
  13
  14 #include "omap3.dtsi"
  15
  16 / {
  17         aliases {
  18                 serial3 = &uart4;
  19         };
  20
  21         cpus {
  22                 /* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */
  23                 cpu: cpu@0 {
  24                         operating-points-v2 = <&cpu0_opp_table>;
  25
  26                         vbb-supply = <&abb_mpu_iva>;
  27                         clock-latency = <300000>; /* From omap-cpufreq driver */
  28                         #cooling-cells = <2>;
  29                 };
  30         };
  31
  32         /* see Documentation/devicetree/bindings/opp/opp.txt */
  33         cpu0_opp_table: opp-table {
  34                 compatible = "operating-points-v2-ti-cpu";
  35                 syscon = <&scm_conf>;
  36
  37                 opp50-300000000 {
  38                         opp-hz = /bits/ 64 <300000000>;
  39                         /*
  40                          * we currently only select the max voltage from table
  41                          * Table 4-19 of the DM3730 Data sheet (SPRS685B)
  42                          * Format is:   cpu0-supply:    <target min max>
  43                          *              vbb-supply:     <target min max>
  44                          */
  45                         opp-microvolt = <1012500 1012500 1012500>,
  46                                          <1012500 1012500 1012500>;
  47                         /*
  48                          * first value is silicon revision bit mask
  49                          * second one is "speed binned" bit mask
  50                          */
  51                         opp-supported-hw = <0xffffffff 3>;
  52                         opp-suspend;
  53                 };
  54
  55                 opp100-600000000 {
  56                         opp-hz = /bits/ 64 <600000000>;
  57                         opp-microvolt = <1200000 1200000 1200000>,
  58                                          <1200000 1200000 1200000>;
  59                         opp-supported-hw = <0xffffffff 3>;
  60                 };
  61
  62                 opp130-800000000 {
  63                         opp-hz = /bits/ 64 <800000000>;
  64                         opp-microvolt = <1325000 1325000 1325000>,
  65                                          <1325000 1325000 1325000>;
  66                         opp-supported-hw = <0xffffffff 3>;
  67                 };
  68
  69                 opp1g-1000000000 {
  70                         opp-hz = /bits/ 64 <1000000000>;
  71                         opp-microvolt = <1375000 1375000 1375000>,
  72                                          <1375000 1375000 1375000>;
  73                         /* only on am/dm37x with speed-binned bit set */
  74                         opp-supported-hw = <0xffffffff 2>;
  75                         turbo-mode;
  76                 };
  77         };
  78
  79         opp_supply_mpu_iva: opp_supply {
  80                 compatible = "ti,omap-opp-supply";
  81                 ti,absolute-max-voltage-uv = <1375000>;
  82         };
  83
  84         ocp@68000000 {
  85                 uart4: serial@49042000 {
  86                         compatible = "ti,omap3-uart";
  87                         reg = <0x49042000 0x400>;
  88                         interrupts = <80>;
  89                         dmas = <&sdma 81 &sdma 82>;
  90                         dma-names = "tx", "rx";
  91                         ti,hwmods = "uart4";
  92                         clock-frequency = <48000000>;
  93                 };
  94
  95                 abb_mpu_iva: regulator-abb-mpu {
  96                         compatible = "ti,abb-v1";
  97                         regulator-name = "abb_mpu_iva";
  98                         #address-cells = <0>;
  99                         #size-cells = <0>;
 100                         reg = <0x483072f0 0x8>, <0x48306818 0x4>;
 101                         reg-names = "base-address", "int-address";
 102                         ti,tranxdone-status-mask = <0x4000000>;
 103                         clocks = <&sys_ck>;
 104                         ti,settling-time = <30>;
 105                         ti,clock-cycles = <8>;
 106                         ti,abb_info = <
 107                         /*uV            ABB     efuse   rbb_m   fbb_m   vset_m*/
 108                         1012500         0       0       0       0       0
 109                         1200000         0       0       0       0       0
 110                         1325000         0       0       0       0       0
 111                         1375000         1       0       0       0       0
 112                         >;
 113                 };
 114
 115                 omap3_pmx_core2: pinmux@480025a0 {
 116                         compatible = "ti,omap3-padconf", "pinctrl-single";
 117                         reg = <0x480025a0 0x5c>;
 118                         #address-cells = <1>;
 119                         #size-cells = <0>;
 120                         #pinctrl-cells = <1>;
 121                         #interrupt-cells = <1>;
 122                         interrupt-controller;
 123                         pinctrl-single,register-width = <16>;
 124                         pinctrl-single,function-mask = <0xff1f>;
 125                 };
 126
 127                 isp: isp@480bc000 {
 128                         compatible = "ti,omap3-isp";
 129                         reg = <0x480bc000 0x12fc
 130                                0x480bd800 0x0600>;
 131                         interrupts = <24>;
 132                         iommus = <&mmu_isp>;
 133                         syscon = <&scm_conf 0x2f0>;
 134                         ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
 135                         #clock-cells = <1>;
 136                         ports {
 137                                 #address-cells = <1>;
 138                                 #size-cells = <0>;
 139                         };
 140                 };
 141
 142                 bandgap: bandgap@48002524 {
 143                         reg = <0x48002524 0x4>;
 144                         compatible = "ti,omap36xx-bandgap";
 145                         #thermal-sensor-cells = <0>;
 146                 };
 147
 148                 target-module@480cb000 {
 149                         compatible = "ti,sysc-omap3630-sr", "ti,sysc";
 150                         ti,hwmods = "smartreflex_core";
 151                         reg = <0x480cb038 0x4>;
 152                         reg-names = "sysc";
 153                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
 154                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 155                                         <SYSC_IDLE_NO>,
 156                                         <SYSC_IDLE_SMART>;
 157                         clocks = <&sr2_fck>;
 158                         clock-names = "fck";
 159                         #address-cells = <1>;
 160                         #size-cells = <1>;
 161                         ranges = <0 0x480cb000 0x001000>;
 162
 163                         smartreflex_core: smartreflex@0 {
 164                                 compatible = "ti,omap3-smartreflex-core";
 165                                 reg = <0 0x400>;
 166                                 interrupts = <19>;
 167                         };
 168                 };
 169
 170                 target-module@480c9000 {
 171                         compatible = "ti,sysc-omap3630-sr", "ti,sysc";
 172                         ti,hwmods = "smartreflex_mpu_iva";
 173                         reg = <0x480c9038 0x4>;
 174                         reg-names = "sysc";
 175                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
 176                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 177                                         <SYSC_IDLE_NO>,
 178                                         <SYSC_IDLE_SMART>;
 179                         clocks = <&sr1_fck>;
 180                         clock-names = "fck";
 181                         #address-cells = <1>;
 182                         #size-cells = <1>;
 183                         ranges = <0 0x480c9000 0x001000>;
 184
 185
 186                         smartreflex_mpu_iva: smartreflex@480c9000 {
 187                                 compatible = "ti,omap3-smartreflex-mpu-iva";
 188                                 reg = <0 0x400>;
 189                                 interrupts = <18>;
 190                         };
 191                 };
 192
 193                 /*
 194                  * Note that the sysconfig register layout is a subset of the
 195                  * "ti,sysc-omap4" type register with just sidle and midle bits
 196                  * available while omap34xx has "ti,sysc-omap2" type sysconfig.
 197                  */
 198                 sgx_module: target-module@50000000 {
 199                         compatible = "ti,sysc-omap4", "ti,sysc";
 200                         reg = <0x5000fe00 0x4>,
 201                               <0x5000fe10 0x4>;
 202                         reg-names = "rev", "sysc";
 203                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 204                                         <SYSC_IDLE_NO>,
 205                                         <SYSC_IDLE_SMART>;
 206                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 207                                         <SYSC_IDLE_NO>,
 208                                         <SYSC_IDLE_SMART>;
 209                         clocks = <&sgx_fck>, <&sgx_ick>;
 210                         clock-names = "fck", "ick";
 211                         #address-cells = <1>;
 212                         #size-cells = <1>;
 213                         ranges = <0 0x50000000 0x2000000>;
 214
 215                         /*
 216                          * Closed source PowerVR driver, no child device
 217                          * binding or driver in mainline
 218                          */
 219                 };
 220         };
 221
 222         thermal_zones: thermal-zones {
 223                 #include "omap3-cpu-thermal.dtsi"
 224         };
 225 };
 226
 227 &sdma {
 228         compatible = "ti,omap3630-sdma", "ti,omap-sdma";
 229 };
 230
 231 /* OMAP3630 needs dss_96m_fck for VENC */
 232 &venc {
 233         clocks = <&dss_tv_fck>, <&dss_96m_fck>;
 234         clock-names = "fck", "tv_dac_clk";
 235 };
 236
 237 &ssi {
 238         status = "okay";
 239
 240         clocks = <&ssi_ssr_fck>,
 241                  <&ssi_sst_fck>,
 242                  <&ssi_ick>;
 243         clock-names = "ssi_ssr_fck",
 244                       "ssi_sst_fck",
 245                       "ssi_ick";
 246 };
 247
 248 /include/ "omap34xx-omap36xx-clocks.dtsi"
 249 /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
 250 /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
 251 /include/ "omap36xx-clocks.dtsi"