arch/arm/boot/dts/omap36xx.dtsi

   1 /*
   2  * Device Tree Source for OMAP3 SoC
   3  *
   4  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/bus/ti-sysc.h>
  12 #include <dt-bindings/media/omap3-isp.h>
  13
  14 #include "omap3.dtsi"
  15
  16 / {
  17         aliases {
  18                 serial3 = &uart4;
  19         };
  20
  21         cpus {
  22                 /* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */
  23                 cpu: cpu@0 {
  24                         operating-points-v2 = <&cpu0_opp_table>;
  25
  26                         clock-latency = <300000>; /* From omap-cpufreq driver */
  27                 };
  28         };
  29
  30         /* see Documentation/devicetree/bindings/opp/opp.txt */
  31         cpu0_opp_table: opp-table {
  32                 compatible = "operating-points-v2-ti-cpu";
  33                 syscon = <&scm_conf>;
  34
  35                 opp50-300000000 {
  36                         opp-hz = /bits/ 64 <300000000>;
  37                         /*
  38                          * we currently only select the max voltage from table
  39                          * Table 4-19 of the DM3730 Data sheet (SPRS685B)
  40                          * Format is: <target min max>
  41                          */
  42                         opp-microvolt = <1012500 1012500 1012500>;
  43                         /*
  44                          * first value is silicon revision bit mask
  45                          * second one is "speed binned" bit mask
  46                          */
  47                         opp-supported-hw = <0xffffffff 3>;
  48                         opp-suspend;
  49                 };
  50
  51                 opp100-600000000 {
  52                         opp-hz = /bits/ 64 <600000000>;
  53                         opp-microvolt = <1200000 1200000 1200000>;
  54                         opp-supported-hw = <0xffffffff 3>;
  55                 };
  56
  57                 opp130-800000000 {
  58                         opp-hz = /bits/ 64 <800000000>;
  59                         opp-microvolt = <1325000 1325000 1325000>;
  60                         opp-supported-hw = <0xffffffff 3>;
  61                 };
  62
  63                 opp1g-1000000000 {
  64                         opp-hz = /bits/ 64 <1000000000>;
  65                         opp-microvolt = <1375000 1375000 1375000>;
  66                         /* only on am/dm37x with speed-binned bit set */
  67                         opp-supported-hw = <0xffffffff 2>;
  68                         turbo-mode;
  69                 };
  70         };
  71
  72         ocp@68000000 {
  73                 uart4: serial@49042000 {
  74                         compatible = "ti,omap3-uart";
  75                         reg = <0x49042000 0x400>;
  76                         interrupts = <80>;
  77                         dmas = <&sdma 81 &sdma 82>;
  78                         dma-names = "tx", "rx";
  79                         ti,hwmods = "uart4";
  80                         clock-frequency = <48000000>;
  81                 };
  82
  83                 abb_mpu_iva: regulator-abb-mpu {
  84                         compatible = "ti,abb-v1";
  85                         regulator-name = "abb_mpu_iva";
  86                         #address-cells = <0>;
  87                         #size-cells = <0>;
  88                         reg = <0x483072f0 0x8>, <0x48306818 0x4>;
  89                         reg-names = "base-address", "int-address";
  90                         ti,tranxdone-status-mask = <0x4000000>;
  91                         clocks = <&sys_ck>;
  92                         ti,settling-time = <30>;
  93                         ti,clock-cycles = <8>;
  94                         ti,abb_info = <
  95                         /*uV            ABB     efuse   rbb_m   fbb_m   vset_m*/
  96                         1012500         0       0       0       0       0
  97                         1200000         0       0       0       0       0
  98                         1325000         0       0       0       0       0
  99                         1375000         1       0       0       0       0
 100                         >;
 101                 };
 102
 103                 omap3_pmx_core2: pinmux@480025a0 {
 104                         compatible = "ti,omap3-padconf", "pinctrl-single";
 105                         reg = <0x480025a0 0x5c>;
 106                         #address-cells = <1>;
 107                         #size-cells = <0>;
 108                         #pinctrl-cells = <1>;
 109                         #interrupt-cells = <1>;
 110                         interrupt-controller;
 111                         pinctrl-single,register-width = <16>;
 112                         pinctrl-single,function-mask = <0xff1f>;
 113                 };
 114
 115                 isp: isp@480bc000 {
 116                         compatible = "ti,omap3-isp";
 117                         reg = <0x480bc000 0x12fc
 118                                0x480bd800 0x0600>;
 119                         interrupts = <24>;
 120                         iommus = <&mmu_isp>;
 121                         syscon = <&scm_conf 0x2f0>;
 122                         ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
 123                         #clock-cells = <1>;
 124                         ports {
 125                                 #address-cells = <1>;
 126                                 #size-cells = <0>;
 127                         };
 128                 };
 129
 130                 bandgap: bandgap@48002524 {
 131                         reg = <0x48002524 0x4>;
 132                         compatible = "ti,omap36xx-bandgap";
 133                         #thermal-sensor-cells = <0>;
 134                 };
 135
 136                 target-module@480cb000 {
 137                         compatible = "ti,sysc-omap3630-sr", "ti,sysc";
 138                         ti,hwmods = "smartreflex_core";
 139                         reg = <0x480cb038 0x4>;
 140                         reg-names = "sysc";
 141                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
 142                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 143                                         <SYSC_IDLE_NO>,
 144                                         <SYSC_IDLE_SMART>;
 145                         clocks = <&sr2_fck>;
 146                         clock-names = "fck";
 147                         #address-cells = <1>;
 148                         #size-cells = <1>;
 149                         ranges = <0 0x480cb000 0x001000>;
 150
 151                         smartreflex_core: smartreflex@0 {
 152                                 compatible = "ti,omap3-smartreflex-core";
 153                                 reg = <0 0x400>;
 154                                 interrupts = <19>;
 155                         };
 156                 };
 157
 158                 target-module@480c9000 {
 159                         compatible = "ti,sysc-omap3630-sr", "ti,sysc";
 160                         ti,hwmods = "smartreflex_mpu_iva";
 161                         reg = <0x480c9038 0x4>;
 162                         reg-names = "sysc";
 163                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
 164                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 165                                         <SYSC_IDLE_NO>,
 166                                         <SYSC_IDLE_SMART>;
 167                         clocks = <&sr1_fck>;
 168                         clock-names = "fck";
 169                         #address-cells = <1>;
 170                         #size-cells = <1>;
 171                         ranges = <0 0x480c9000 0x001000>;
 172
 173
 174                         smartreflex_mpu_iva: smartreflex@480c9000 {
 175                                 compatible = "ti,omap3-smartreflex-mpu-iva";
 176                                 reg = <0 0x400>;
 177                                 interrupts = <18>;
 178                         };
 179                 };
 180
 181                 /*
 182                  * Note that the sysconfig register layout is a subset of the
 183                  * "ti,sysc-omap4" type register with just sidle and midle bits
 184                  * available while omap34xx has "ti,sysc-omap2" type sysconfig.
 185                  */
 186                 sgx_module: target-module@50000000 {
 187                         compatible = "ti,sysc-omap4", "ti,sysc";
 188                         reg = <0x5000fe00 0x4>,
 189                               <0x5000fe10 0x4>;
 190                         reg-names = "rev", "sysc";
 191                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 192                                         <SYSC_IDLE_NO>,
 193                                         <SYSC_IDLE_SMART>;
 194                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 195                                         <SYSC_IDLE_NO>,
 196                                         <SYSC_IDLE_SMART>;
 197                         clocks = <&sgx_fck>, <&sgx_ick>;
 198                         clock-names = "fck", "ick";
 199                         #address-cells = <1>;
 200                         #size-cells = <1>;
 201                         ranges = <0 0x50000000 0x2000000>;
 202
 203                         /*
 204                          * Closed source PowerVR driver, no child device
 205                          * binding or driver in mainline
 206                          */
 207                 };
 208         };
 209
 210         thermal_zones: thermal-zones {
 211                 #include "omap3-cpu-thermal.dtsi"
 212         };
 213 };
 214
 215 /* OMAP3630 needs dss_96m_fck for VENC */
 216 &venc {
 217         clocks = <&dss_tv_fck>, <&dss_96m_fck>;
 218         clock-names = "fck", "tv_dac_clk";
 219 };
 220
 221 &ssi {
 222         status = "ok";
 223
 224         clocks = <&ssi_ssr_fck>,
 225                  <&ssi_sst_fck>,
 226                  <&ssi_ick>;
 227         clock-names = "ssi_ssr_fck",
 228                       "ssi_sst_fck",
 229                       "ssi_ick";
 230 };
 231
 232 /include/ "omap34xx-omap36xx-clocks.dtsi"
 233 /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
 234 /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
 235 /include/ "omap36xx-clocks.dtsi"