2 * Device Tree Source for OMAP3 SoC
4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/media/omap3-isp.h>
22 /* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */
24 operating-points-v2 = <&cpu0_opp_table>;
26 vbb-supply = <&abb_mpu_iva>;
27 clock-latency = <300000>; /* From omap-cpufreq driver */
32 /* see Documentation/devicetree/bindings/opp/opp.txt */
33 cpu0_opp_table: opp-table {
34 compatible = "operating-points-v2-ti-cpu";
38 opp-hz = /bits/ 64 <300000000>;
40 * we currently only select the max voltage from table
41 * Table 4-19 of the DM3730 Data sheet (SPRS685B)
42 * Format is: cpu0-supply: <target min max>
43 * vbb-supply: <target min max>
45 opp-microvolt = <1012500 1012500 1012500>,
46 <1012500 1012500 1012500>;
48 * first value is silicon revision bit mask
49 * second one is "speed binned" bit mask
51 opp-supported-hw = <0xffffffff 3>;
56 opp-hz = /bits/ 64 <600000000>;
57 opp-microvolt = <1200000 1200000 1200000>,
58 <1200000 1200000 1200000>;
59 opp-supported-hw = <0xffffffff 3>;
63 opp-hz = /bits/ 64 <800000000>;
64 opp-microvolt = <1325000 1325000 1325000>,
65 <1325000 1325000 1325000>;
66 opp-supported-hw = <0xffffffff 3>;
70 opp-hz = /bits/ 64 <1000000000>;
71 opp-microvolt = <1375000 1375000 1375000>,
72 <1375000 1375000 1375000>;
73 /* only on am/dm37x with speed-binned bit set */
74 opp-supported-hw = <0xffffffff 2>;
79 opp_supply_mpu_iva: opp_supply {
80 compatible = "ti,omap-opp-supply";
81 ti,absolute-max-voltage-uv = <1375000>;
85 uart4: serial@49042000 {
86 compatible = "ti,omap3-uart";
87 reg = <0x49042000 0x400>;
89 dmas = <&sdma 81 &sdma 82>;
90 dma-names = "tx", "rx";
92 clock-frequency = <48000000>;
95 abb_mpu_iva: regulator-abb-mpu {
96 compatible = "ti,abb-v1";
97 regulator-name = "abb_mpu_iva";
100 reg = <0x483072f0 0x8>, <0x48306818 0x4>;
101 reg-names = "base-address", "int-address";
102 ti,tranxdone-status-mask = <0x4000000>;
104 ti,settling-time = <30>;
105 ti,clock-cycles = <8>;
107 /*uV ABB efuse rbb_m fbb_m vset_m*/
115 omap3_pmx_core2: pinmux@480025a0 {
116 compatible = "ti,omap3-padconf", "pinctrl-single";
117 reg = <0x480025a0 0x5c>;
118 #address-cells = <1>;
120 #pinctrl-cells = <1>;
121 #interrupt-cells = <1>;
122 interrupt-controller;
123 pinctrl-single,register-width = <16>;
124 pinctrl-single,function-mask = <0xff1f>;
128 compatible = "ti,omap3-isp";
129 reg = <0x480bc000 0x12fc
133 syscon = <&scm_conf 0x2f0>;
134 ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
137 #address-cells = <1>;
142 bandgap: bandgap@48002524 {
143 reg = <0x48002524 0x4>;
144 compatible = "ti,omap36xx-bandgap";
145 #thermal-sensor-cells = <0>;
148 target-module@480cb000 {
149 compatible = "ti,sysc-omap3630-sr", "ti,sysc";
150 ti,hwmods = "smartreflex_core";
151 reg = <0x480cb038 0x4>;
153 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
154 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
159 #address-cells = <1>;
161 ranges = <0 0x480cb000 0x001000>;
163 smartreflex_core: smartreflex@0 {
164 compatible = "ti,omap3-smartreflex-core";
170 target-module@480c9000 {
171 compatible = "ti,sysc-omap3630-sr", "ti,sysc";
172 ti,hwmods = "smartreflex_mpu_iva";
173 reg = <0x480c9038 0x4>;
175 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
176 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
181 #address-cells = <1>;
183 ranges = <0 0x480c9000 0x001000>;
186 smartreflex_mpu_iva: smartreflex@480c9000 {
187 compatible = "ti,omap3-smartreflex-mpu-iva";
194 * Note that the sysconfig register layout is a subset of the
195 * "ti,sysc-omap4" type register with just sidle and midle bits
196 * available while omap34xx has "ti,sysc-omap2" type sysconfig.
198 sgx_module: target-module@50000000 {
199 compatible = "ti,sysc-omap4", "ti,sysc";
200 reg = <0x5000fe00 0x4>,
202 reg-names = "rev", "sysc";
203 ti,sysc-midle = <SYSC_IDLE_FORCE>,
206 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
209 clocks = <&sgx_fck>, <&sgx_ick>;
210 clock-names = "fck", "ick";
211 #address-cells = <1>;
213 ranges = <0 0x50000000 0x2000000>;
216 * Closed source PowerVR driver, no child device
217 * binding or driver in mainline
222 thermal_zones: thermal-zones {
223 #include "omap3-cpu-thermal.dtsi"
228 compatible = "ti,omap3630-sdma", "ti,omap-sdma";
231 /* OMAP3630 needs dss_96m_fck for VENC */
233 clocks = <&dss_tv_fck>, <&dss_96m_fck>;
234 clock-names = "fck", "tv_dac_clk";
240 clocks = <&ssi_ssr_fck>,
243 clock-names = "ssi_ssr_fck",
248 /include/ "omap34xx-omap36xx-clocks.dtsi"
249 /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
250 /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
251 /include/ "omap36xx-clocks.dtsi"