2 * Device Tree Source for OMAP3 SoC
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/omap.h>
16 compatible = "ti,omap3430", "ti,omap3";
17 interrupt-parent = <&intc>;
36 compatible = "arm,cortex-a8";
43 clock-latency = <300000>; /* From omap-cpufreq driver */
48 compatible = "arm,cortex-a8-pmu";
49 reg = <0x54000000 0x800000>;
51 ti,hwmods = "debugss";
55 * The soc node represents the soc top level view. It is used for IPs
56 * that are not memory mapped in the MPU view or for the MPU itself.
59 compatible = "ti,omap-infra";
61 compatible = "ti,omap3-mpu";
66 compatible = "ti,iva2.2";
70 compatible = "ti,omap3-c64";
76 * XXX: Use a flat representation of the OMAP3 interconnect.
77 * The real OMAP interconnect network is quite complex.
78 * Since it will not bring real advantage to represent that in DT for
79 * the moment, just use a fake OCP bus entry to represent the whole bus
83 compatible = "ti,omap3-l3-smx", "simple-bus";
84 reg = <0x68000000 0x10000>;
89 ti,hwmods = "l3_main";
91 l4_core: l4@48000000 {
92 compatible = "ti,omap3-l4-core", "simple-bus";
95 ranges = <0 0x48000000 0x1000000>;
98 compatible = "ti,omap3-scm", "simple-bus";
99 reg = <0x2000 0x2000>;
100 #address-cells = <1>;
102 ranges = <0 0x2000 0x2000>;
104 omap3_pmx_core: pinmux@30 {
105 compatible = "ti,omap3-padconf",
108 #address-cells = <1>;
110 #pinctrl-cells = <1>;
111 #interrupt-cells = <1>;
112 interrupt-controller;
113 pinctrl-single,register-width = <16>;
114 pinctrl-single,function-mask = <0xff1f>;
117 scm_conf: scm_conf@270 {
118 compatible = "syscon", "simple-bus";
120 #address-cells = <1>;
122 ranges = <0 0x270 0x330>;
124 pbias_regulator: pbias_regulator@2b0 {
125 compatible = "ti,pbias-omap3", "ti,pbias-omap";
127 syscon = <&scm_conf>;
128 pbias_mmc_reg: pbias_mmc_omap2430 {
129 regulator-name = "pbias_mmc_omap2430";
130 regulator-min-microvolt = <1800000>;
131 regulator-max-microvolt = <3000000>;
136 #address-cells = <1>;
141 scm_clockdomains: clockdomains {
144 omap3_pmx_wkup: pinmux@a00 {
145 compatible = "ti,omap3-padconf",
148 #address-cells = <1>;
150 #pinctrl-cells = <1>;
151 #interrupt-cells = <1>;
152 interrupt-controller;
153 pinctrl-single,register-width = <16>;
154 pinctrl-single,function-mask = <0xff1f>;
160 compatible = "ti,omap3-aes";
162 reg = <0x480c5000 0x50>;
164 dmas = <&sdma 65 &sdma 66>;
165 dma-names = "tx", "rx";
169 compatible = "ti,omap3-prm";
170 reg = <0x48306000 0x4000>;
174 #address-cells = <1>;
178 prm_clockdomains: clockdomains {
183 compatible = "ti,omap3-cm";
184 reg = <0x48004000 0x4000>;
187 #address-cells = <1>;
191 cm_clockdomains: clockdomains {
195 counter32k: counter@48320000 {
196 compatible = "ti,omap-counter32k";
197 reg = <0x48320000 0x20>;
198 ti,hwmods = "counter_32k";
201 intc: interrupt-controller@48200000 {
202 compatible = "ti,omap3-intc";
203 interrupt-controller;
204 #interrupt-cells = <1>;
205 reg = <0x48200000 0x1000>;
208 sdma: dma-controller@48056000 {
209 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
210 reg = <0x48056000 0x1000>;
220 gpio1: gpio@48310000 {
221 compatible = "ti,omap3-gpio";
222 reg = <0x48310000 0x200>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
232 gpio2: gpio@49050000 {
233 compatible = "ti,omap3-gpio";
234 reg = <0x49050000 0x200>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
243 gpio3: gpio@49052000 {
244 compatible = "ti,omap3-gpio";
245 reg = <0x49052000 0x200>;
250 interrupt-controller;
251 #interrupt-cells = <2>;
254 gpio4: gpio@49054000 {
255 compatible = "ti,omap3-gpio";
256 reg = <0x49054000 0x200>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
265 gpio5: gpio@49056000 {
266 compatible = "ti,omap3-gpio";
267 reg = <0x49056000 0x200>;
272 interrupt-controller;
273 #interrupt-cells = <2>;
276 gpio6: gpio@49058000 {
277 compatible = "ti,omap3-gpio";
278 reg = <0x49058000 0x200>;
283 interrupt-controller;
284 #interrupt-cells = <2>;
287 uart1: serial@4806a000 {
288 compatible = "ti,omap3-uart";
289 reg = <0x4806a000 0x2000>;
290 interrupts-extended = <&intc 72>;
291 dmas = <&sdma 49 &sdma 50>;
292 dma-names = "tx", "rx";
294 clock-frequency = <48000000>;
297 uart2: serial@4806c000 {
298 compatible = "ti,omap3-uart";
299 reg = <0x4806c000 0x400>;
300 interrupts-extended = <&intc 73>;
301 dmas = <&sdma 51 &sdma 52>;
302 dma-names = "tx", "rx";
304 clock-frequency = <48000000>;
307 uart3: serial@49020000 {
308 compatible = "ti,omap3-uart";
309 reg = <0x49020000 0x400>;
310 interrupts-extended = <&intc 74>;
311 dmas = <&sdma 53 &sdma 54>;
312 dma-names = "tx", "rx";
314 clock-frequency = <48000000>;
318 compatible = "ti,omap3-i2c";
319 reg = <0x48070000 0x80>;
321 dmas = <&sdma 27 &sdma 28>;
322 dma-names = "tx", "rx";
323 #address-cells = <1>;
329 compatible = "ti,omap3-i2c";
330 reg = <0x48072000 0x80>;
332 dmas = <&sdma 29 &sdma 30>;
333 dma-names = "tx", "rx";
334 #address-cells = <1>;
340 compatible = "ti,omap3-i2c";
341 reg = <0x48060000 0x80>;
343 dmas = <&sdma 25 &sdma 26>;
344 dma-names = "tx", "rx";
345 #address-cells = <1>;
350 mailbox: mailbox@48094000 {
351 compatible = "ti,omap3-mailbox";
352 ti,hwmods = "mailbox";
353 reg = <0x48094000 0x200>;
356 ti,mbox-num-users = <2>;
357 ti,mbox-num-fifos = <2>;
359 ti,mbox-tx = <0 0 0>;
360 ti,mbox-rx = <1 0 0>;
364 mcspi1: spi@48098000 {
365 compatible = "ti,omap2-mcspi";
366 reg = <0x48098000 0x100>;
368 #address-cells = <1>;
370 ti,hwmods = "mcspi1";
380 dma-names = "tx0", "rx0", "tx1", "rx1",
381 "tx2", "rx2", "tx3", "rx3";
384 mcspi2: spi@4809a000 {
385 compatible = "ti,omap2-mcspi";
386 reg = <0x4809a000 0x100>;
388 #address-cells = <1>;
390 ti,hwmods = "mcspi2";
396 dma-names = "tx0", "rx0", "tx1", "rx1";
399 mcspi3: spi@480b8000 {
400 compatible = "ti,omap2-mcspi";
401 reg = <0x480b8000 0x100>;
403 #address-cells = <1>;
405 ti,hwmods = "mcspi3";
411 dma-names = "tx0", "rx0", "tx1", "rx1";
414 mcspi4: spi@480ba000 {
415 compatible = "ti,omap2-mcspi";
416 reg = <0x480ba000 0x100>;
418 #address-cells = <1>;
420 ti,hwmods = "mcspi4";
422 dmas = <&sdma 70>, <&sdma 71>;
423 dma-names = "tx0", "rx0";
426 hdqw1w: 1w@480b2000 {
427 compatible = "ti,omap3-1w";
428 reg = <0x480b2000 0x1000>;
434 compatible = "ti,omap3-hsmmc";
435 reg = <0x4809c000 0x200>;
439 dmas = <&sdma 61>, <&sdma 62>;
440 dma-names = "tx", "rx";
441 pbias-supply = <&pbias_mmc_reg>;
445 compatible = "ti,omap3-hsmmc";
446 reg = <0x480b4000 0x200>;
449 dmas = <&sdma 47>, <&sdma 48>;
450 dma-names = "tx", "rx";
454 compatible = "ti,omap3-hsmmc";
455 reg = <0x480ad000 0x200>;
458 dmas = <&sdma 77>, <&sdma 78>;
459 dma-names = "tx", "rx";
462 mmu_isp: mmu@480bd400 {
464 compatible = "ti,omap2-iommu";
465 reg = <0x480bd400 0x80>;
467 ti,hwmods = "mmu_isp";
468 ti,#tlb-entries = <8>;
471 mmu_iva: mmu@5d000000 {
473 compatible = "ti,omap2-iommu";
474 reg = <0x5d000000 0x80>;
476 ti,hwmods = "mmu_iva";
481 compatible = "ti,omap3-wdt";
482 reg = <0x48314000 0x80>;
483 ti,hwmods = "wd_timer2";
486 mcbsp1: mcbsp@48074000 {
487 compatible = "ti,omap3-mcbsp";
488 reg = <0x48074000 0xff>;
490 interrupts = <16>, /* OCP compliant interrupt */
491 <59>, /* TX interrupt */
492 <60>; /* RX interrupt */
493 interrupt-names = "common", "tx", "rx";
494 ti,buffer-size = <128>;
495 ti,hwmods = "mcbsp1";
498 dma-names = "tx", "rx";
499 clocks = <&mcbsp1_fck>;
504 mcbsp2: mcbsp@49022000 {
505 compatible = "ti,omap3-mcbsp";
506 reg = <0x49022000 0xff>,
508 reg-names = "mpu", "sidetone";
509 interrupts = <17>, /* OCP compliant interrupt */
510 <62>, /* TX interrupt */
511 <63>, /* RX interrupt */
513 interrupt-names = "common", "tx", "rx", "sidetone";
514 ti,buffer-size = <1280>;
515 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
518 dma-names = "tx", "rx";
519 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
520 clock-names = "fck", "ick";
524 mcbsp3: mcbsp@49024000 {
525 compatible = "ti,omap3-mcbsp";
526 reg = <0x49024000 0xff>,
528 reg-names = "mpu", "sidetone";
529 interrupts = <22>, /* OCP compliant interrupt */
530 <89>, /* TX interrupt */
531 <90>, /* RX interrupt */
533 interrupt-names = "common", "tx", "rx", "sidetone";
534 ti,buffer-size = <128>;
535 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
538 dma-names = "tx", "rx";
539 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
540 clock-names = "fck", "ick";
544 mcbsp4: mcbsp@49026000 {
545 compatible = "ti,omap3-mcbsp";
546 reg = <0x49026000 0xff>;
548 interrupts = <23>, /* OCP compliant interrupt */
549 <54>, /* TX interrupt */
550 <55>; /* RX interrupt */
551 interrupt-names = "common", "tx", "rx";
552 ti,buffer-size = <128>;
553 ti,hwmods = "mcbsp4";
556 dma-names = "tx", "rx";
557 clocks = <&mcbsp4_fck>;
562 mcbsp5: mcbsp@48096000 {
563 compatible = "ti,omap3-mcbsp";
564 reg = <0x48096000 0xff>;
566 interrupts = <27>, /* OCP compliant interrupt */
567 <81>, /* TX interrupt */
568 <82>; /* RX interrupt */
569 interrupt-names = "common", "tx", "rx";
570 ti,buffer-size = <128>;
571 ti,hwmods = "mcbsp5";
574 dma-names = "tx", "rx";
575 clocks = <&mcbsp5_fck>;
580 sham: sham@480c3000 {
581 compatible = "ti,omap3-sham";
583 reg = <0x480c3000 0x64>;
589 smartreflex_core: smartreflex@480cb000 {
590 compatible = "ti,omap3-smartreflex-core";
591 ti,hwmods = "smartreflex_core";
592 reg = <0x480cb000 0x400>;
596 smartreflex_mpu_iva: smartreflex@480c9000 {
597 compatible = "ti,omap3-smartreflex-iva";
598 ti,hwmods = "smartreflex_mpu_iva";
599 reg = <0x480c9000 0x400>;
603 timer1: timer@48318000 {
604 compatible = "ti,omap3430-timer";
605 reg = <0x48318000 0x400>;
607 ti,hwmods = "timer1";
611 timer2: timer@49032000 {
612 compatible = "ti,omap3430-timer";
613 reg = <0x49032000 0x400>;
615 ti,hwmods = "timer2";
618 timer3: timer@49034000 {
619 compatible = "ti,omap3430-timer";
620 reg = <0x49034000 0x400>;
622 ti,hwmods = "timer3";
625 timer4: timer@49036000 {
626 compatible = "ti,omap3430-timer";
627 reg = <0x49036000 0x400>;
629 ti,hwmods = "timer4";
632 timer5: timer@49038000 {
633 compatible = "ti,omap3430-timer";
634 reg = <0x49038000 0x400>;
636 ti,hwmods = "timer5";
640 timer6: timer@4903a000 {
641 compatible = "ti,omap3430-timer";
642 reg = <0x4903a000 0x400>;
644 ti,hwmods = "timer6";
648 timer7: timer@4903c000 {
649 compatible = "ti,omap3430-timer";
650 reg = <0x4903c000 0x400>;
652 ti,hwmods = "timer7";
656 timer8: timer@4903e000 {
657 compatible = "ti,omap3430-timer";
658 reg = <0x4903e000 0x400>;
660 ti,hwmods = "timer8";
665 timer9: timer@49040000 {
666 compatible = "ti,omap3430-timer";
667 reg = <0x49040000 0x400>;
669 ti,hwmods = "timer9";
673 timer10: timer@48086000 {
674 compatible = "ti,omap3430-timer";
675 reg = <0x48086000 0x400>;
677 ti,hwmods = "timer10";
681 timer11: timer@48088000 {
682 compatible = "ti,omap3430-timer";
683 reg = <0x48088000 0x400>;
685 ti,hwmods = "timer11";
689 timer12: timer@48304000 {
690 compatible = "ti,omap3430-timer";
691 reg = <0x48304000 0x400>;
693 ti,hwmods = "timer12";
698 usbhstll: usbhstll@48062000 {
699 compatible = "ti,usbhs-tll";
700 reg = <0x48062000 0x1000>;
702 ti,hwmods = "usb_tll_hs";
705 usbhshost: usbhshost@48064000 {
706 compatible = "ti,usbhs-host";
707 reg = <0x48064000 0x400>;
708 ti,hwmods = "usb_host_hs";
709 #address-cells = <1>;
713 usbhsohci: ohci@48064400 {
714 compatible = "ti,ohci-omap3";
715 reg = <0x48064400 0x400>;
719 usbhsehci: ehci@48064800 {
720 compatible = "ti,ehci-omap";
721 reg = <0x48064800 0x400>;
726 gpmc: gpmc@6e000000 {
727 compatible = "ti,omap3430-gpmc";
729 reg = <0x6e000000 0x02d0>;
734 gpmc,num-waitpins = <4>;
735 #address-cells = <2>;
737 interrupt-controller;
738 #interrupt-cells = <2>;
743 usb_otg_hs: usb_otg_hs@480ab000 {
744 compatible = "ti,omap3-musb";
745 reg = <0x480ab000 0x1000>;
746 interrupts = <92>, <93>;
747 interrupt-names = "mc", "dma";
748 ti,hwmods = "usb_otg_hs";
755 compatible = "ti,omap3-dss";
756 reg = <0x48050000 0x200>;
758 ti,hwmods = "dss_core";
759 clocks = <&dss1_alwon_fck>;
761 #address-cells = <1>;
766 compatible = "ti,omap3-dispc";
767 reg = <0x48050400 0x400>;
769 ti,hwmods = "dss_dispc";
770 clocks = <&dss1_alwon_fck>;
774 dsi: encoder@4804fc00 {
775 compatible = "ti,omap3-dsi";
776 reg = <0x4804fc00 0x200>,
779 reg-names = "proto", "phy", "pll";
782 ti,hwmods = "dss_dsi1";
783 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
784 clock-names = "fck", "sys_clk";
787 rfbi: encoder@48050800 {
788 compatible = "ti,omap3-rfbi";
789 reg = <0x48050800 0x100>;
791 ti,hwmods = "dss_rfbi";
792 clocks = <&dss1_alwon_fck>, <&dss_ick>;
793 clock-names = "fck", "ick";
796 venc: encoder@48050c00 {
797 compatible = "ti,omap3-venc";
798 reg = <0x48050c00 0x100>;
800 ti,hwmods = "dss_venc";
801 clocks = <&dss_tv_fck>;
806 ssi: ssi-controller@48058000 {
807 compatible = "ti,omap3-ssi";
812 reg = <0x48058000 0x1000>,
818 interrupt-names = "gdd_mpu";
820 #address-cells = <1>;
824 ssi_port1: ssi-port@4805a000 {
825 compatible = "ti,omap3-ssi-port";
827 reg = <0x4805a000 0x800>,
836 ssi_port2: ssi-port@4805b000 {
837 compatible = "ti,omap3-ssi-port";
839 reg = <0x4805b000 0x800>,
851 /include/ "omap3xxx-clocks.dtsi"