2 * Device Tree Source for OMAP3 SoC
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/omap.h>
17 compatible = "ti,omap3430", "ti,omap3";
18 interrupt-parent = <&intc>;
37 compatible = "arm,cortex-a8";
44 clock-latency = <300000>; /* From omap-cpufreq driver */
49 compatible = "arm,cortex-a8-pmu";
50 reg = <0x54000000 0x800000>;
52 ti,hwmods = "debugss";
56 * The soc node represents the soc top level view. It is used for IPs
57 * that are not memory mapped in the MPU view or for the MPU itself.
60 compatible = "ti,omap-infra";
62 compatible = "ti,omap3-mpu";
67 compatible = "ti,iva2.2";
71 compatible = "ti,omap3-c64";
77 * XXX: Use a flat representation of the OMAP3 interconnect.
78 * The real OMAP interconnect network is quite complex.
79 * Since it will not bring real advantage to represent that in DT for
80 * the moment, just use a fake OCP bus entry to represent the whole bus
84 compatible = "ti,omap3-l3-smx", "simple-bus";
85 reg = <0x68000000 0x10000>;
90 ti,hwmods = "l3_main";
92 l4_core: l4@48000000 {
93 compatible = "ti,omap3-l4-core", "simple-bus";
96 ranges = <0 0x48000000 0x1000000>;
99 compatible = "ti,omap3-scm", "simple-bus";
100 reg = <0x2000 0x2000>;
101 #address-cells = <1>;
103 ranges = <0 0x2000 0x2000>;
105 omap3_pmx_core: pinmux@30 {
106 compatible = "ti,omap3-padconf",
109 #address-cells = <1>;
111 #pinctrl-cells = <1>;
112 #interrupt-cells = <1>;
113 interrupt-controller;
114 pinctrl-single,register-width = <16>;
115 pinctrl-single,function-mask = <0xff1f>;
118 scm_conf: scm_conf@270 {
119 compatible = "syscon", "simple-bus";
121 #address-cells = <1>;
123 ranges = <0 0x270 0x330>;
125 pbias_regulator: pbias_regulator@2b0 {
126 compatible = "ti,pbias-omap3", "ti,pbias-omap";
128 syscon = <&scm_conf>;
129 pbias_mmc_reg: pbias_mmc_omap2430 {
130 regulator-name = "pbias_mmc_omap2430";
131 regulator-min-microvolt = <1800000>;
132 regulator-max-microvolt = <3000000>;
137 #address-cells = <1>;
142 scm_clockdomains: clockdomains {
145 omap3_pmx_wkup: pinmux@a00 {
146 compatible = "ti,omap3-padconf",
149 #address-cells = <1>;
151 #pinctrl-cells = <1>;
152 #interrupt-cells = <1>;
153 interrupt-controller;
154 pinctrl-single,register-width = <16>;
155 pinctrl-single,function-mask = <0xff1f>;
161 compatible = "ti,omap3-aes";
163 reg = <0x480c5000 0x50>;
165 dmas = <&sdma 65 &sdma 66>;
166 dma-names = "tx", "rx";
170 compatible = "ti,omap3-prm";
171 reg = <0x48306000 0x4000>;
175 #address-cells = <1>;
179 prm_clockdomains: clockdomains {
184 compatible = "ti,omap3-cm";
185 reg = <0x48004000 0x4000>;
188 #address-cells = <1>;
192 cm_clockdomains: clockdomains {
196 target-module@48320000 {
197 compatible = "ti,sysc-omap2", "ti,sysc";
198 reg = <0x48320000 0x4>,
200 reg-names = "rev", "sysc";
201 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
203 clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>;
204 clock-names = "fck", "ick";
205 #address-cells = <1>;
207 ranges = <0x0 0x48320000 0x1000>;
209 counter32k: counter@0 {
210 compatible = "ti,omap-counter32k";
215 intc: interrupt-controller@48200000 {
216 compatible = "ti,omap3-intc";
217 interrupt-controller;
218 #interrupt-cells = <1>;
219 reg = <0x48200000 0x1000>;
222 target-module@48056000 {
223 compatible = "ti,sysc-omap2", "ti,sysc";
224 reg = <0x48056000 0x4>,
227 reg-names = "rev", "sysc", "syss";
228 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
230 SYSC_OMAP2_SOFTRESET |
231 SYSC_OMAP2_AUTOIDLE)>;
232 ti,sysc-midle = <SYSC_IDLE_FORCE>,
235 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
239 /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */
240 clocks = <&core_l3_ick>;
242 #address-cells = <1>;
244 ranges = <0 0x48056000 0x1000>;
246 sdma: dma-controller@0 {
247 compatible = "ti,omap3430-sdma", "ti,omap-sdma";
259 gpio1: gpio@48310000 {
260 compatible = "ti,omap3-gpio";
261 reg = <0x48310000 0x200>;
267 interrupt-controller;
268 #interrupt-cells = <2>;
271 gpio2: gpio@49050000 {
272 compatible = "ti,omap3-gpio";
273 reg = <0x49050000 0x200>;
278 interrupt-controller;
279 #interrupt-cells = <2>;
282 gpio3: gpio@49052000 {
283 compatible = "ti,omap3-gpio";
284 reg = <0x49052000 0x200>;
289 interrupt-controller;
290 #interrupt-cells = <2>;
293 gpio4: gpio@49054000 {
294 compatible = "ti,omap3-gpio";
295 reg = <0x49054000 0x200>;
300 interrupt-controller;
301 #interrupt-cells = <2>;
304 gpio5: gpio@49056000 {
305 compatible = "ti,omap3-gpio";
306 reg = <0x49056000 0x200>;
311 interrupt-controller;
312 #interrupt-cells = <2>;
315 gpio6: gpio@49058000 {
316 compatible = "ti,omap3-gpio";
317 reg = <0x49058000 0x200>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
326 uart1: serial@4806a000 {
327 compatible = "ti,omap3-uart";
328 reg = <0x4806a000 0x2000>;
329 interrupts-extended = <&intc 72>;
330 dmas = <&sdma 49 &sdma 50>;
331 dma-names = "tx", "rx";
333 clock-frequency = <48000000>;
336 uart2: serial@4806c000 {
337 compatible = "ti,omap3-uart";
338 reg = <0x4806c000 0x400>;
339 interrupts-extended = <&intc 73>;
340 dmas = <&sdma 51 &sdma 52>;
341 dma-names = "tx", "rx";
343 clock-frequency = <48000000>;
346 uart3: serial@49020000 {
347 compatible = "ti,omap3-uart";
348 reg = <0x49020000 0x400>;
349 interrupts-extended = <&intc 74>;
350 dmas = <&sdma 53 &sdma 54>;
351 dma-names = "tx", "rx";
353 clock-frequency = <48000000>;
357 compatible = "ti,omap3-i2c";
358 reg = <0x48070000 0x80>;
360 dmas = <&sdma 27 &sdma 28>;
361 dma-names = "tx", "rx";
362 #address-cells = <1>;
368 compatible = "ti,omap3-i2c";
369 reg = <0x48072000 0x80>;
371 dmas = <&sdma 29 &sdma 30>;
372 dma-names = "tx", "rx";
373 #address-cells = <1>;
379 compatible = "ti,omap3-i2c";
380 reg = <0x48060000 0x80>;
382 dmas = <&sdma 25 &sdma 26>;
383 dma-names = "tx", "rx";
384 #address-cells = <1>;
389 mailbox: mailbox@48094000 {
390 compatible = "ti,omap3-mailbox";
391 ti,hwmods = "mailbox";
392 reg = <0x48094000 0x200>;
395 ti,mbox-num-users = <2>;
396 ti,mbox-num-fifos = <2>;
398 ti,mbox-tx = <0 0 0>;
399 ti,mbox-rx = <1 0 0>;
403 mcspi1: spi@48098000 {
404 compatible = "ti,omap2-mcspi";
405 reg = <0x48098000 0x100>;
407 #address-cells = <1>;
409 ti,hwmods = "mcspi1";
419 dma-names = "tx0", "rx0", "tx1", "rx1",
420 "tx2", "rx2", "tx3", "rx3";
423 mcspi2: spi@4809a000 {
424 compatible = "ti,omap2-mcspi";
425 reg = <0x4809a000 0x100>;
427 #address-cells = <1>;
429 ti,hwmods = "mcspi2";
435 dma-names = "tx0", "rx0", "tx1", "rx1";
438 mcspi3: spi@480b8000 {
439 compatible = "ti,omap2-mcspi";
440 reg = <0x480b8000 0x100>;
442 #address-cells = <1>;
444 ti,hwmods = "mcspi3";
450 dma-names = "tx0", "rx0", "tx1", "rx1";
453 mcspi4: spi@480ba000 {
454 compatible = "ti,omap2-mcspi";
455 reg = <0x480ba000 0x100>;
457 #address-cells = <1>;
459 ti,hwmods = "mcspi4";
461 dmas = <&sdma 70>, <&sdma 71>;
462 dma-names = "tx0", "rx0";
465 hdqw1w: 1w@480b2000 {
466 compatible = "ti,omap3-1w";
467 reg = <0x480b2000 0x1000>;
473 compatible = "ti,omap3-hsmmc";
474 reg = <0x4809c000 0x200>;
478 dmas = <&sdma 61>, <&sdma 62>;
479 dma-names = "tx", "rx";
480 pbias-supply = <&pbias_mmc_reg>;
484 compatible = "ti,omap3-hsmmc";
485 reg = <0x480b4000 0x200>;
488 dmas = <&sdma 47>, <&sdma 48>;
489 dma-names = "tx", "rx";
493 compatible = "ti,omap3-hsmmc";
494 reg = <0x480ad000 0x200>;
497 dmas = <&sdma 77>, <&sdma 78>;
498 dma-names = "tx", "rx";
501 mmu_isp: mmu@480bd400 {
503 compatible = "ti,omap2-iommu";
504 reg = <0x480bd400 0x80>;
506 ti,hwmods = "mmu_isp";
507 ti,#tlb-entries = <8>;
510 mmu_iva: mmu@5d000000 {
512 compatible = "ti,omap2-iommu";
513 reg = <0x5d000000 0x80>;
515 ti,hwmods = "mmu_iva";
520 compatible = "ti,omap3-wdt";
521 reg = <0x48314000 0x80>;
522 ti,hwmods = "wd_timer2";
525 mcbsp1: mcbsp@48074000 {
526 compatible = "ti,omap3-mcbsp";
527 reg = <0x48074000 0xff>;
529 interrupts = <16>, /* OCP compliant interrupt */
530 <59>, /* TX interrupt */
531 <60>; /* RX interrupt */
532 interrupt-names = "common", "tx", "rx";
533 ti,buffer-size = <128>;
534 ti,hwmods = "mcbsp1";
537 dma-names = "tx", "rx";
538 clocks = <&mcbsp1_fck>;
543 /* Likely needs to be tagged disabled on HS devices */
544 rng_target: target-module@480a0000 {
545 compatible = "ti,sysc-omap2", "ti,sysc";
546 reg = <0x480a003c 0x4>,
549 reg-names = "rev", "sysc", "syss";
550 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
551 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
556 #address-cells = <1>;
558 ranges = <0 0x480a0000 0x2000>;
561 compatible = "ti,omap2-rng";
567 mcbsp2: mcbsp@49022000 {
568 compatible = "ti,omap3-mcbsp";
569 reg = <0x49022000 0xff>,
571 reg-names = "mpu", "sidetone";
572 interrupts = <17>, /* OCP compliant interrupt */
573 <62>, /* TX interrupt */
574 <63>, /* RX interrupt */
576 interrupt-names = "common", "tx", "rx", "sidetone";
577 ti,buffer-size = <1280>;
578 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
581 dma-names = "tx", "rx";
582 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
583 clock-names = "fck", "ick";
587 mcbsp3: mcbsp@49024000 {
588 compatible = "ti,omap3-mcbsp";
589 reg = <0x49024000 0xff>,
591 reg-names = "mpu", "sidetone";
592 interrupts = <22>, /* OCP compliant interrupt */
593 <89>, /* TX interrupt */
594 <90>, /* RX interrupt */
596 interrupt-names = "common", "tx", "rx", "sidetone";
597 ti,buffer-size = <128>;
598 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
601 dma-names = "tx", "rx";
602 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
603 clock-names = "fck", "ick";
607 mcbsp4: mcbsp@49026000 {
608 compatible = "ti,omap3-mcbsp";
609 reg = <0x49026000 0xff>;
611 interrupts = <23>, /* OCP compliant interrupt */
612 <54>, /* TX interrupt */
613 <55>; /* RX interrupt */
614 interrupt-names = "common", "tx", "rx";
615 ti,buffer-size = <128>;
616 ti,hwmods = "mcbsp4";
619 dma-names = "tx", "rx";
620 clocks = <&mcbsp4_fck>;
622 #sound-dai-cells = <0>;
626 mcbsp5: mcbsp@48096000 {
627 compatible = "ti,omap3-mcbsp";
628 reg = <0x48096000 0xff>;
630 interrupts = <27>, /* OCP compliant interrupt */
631 <81>, /* TX interrupt */
632 <82>; /* RX interrupt */
633 interrupt-names = "common", "tx", "rx";
634 ti,buffer-size = <128>;
635 ti,hwmods = "mcbsp5";
638 dma-names = "tx", "rx";
639 clocks = <&mcbsp5_fck>;
644 sham: sham@480c3000 {
645 compatible = "ti,omap3-sham";
647 reg = <0x480c3000 0x64>;
653 timer1_target: target-module@48318000 {
654 compatible = "ti,sysc-omap2-timer", "ti,sysc";
655 reg = <0x48318000 0x4>,
658 reg-names = "rev", "sysc", "syss";
659 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
661 SYSC_OMAP2_ENAWAKEUP |
662 SYSC_OMAP2_SOFTRESET |
663 SYSC_OMAP2_AUTOIDLE)>;
664 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
668 clocks = <&gpt1_fck>, <&gpt1_ick>;
669 clock-names = "fck", "ick";
670 #address-cells = <1>;
672 ranges = <0x0 0x48318000 0x1000>;
675 compatible = "ti,omap3430-timer";
677 clocks = <&gpt1_fck>;
684 timer2_target: target-module@49032000 {
685 compatible = "ti,sysc-omap2-timer", "ti,sysc";
686 reg = <0x49032000 0x4>,
689 reg-names = "rev", "sysc", "syss";
690 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
692 SYSC_OMAP2_ENAWAKEUP |
693 SYSC_OMAP2_SOFTRESET |
694 SYSC_OMAP2_AUTOIDLE)>;
695 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
699 clocks = <&gpt2_fck>, <&gpt2_ick>;
700 clock-names = "fck", "ick";
701 #address-cells = <1>;
703 ranges = <0x0 0x49032000 0x1000>;
706 compatible = "ti,omap3430-timer";
712 timer3: timer@49034000 {
713 compatible = "ti,omap3430-timer";
714 reg = <0x49034000 0x400>;
716 ti,hwmods = "timer3";
719 timer4: timer@49036000 {
720 compatible = "ti,omap3430-timer";
721 reg = <0x49036000 0x400>;
723 ti,hwmods = "timer4";
726 timer5: timer@49038000 {
727 compatible = "ti,omap3430-timer";
728 reg = <0x49038000 0x400>;
730 ti,hwmods = "timer5";
734 timer6: timer@4903a000 {
735 compatible = "ti,omap3430-timer";
736 reg = <0x4903a000 0x400>;
738 ti,hwmods = "timer6";
742 timer7: timer@4903c000 {
743 compatible = "ti,omap3430-timer";
744 reg = <0x4903c000 0x400>;
746 ti,hwmods = "timer7";
750 timer8: timer@4903e000 {
751 compatible = "ti,omap3430-timer";
752 reg = <0x4903e000 0x400>;
754 ti,hwmods = "timer8";
759 timer9: timer@49040000 {
760 compatible = "ti,omap3430-timer";
761 reg = <0x49040000 0x400>;
763 ti,hwmods = "timer9";
767 timer10: timer@48086000 {
768 compatible = "ti,omap3430-timer";
769 reg = <0x48086000 0x400>;
771 ti,hwmods = "timer10";
775 timer11: timer@48088000 {
776 compatible = "ti,omap3430-timer";
777 reg = <0x48088000 0x400>;
779 ti,hwmods = "timer11";
783 timer12_target: target-module@48304000 {
784 compatible = "ti,sysc-omap2-timer", "ti,sysc";
785 reg = <0x48304000 0x4>,
788 reg-names = "rev", "sysc", "syss";
789 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
791 SYSC_OMAP2_ENAWAKEUP |
792 SYSC_OMAP2_SOFTRESET |
793 SYSC_OMAP2_AUTOIDLE)>;
794 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
798 clocks = <&gpt12_fck>, <&gpt12_ick>;
799 clock-names = "fck", "ick";
800 #address-cells = <1>;
802 ranges = <0x0 0x48304000 0x1000>;
805 compatible = "ti,omap3430-timer";
813 usbhstll: usbhstll@48062000 {
814 compatible = "ti,usbhs-tll";
815 reg = <0x48062000 0x1000>;
817 ti,hwmods = "usb_tll_hs";
820 usbhshost: usbhshost@48064000 {
821 compatible = "ti,usbhs-host";
822 reg = <0x48064000 0x400>;
823 ti,hwmods = "usb_host_hs";
824 #address-cells = <1>;
828 usbhsohci: ohci@48064400 {
829 compatible = "ti,ohci-omap3";
830 reg = <0x48064400 0x400>;
832 remote-wakeup-connected;
835 usbhsehci: ehci@48064800 {
836 compatible = "ti,ehci-omap";
837 reg = <0x48064800 0x400>;
842 gpmc: gpmc@6e000000 {
843 compatible = "ti,omap3430-gpmc";
845 reg = <0x6e000000 0x02d0>;
850 gpmc,num-waitpins = <4>;
851 #address-cells = <2>;
853 interrupt-controller;
854 #interrupt-cells = <2>;
859 usb_otg_hs: usb_otg_hs@480ab000 {
860 compatible = "ti,omap3-musb";
861 reg = <0x480ab000 0x1000>;
862 interrupts = <92>, <93>;
863 interrupt-names = "mc", "dma";
864 ti,hwmods = "usb_otg_hs";
871 compatible = "ti,omap3-dss";
872 reg = <0x48050000 0x200>;
874 ti,hwmods = "dss_core";
875 clocks = <&dss1_alwon_fck>;
877 #address-cells = <1>;
882 compatible = "ti,omap3-dispc";
883 reg = <0x48050400 0x400>;
885 ti,hwmods = "dss_dispc";
886 clocks = <&dss1_alwon_fck>;
890 dsi: encoder@4804fc00 {
891 compatible = "ti,omap3-dsi";
892 reg = <0x4804fc00 0x200>,
895 reg-names = "proto", "phy", "pll";
898 ti,hwmods = "dss_dsi1";
899 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
900 clock-names = "fck", "sys_clk";
903 rfbi: encoder@48050800 {
904 compatible = "ti,omap3-rfbi";
905 reg = <0x48050800 0x100>;
907 ti,hwmods = "dss_rfbi";
908 clocks = <&dss1_alwon_fck>, <&dss_ick>;
909 clock-names = "fck", "ick";
912 venc: encoder@48050c00 {
913 compatible = "ti,omap3-venc";
914 reg = <0x48050c00 0x100>;
916 ti,hwmods = "dss_venc";
917 clocks = <&dss_tv_fck>;
922 ssi: ssi-controller@48058000 {
923 compatible = "ti,omap3-ssi";
928 reg = <0x48058000 0x1000>,
934 interrupt-names = "gdd_mpu";
936 #address-cells = <1>;
940 ssi_port1: ssi-port@4805a000 {
941 compatible = "ti,omap3-ssi-port";
943 reg = <0x4805a000 0x800>,
952 ssi_port2: ssi-port@4805b000 {
953 compatible = "ti,omap3-ssi-port";
955 reg = <0x4805b000 0x800>,
967 #include "omap3xxx-clocks.dtsi"
969 /* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */
974 assigned-clocks = <&gpt1_fck>;
975 assigned-clock-parents = <&omap_32k_fck>;