2 * Device Tree Source for OMAP3 SoC
4 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/omap.h>
17 compatible = "ti,omap3430", "ti,omap3";
18 interrupt-parent = <&intc>;
40 compatible = "arm,cortex-a8";
47 clock-latency = <300000>; /* From omap-cpufreq driver */
52 compatible = "arm,cortex-a8-pmu";
53 reg = <0x54000000 0x800000>;
55 ti,hwmods = "debugss";
59 * The soc node represents the soc top level view. It is used for IPs
60 * that are not memory mapped in the MPU view or for the MPU itself.
63 compatible = "ti,omap-infra";
65 compatible = "ti,omap3-mpu";
70 compatible = "ti,iva2.2";
74 compatible = "ti,omap3-c64";
80 * XXX: Use a flat representation of the OMAP3 interconnect.
81 * The real OMAP interconnect network is quite complex.
82 * Since it will not bring real advantage to represent that in DT for
83 * the moment, just use a fake OCP bus entry to represent the whole bus
87 compatible = "ti,omap3-l3-smx", "simple-bus";
88 reg = <0x68000000 0x10000>;
93 ti,hwmods = "l3_main";
95 l4_core: l4@48000000 {
96 compatible = "ti,omap3-l4-core", "simple-bus";
99 ranges = <0 0x48000000 0x1000000>;
102 compatible = "ti,omap3-scm", "simple-bus";
103 reg = <0x2000 0x2000>;
104 #address-cells = <1>;
106 ranges = <0 0x2000 0x2000>;
108 omap3_pmx_core: pinmux@30 {
109 compatible = "ti,omap3-padconf",
112 #address-cells = <1>;
114 #pinctrl-cells = <1>;
115 #interrupt-cells = <1>;
116 interrupt-controller;
117 pinctrl-single,register-width = <16>;
118 pinctrl-single,function-mask = <0xff1f>;
121 scm_conf: scm_conf@270 {
122 compatible = "syscon", "simple-bus";
124 #address-cells = <1>;
126 ranges = <0 0x270 0x330>;
128 pbias_regulator: pbias_regulator@2b0 {
129 compatible = "ti,pbias-omap3", "ti,pbias-omap";
131 syscon = <&scm_conf>;
132 pbias_mmc_reg: pbias_mmc_omap2430 {
133 regulator-name = "pbias_mmc_omap2430";
134 regulator-min-microvolt = <1800000>;
135 regulator-max-microvolt = <3000000>;
140 #address-cells = <1>;
145 scm_clockdomains: clockdomains {
148 omap3_pmx_wkup: pinmux@a00 {
149 compatible = "ti,omap3-padconf",
152 #address-cells = <1>;
154 #pinctrl-cells = <1>;
155 #interrupt-cells = <1>;
156 interrupt-controller;
157 pinctrl-single,register-width = <16>;
158 pinctrl-single,function-mask = <0xff1f>;
163 aes1_target: target-module@480a6000 {
164 compatible = "ti,sysc-omap2", "ti,sysc";
165 reg = <0x480a6044 0x4>,
168 reg-names = "rev", "sysc", "syss";
169 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
170 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
174 clocks = <&aes1_ick>;
176 #address-cells = <1>;
178 ranges = <0 0x480a6000 0x2000>;
181 compatible = "ti,omap3-aes";
184 dmas = <&sdma 9 &sdma 10>;
185 dma-names = "tx", "rx";
189 aes2_target: target-module@480c5000 {
190 compatible = "ti,sysc-omap2", "ti,sysc";
191 reg = <0x480c5044 0x4>,
194 reg-names = "rev", "sysc", "syss";
195 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
196 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
200 clocks = <&aes2_ick>;
202 #address-cells = <1>;
204 ranges = <0 0x480c5000 0x2000>;
207 compatible = "ti,omap3-aes";
210 dmas = <&sdma 65 &sdma 66>;
211 dma-names = "tx", "rx";
216 compatible = "ti,omap3-prm";
217 reg = <0x48306000 0x4000>;
221 #address-cells = <1>;
225 prm_clockdomains: clockdomains {
230 compatible = "ti,omap3-cm";
231 reg = <0x48004000 0x4000>;
234 #address-cells = <1>;
238 cm_clockdomains: clockdomains {
242 target-module@48320000 {
243 compatible = "ti,sysc-omap2", "ti,sysc";
244 reg = <0x48320000 0x4>,
246 reg-names = "rev", "sysc";
247 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
249 clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>;
250 clock-names = "fck", "ick";
251 #address-cells = <1>;
253 ranges = <0x0 0x48320000 0x1000>;
255 counter32k: counter@0 {
256 compatible = "ti,omap-counter32k";
261 intc: interrupt-controller@48200000 {
262 compatible = "ti,omap3-intc";
263 interrupt-controller;
264 #interrupt-cells = <1>;
265 reg = <0x48200000 0x1000>;
268 target-module@48056000 {
269 compatible = "ti,sysc-omap2", "ti,sysc";
270 reg = <0x48056000 0x4>,
273 reg-names = "rev", "sysc", "syss";
274 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
276 SYSC_OMAP2_SOFTRESET |
277 SYSC_OMAP2_AUTOIDLE)>;
278 ti,sysc-midle = <SYSC_IDLE_FORCE>,
281 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
285 /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */
286 clocks = <&core_l3_ick>;
288 #address-cells = <1>;
290 ranges = <0 0x48056000 0x1000>;
292 sdma: dma-controller@0 {
293 compatible = "ti,omap3430-sdma", "ti,omap-sdma";
305 gpio1: gpio@48310000 {
306 compatible = "ti,omap3-gpio";
307 reg = <0x48310000 0x200>;
313 interrupt-controller;
314 #interrupt-cells = <2>;
317 gpio2: gpio@49050000 {
318 compatible = "ti,omap3-gpio";
319 reg = <0x49050000 0x200>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
328 gpio3: gpio@49052000 {
329 compatible = "ti,omap3-gpio";
330 reg = <0x49052000 0x200>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
339 gpio4: gpio@49054000 {
340 compatible = "ti,omap3-gpio";
341 reg = <0x49054000 0x200>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
350 gpio5: gpio@49056000 {
351 compatible = "ti,omap3-gpio";
352 reg = <0x49056000 0x200>;
357 interrupt-controller;
358 #interrupt-cells = <2>;
361 gpio6: gpio@49058000 {
362 compatible = "ti,omap3-gpio";
363 reg = <0x49058000 0x200>;
368 interrupt-controller;
369 #interrupt-cells = <2>;
372 uart1: serial@4806a000 {
373 compatible = "ti,omap3-uart";
374 reg = <0x4806a000 0x2000>;
375 interrupts-extended = <&intc 72>;
376 dmas = <&sdma 49 &sdma 50>;
377 dma-names = "tx", "rx";
379 clock-frequency = <48000000>;
382 uart2: serial@4806c000 {
383 compatible = "ti,omap3-uart";
384 reg = <0x4806c000 0x400>;
385 interrupts-extended = <&intc 73>;
386 dmas = <&sdma 51 &sdma 52>;
387 dma-names = "tx", "rx";
389 clock-frequency = <48000000>;
392 uart3: serial@49020000 {
393 compatible = "ti,omap3-uart";
394 reg = <0x49020000 0x400>;
395 interrupts-extended = <&intc 74>;
396 dmas = <&sdma 53 &sdma 54>;
397 dma-names = "tx", "rx";
399 clock-frequency = <48000000>;
403 compatible = "ti,omap3-i2c";
404 reg = <0x48070000 0x80>;
406 #address-cells = <1>;
412 compatible = "ti,omap3-i2c";
413 reg = <0x48072000 0x80>;
415 #address-cells = <1>;
421 compatible = "ti,omap3-i2c";
422 reg = <0x48060000 0x80>;
424 #address-cells = <1>;
429 mailbox: mailbox@48094000 {
430 compatible = "ti,omap3-mailbox";
431 ti,hwmods = "mailbox";
432 reg = <0x48094000 0x200>;
435 ti,mbox-num-users = <2>;
436 ti,mbox-num-fifos = <2>;
438 ti,mbox-tx = <0 0 0>;
439 ti,mbox-rx = <1 0 0>;
443 mcspi1: spi@48098000 {
444 compatible = "ti,omap2-mcspi";
445 reg = <0x48098000 0x100>;
447 #address-cells = <1>;
449 ti,hwmods = "mcspi1";
459 dma-names = "tx0", "rx0", "tx1", "rx1",
460 "tx2", "rx2", "tx3", "rx3";
463 mcspi2: spi@4809a000 {
464 compatible = "ti,omap2-mcspi";
465 reg = <0x4809a000 0x100>;
467 #address-cells = <1>;
469 ti,hwmods = "mcspi2";
475 dma-names = "tx0", "rx0", "tx1", "rx1";
478 mcspi3: spi@480b8000 {
479 compatible = "ti,omap2-mcspi";
480 reg = <0x480b8000 0x100>;
482 #address-cells = <1>;
484 ti,hwmods = "mcspi3";
490 dma-names = "tx0", "rx0", "tx1", "rx1";
493 mcspi4: spi@480ba000 {
494 compatible = "ti,omap2-mcspi";
495 reg = <0x480ba000 0x100>;
497 #address-cells = <1>;
499 ti,hwmods = "mcspi4";
501 dmas = <&sdma 70>, <&sdma 71>;
502 dma-names = "tx0", "rx0";
505 hdqw1w: 1w@480b2000 {
506 compatible = "ti,omap3-1w";
507 reg = <0x480b2000 0x1000>;
513 compatible = "ti,omap3-hsmmc";
514 reg = <0x4809c000 0x200>;
518 dmas = <&sdma 61>, <&sdma 62>;
519 dma-names = "tx", "rx";
520 pbias-supply = <&pbias_mmc_reg>;
524 compatible = "ti,omap3-hsmmc";
525 reg = <0x480b4000 0x200>;
528 dmas = <&sdma 47>, <&sdma 48>;
529 dma-names = "tx", "rx";
533 compatible = "ti,omap3-hsmmc";
534 reg = <0x480ad000 0x200>;
537 dmas = <&sdma 77>, <&sdma 78>;
538 dma-names = "tx", "rx";
541 mmu_isp: mmu@480bd400 {
543 compatible = "ti,omap2-iommu";
544 reg = <0x480bd400 0x80>;
546 ti,hwmods = "mmu_isp";
547 ti,#tlb-entries = <8>;
550 mmu_iva: mmu@5d000000 {
552 compatible = "ti,omap2-iommu";
553 reg = <0x5d000000 0x80>;
555 ti,hwmods = "mmu_iva";
560 compatible = "ti,omap3-wdt";
561 reg = <0x48314000 0x80>;
562 ti,hwmods = "wd_timer2";
565 mcbsp1: mcbsp@48074000 {
566 compatible = "ti,omap3-mcbsp";
567 reg = <0x48074000 0xff>;
569 interrupts = <16>, /* OCP compliant interrupt */
570 <59>, /* TX interrupt */
571 <60>; /* RX interrupt */
572 interrupt-names = "common", "tx", "rx";
573 ti,buffer-size = <128>;
574 ti,hwmods = "mcbsp1";
577 dma-names = "tx", "rx";
578 clocks = <&mcbsp1_fck>;
583 /* Likely needs to be tagged disabled on HS devices */
584 rng_target: target-module@480a0000 {
585 compatible = "ti,sysc-omap2", "ti,sysc";
586 reg = <0x480a003c 0x4>,
589 reg-names = "rev", "sysc", "syss";
590 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
591 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
596 #address-cells = <1>;
598 ranges = <0 0x480a0000 0x2000>;
601 compatible = "ti,omap2-rng";
607 mcbsp2: mcbsp@49022000 {
608 compatible = "ti,omap3-mcbsp";
609 reg = <0x49022000 0xff>,
611 reg-names = "mpu", "sidetone";
612 interrupts = <17>, /* OCP compliant interrupt */
613 <62>, /* TX interrupt */
614 <63>, /* RX interrupt */
616 interrupt-names = "common", "tx", "rx", "sidetone";
617 ti,buffer-size = <1280>;
618 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
621 dma-names = "tx", "rx";
622 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
623 clock-names = "fck", "ick";
627 mcbsp3: mcbsp@49024000 {
628 compatible = "ti,omap3-mcbsp";
629 reg = <0x49024000 0xff>,
631 reg-names = "mpu", "sidetone";
632 interrupts = <22>, /* OCP compliant interrupt */
633 <89>, /* TX interrupt */
634 <90>, /* RX interrupt */
636 interrupt-names = "common", "tx", "rx", "sidetone";
637 ti,buffer-size = <128>;
638 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
641 dma-names = "tx", "rx";
642 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
643 clock-names = "fck", "ick";
647 mcbsp4: mcbsp@49026000 {
648 compatible = "ti,omap3-mcbsp";
649 reg = <0x49026000 0xff>;
651 interrupts = <23>, /* OCP compliant interrupt */
652 <54>, /* TX interrupt */
653 <55>; /* RX interrupt */
654 interrupt-names = "common", "tx", "rx";
655 ti,buffer-size = <128>;
656 ti,hwmods = "mcbsp4";
659 dma-names = "tx", "rx";
660 clocks = <&mcbsp4_fck>;
662 #sound-dai-cells = <0>;
666 mcbsp5: mcbsp@48096000 {
667 compatible = "ti,omap3-mcbsp";
668 reg = <0x48096000 0xff>;
670 interrupts = <27>, /* OCP compliant interrupt */
671 <81>, /* TX interrupt */
672 <82>; /* RX interrupt */
673 interrupt-names = "common", "tx", "rx";
674 ti,buffer-size = <128>;
675 ti,hwmods = "mcbsp5";
678 dma-names = "tx", "rx";
679 clocks = <&mcbsp5_fck>;
684 sham: sham@480c3000 {
685 compatible = "ti,omap3-sham";
687 reg = <0x480c3000 0x64>;
693 timer1_target: target-module@48318000 {
694 compatible = "ti,sysc-omap2-timer", "ti,sysc";
695 reg = <0x48318000 0x4>,
698 reg-names = "rev", "sysc", "syss";
699 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
701 SYSC_OMAP2_ENAWAKEUP |
702 SYSC_OMAP2_SOFTRESET |
703 SYSC_OMAP2_AUTOIDLE)>;
704 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
708 clocks = <&gpt1_fck>, <&gpt1_ick>;
709 clock-names = "fck", "ick";
710 #address-cells = <1>;
712 ranges = <0x0 0x48318000 0x1000>;
715 compatible = "ti,omap3430-timer";
717 clocks = <&gpt1_fck>;
724 timer2_target: target-module@49032000 {
725 compatible = "ti,sysc-omap2-timer", "ti,sysc";
726 reg = <0x49032000 0x4>,
729 reg-names = "rev", "sysc", "syss";
730 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
732 SYSC_OMAP2_ENAWAKEUP |
733 SYSC_OMAP2_SOFTRESET |
734 SYSC_OMAP2_AUTOIDLE)>;
735 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
739 clocks = <&gpt2_fck>, <&gpt2_ick>;
740 clock-names = "fck", "ick";
741 #address-cells = <1>;
743 ranges = <0x0 0x49032000 0x1000>;
746 compatible = "ti,omap3430-timer";
752 timer3: timer@49034000 {
753 compatible = "ti,omap3430-timer";
754 reg = <0x49034000 0x400>;
756 ti,hwmods = "timer3";
759 timer4: timer@49036000 {
760 compatible = "ti,omap3430-timer";
761 reg = <0x49036000 0x400>;
763 ti,hwmods = "timer4";
766 timer5: timer@49038000 {
767 compatible = "ti,omap3430-timer";
768 reg = <0x49038000 0x400>;
770 ti,hwmods = "timer5";
774 timer6: timer@4903a000 {
775 compatible = "ti,omap3430-timer";
776 reg = <0x4903a000 0x400>;
778 ti,hwmods = "timer6";
782 timer7: timer@4903c000 {
783 compatible = "ti,omap3430-timer";
784 reg = <0x4903c000 0x400>;
786 ti,hwmods = "timer7";
790 timer8: timer@4903e000 {
791 compatible = "ti,omap3430-timer";
792 reg = <0x4903e000 0x400>;
794 ti,hwmods = "timer8";
799 timer9: timer@49040000 {
800 compatible = "ti,omap3430-timer";
801 reg = <0x49040000 0x400>;
803 ti,hwmods = "timer9";
807 timer10: timer@48086000 {
808 compatible = "ti,omap3430-timer";
809 reg = <0x48086000 0x400>;
811 ti,hwmods = "timer10";
815 timer11: timer@48088000 {
816 compatible = "ti,omap3430-timer";
817 reg = <0x48088000 0x400>;
819 ti,hwmods = "timer11";
823 timer12_target: target-module@48304000 {
824 compatible = "ti,sysc-omap2-timer", "ti,sysc";
825 reg = <0x48304000 0x4>,
828 reg-names = "rev", "sysc", "syss";
829 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
831 SYSC_OMAP2_ENAWAKEUP |
832 SYSC_OMAP2_SOFTRESET |
833 SYSC_OMAP2_AUTOIDLE)>;
834 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
838 clocks = <&gpt12_fck>, <&gpt12_ick>;
839 clock-names = "fck", "ick";
840 #address-cells = <1>;
842 ranges = <0x0 0x48304000 0x1000>;
845 compatible = "ti,omap3430-timer";
853 usbhstll: usbhstll@48062000 {
854 compatible = "ti,usbhs-tll";
855 reg = <0x48062000 0x1000>;
857 ti,hwmods = "usb_tll_hs";
860 usbhshost: usbhshost@48064000 {
861 compatible = "ti,usbhs-host";
862 reg = <0x48064000 0x400>;
863 ti,hwmods = "usb_host_hs";
864 #address-cells = <1>;
868 usbhsohci: ohci@48064400 {
869 compatible = "ti,ohci-omap3";
870 reg = <0x48064400 0x400>;
872 remote-wakeup-connected;
875 usbhsehci: ehci@48064800 {
876 compatible = "ti,ehci-omap";
877 reg = <0x48064800 0x400>;
882 gpmc: gpmc@6e000000 {
883 compatible = "ti,omap3430-gpmc";
885 reg = <0x6e000000 0x02d0>;
890 gpmc,num-waitpins = <4>;
891 #address-cells = <2>;
893 interrupt-controller;
894 #interrupt-cells = <2>;
899 usb_otg_hs: usb_otg_hs@480ab000 {
900 compatible = "ti,omap3-musb";
901 reg = <0x480ab000 0x1000>;
902 interrupts = <92>, <93>;
903 interrupt-names = "mc", "dma";
904 ti,hwmods = "usb_otg_hs";
911 compatible = "ti,omap3-dss";
912 reg = <0x48050000 0x200>;
914 ti,hwmods = "dss_core";
915 clocks = <&dss1_alwon_fck>;
917 #address-cells = <1>;
922 compatible = "ti,omap3-dispc";
923 reg = <0x48050400 0x400>;
925 ti,hwmods = "dss_dispc";
926 clocks = <&dss1_alwon_fck>;
930 dsi: encoder@4804fc00 {
931 compatible = "ti,omap3-dsi";
932 reg = <0x4804fc00 0x200>,
935 reg-names = "proto", "phy", "pll";
938 ti,hwmods = "dss_dsi1";
939 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
940 clock-names = "fck", "sys_clk";
942 #address-cells = <1>;
946 rfbi: encoder@48050800 {
947 compatible = "ti,omap3-rfbi";
948 reg = <0x48050800 0x100>;
950 ti,hwmods = "dss_rfbi";
951 clocks = <&dss1_alwon_fck>, <&dss_ick>;
952 clock-names = "fck", "ick";
955 venc: encoder@48050c00 {
956 compatible = "ti,omap3-venc";
957 reg = <0x48050c00 0x100>;
959 ti,hwmods = "dss_venc";
960 clocks = <&dss_tv_fck>;
965 ssi: ssi-controller@48058000 {
966 compatible = "ti,omap3-ssi";
971 reg = <0x48058000 0x1000>,
977 interrupt-names = "gdd_mpu";
979 #address-cells = <1>;
983 ssi_port1: ssi-port@4805a000 {
984 compatible = "ti,omap3-ssi-port";
986 reg = <0x4805a000 0x800>,
995 ssi_port2: ssi-port@4805b000 {
996 compatible = "ti,omap3-ssi-port";
998 reg = <0x4805b000 0x800>,
1010 #include "omap3xxx-clocks.dtsi"
1012 /* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */
1014 ti,no-reset-on-init;
1017 assigned-clocks = <&gpt1_fck>;
1018 assigned-clock-parents = <&omap_32k_fck>;