2 * Device Tree Source for OMAP3 SoC
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/omap.h>
17 compatible = "ti,omap3430", "ti,omap3";
18 interrupt-parent = <&intc>;
37 compatible = "arm,cortex-a8";
44 clock-latency = <300000>; /* From omap-cpufreq driver */
49 compatible = "arm,cortex-a8-pmu";
50 reg = <0x54000000 0x800000>;
52 ti,hwmods = "debugss";
56 * The soc node represents the soc top level view. It is used for IPs
57 * that are not memory mapped in the MPU view or for the MPU itself.
60 compatible = "ti,omap-infra";
62 compatible = "ti,omap3-mpu";
67 compatible = "ti,iva2.2";
71 compatible = "ti,omap3-c64";
77 * XXX: Use a flat representation of the OMAP3 interconnect.
78 * The real OMAP interconnect network is quite complex.
79 * Since it will not bring real advantage to represent that in DT for
80 * the moment, just use a fake OCP bus entry to represent the whole bus
84 compatible = "ti,omap3-l3-smx", "simple-bus";
85 reg = <0x68000000 0x10000>;
90 ti,hwmods = "l3_main";
92 l4_core: l4@48000000 {
93 compatible = "ti,omap3-l4-core", "simple-bus";
96 ranges = <0 0x48000000 0x1000000>;
99 compatible = "ti,omap3-scm", "simple-bus";
100 reg = <0x2000 0x2000>;
101 #address-cells = <1>;
103 ranges = <0 0x2000 0x2000>;
105 omap3_pmx_core: pinmux@30 {
106 compatible = "ti,omap3-padconf",
109 #address-cells = <1>;
111 #pinctrl-cells = <1>;
112 #interrupt-cells = <1>;
113 interrupt-controller;
114 pinctrl-single,register-width = <16>;
115 pinctrl-single,function-mask = <0xff1f>;
118 scm_conf: scm_conf@270 {
119 compatible = "syscon", "simple-bus";
121 #address-cells = <1>;
123 ranges = <0 0x270 0x330>;
125 pbias_regulator: pbias_regulator@2b0 {
126 compatible = "ti,pbias-omap3", "ti,pbias-omap";
128 syscon = <&scm_conf>;
129 pbias_mmc_reg: pbias_mmc_omap2430 {
130 regulator-name = "pbias_mmc_omap2430";
131 regulator-min-microvolt = <1800000>;
132 regulator-max-microvolt = <3000000>;
137 #address-cells = <1>;
142 scm_clockdomains: clockdomains {
145 omap3_pmx_wkup: pinmux@a00 {
146 compatible = "ti,omap3-padconf",
149 #address-cells = <1>;
151 #pinctrl-cells = <1>;
152 #interrupt-cells = <1>;
153 interrupt-controller;
154 pinctrl-single,register-width = <16>;
155 pinctrl-single,function-mask = <0xff1f>;
161 compatible = "ti,omap3-aes";
163 reg = <0x480c5000 0x50>;
165 dmas = <&sdma 65 &sdma 66>;
166 dma-names = "tx", "rx";
170 compatible = "ti,omap3-prm";
171 reg = <0x48306000 0x4000>;
175 #address-cells = <1>;
179 prm_clockdomains: clockdomains {
184 compatible = "ti,omap3-cm";
185 reg = <0x48004000 0x4000>;
188 #address-cells = <1>;
192 cm_clockdomains: clockdomains {
196 counter32k: counter@48320000 {
197 compatible = "ti,omap-counter32k";
198 reg = <0x48320000 0x20>;
199 ti,hwmods = "counter_32k";
202 intc: interrupt-controller@48200000 {
203 compatible = "ti,omap3-intc";
204 interrupt-controller;
205 #interrupt-cells = <1>;
206 reg = <0x48200000 0x1000>;
209 target-module@48056000 {
210 compatible = "ti,sysc-omap2", "ti,sysc";
211 reg = <0x48056000 0x4>,
214 reg-names = "rev", "sysc", "syss";
215 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
217 SYSC_OMAP2_SOFTRESET |
218 SYSC_OMAP2_AUTOIDLE)>;
219 ti,sysc-midle = <SYSC_IDLE_FORCE>,
222 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
226 /* Domains (V, P, C): core, core_pwrdm, core_l3_clkdm */
227 clocks = <&core_l3_ick>;
229 #address-cells = <1>;
231 ranges = <0 0x48056000 0x1000>;
233 sdma: dma-controller@0 {
234 compatible = "ti,omap3430-sdma", "ti,omap-sdma";
246 gpio1: gpio@48310000 {
247 compatible = "ti,omap3-gpio";
248 reg = <0x48310000 0x200>;
254 interrupt-controller;
255 #interrupt-cells = <2>;
258 gpio2: gpio@49050000 {
259 compatible = "ti,omap3-gpio";
260 reg = <0x49050000 0x200>;
265 interrupt-controller;
266 #interrupt-cells = <2>;
269 gpio3: gpio@49052000 {
270 compatible = "ti,omap3-gpio";
271 reg = <0x49052000 0x200>;
276 interrupt-controller;
277 #interrupt-cells = <2>;
280 gpio4: gpio@49054000 {
281 compatible = "ti,omap3-gpio";
282 reg = <0x49054000 0x200>;
287 interrupt-controller;
288 #interrupt-cells = <2>;
291 gpio5: gpio@49056000 {
292 compatible = "ti,omap3-gpio";
293 reg = <0x49056000 0x200>;
298 interrupt-controller;
299 #interrupt-cells = <2>;
302 gpio6: gpio@49058000 {
303 compatible = "ti,omap3-gpio";
304 reg = <0x49058000 0x200>;
309 interrupt-controller;
310 #interrupt-cells = <2>;
313 uart1: serial@4806a000 {
314 compatible = "ti,omap3-uart";
315 reg = <0x4806a000 0x2000>;
316 interrupts-extended = <&intc 72>;
317 dmas = <&sdma 49 &sdma 50>;
318 dma-names = "tx", "rx";
320 clock-frequency = <48000000>;
323 uart2: serial@4806c000 {
324 compatible = "ti,omap3-uart";
325 reg = <0x4806c000 0x400>;
326 interrupts-extended = <&intc 73>;
327 dmas = <&sdma 51 &sdma 52>;
328 dma-names = "tx", "rx";
330 clock-frequency = <48000000>;
333 uart3: serial@49020000 {
334 compatible = "ti,omap3-uart";
335 reg = <0x49020000 0x400>;
336 interrupts-extended = <&intc 74>;
337 dmas = <&sdma 53 &sdma 54>;
338 dma-names = "tx", "rx";
340 clock-frequency = <48000000>;
344 compatible = "ti,omap3-i2c";
345 reg = <0x48070000 0x80>;
347 dmas = <&sdma 27 &sdma 28>;
348 dma-names = "tx", "rx";
349 #address-cells = <1>;
355 compatible = "ti,omap3-i2c";
356 reg = <0x48072000 0x80>;
358 dmas = <&sdma 29 &sdma 30>;
359 dma-names = "tx", "rx";
360 #address-cells = <1>;
366 compatible = "ti,omap3-i2c";
367 reg = <0x48060000 0x80>;
369 dmas = <&sdma 25 &sdma 26>;
370 dma-names = "tx", "rx";
371 #address-cells = <1>;
376 mailbox: mailbox@48094000 {
377 compatible = "ti,omap3-mailbox";
378 ti,hwmods = "mailbox";
379 reg = <0x48094000 0x200>;
382 ti,mbox-num-users = <2>;
383 ti,mbox-num-fifos = <2>;
385 ti,mbox-tx = <0 0 0>;
386 ti,mbox-rx = <1 0 0>;
390 mcspi1: spi@48098000 {
391 compatible = "ti,omap2-mcspi";
392 reg = <0x48098000 0x100>;
394 #address-cells = <1>;
396 ti,hwmods = "mcspi1";
406 dma-names = "tx0", "rx0", "tx1", "rx1",
407 "tx2", "rx2", "tx3", "rx3";
410 mcspi2: spi@4809a000 {
411 compatible = "ti,omap2-mcspi";
412 reg = <0x4809a000 0x100>;
414 #address-cells = <1>;
416 ti,hwmods = "mcspi2";
422 dma-names = "tx0", "rx0", "tx1", "rx1";
425 mcspi3: spi@480b8000 {
426 compatible = "ti,omap2-mcspi";
427 reg = <0x480b8000 0x100>;
429 #address-cells = <1>;
431 ti,hwmods = "mcspi3";
437 dma-names = "tx0", "rx0", "tx1", "rx1";
440 mcspi4: spi@480ba000 {
441 compatible = "ti,omap2-mcspi";
442 reg = <0x480ba000 0x100>;
444 #address-cells = <1>;
446 ti,hwmods = "mcspi4";
448 dmas = <&sdma 70>, <&sdma 71>;
449 dma-names = "tx0", "rx0";
452 hdqw1w: 1w@480b2000 {
453 compatible = "ti,omap3-1w";
454 reg = <0x480b2000 0x1000>;
460 compatible = "ti,omap3-hsmmc";
461 reg = <0x4809c000 0x200>;
465 dmas = <&sdma 61>, <&sdma 62>;
466 dma-names = "tx", "rx";
467 pbias-supply = <&pbias_mmc_reg>;
471 compatible = "ti,omap3-hsmmc";
472 reg = <0x480b4000 0x200>;
475 dmas = <&sdma 47>, <&sdma 48>;
476 dma-names = "tx", "rx";
480 compatible = "ti,omap3-hsmmc";
481 reg = <0x480ad000 0x200>;
484 dmas = <&sdma 77>, <&sdma 78>;
485 dma-names = "tx", "rx";
488 mmu_isp: mmu@480bd400 {
490 compatible = "ti,omap2-iommu";
491 reg = <0x480bd400 0x80>;
493 ti,hwmods = "mmu_isp";
494 ti,#tlb-entries = <8>;
497 mmu_iva: mmu@5d000000 {
499 compatible = "ti,omap2-iommu";
500 reg = <0x5d000000 0x80>;
502 ti,hwmods = "mmu_iva";
507 compatible = "ti,omap3-wdt";
508 reg = <0x48314000 0x80>;
509 ti,hwmods = "wd_timer2";
512 mcbsp1: mcbsp@48074000 {
513 compatible = "ti,omap3-mcbsp";
514 reg = <0x48074000 0xff>;
516 interrupts = <16>, /* OCP compliant interrupt */
517 <59>, /* TX interrupt */
518 <60>; /* RX interrupt */
519 interrupt-names = "common", "tx", "rx";
520 ti,buffer-size = <128>;
521 ti,hwmods = "mcbsp1";
524 dma-names = "tx", "rx";
525 clocks = <&mcbsp1_fck>;
530 /* Likely needs to be tagged disabled on HS devices */
531 rng_target: target-module@480a0000 {
532 compatible = "ti,sysc-omap2", "ti,sysc";
533 reg = <0x480a003c 0x4>,
536 reg-names = "rev", "sysc", "syss";
537 ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
538 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
543 #address-cells = <1>;
545 ranges = <0 0x480a0000 0x2000>;
548 compatible = "ti,omap2-rng";
554 mcbsp2: mcbsp@49022000 {
555 compatible = "ti,omap3-mcbsp";
556 reg = <0x49022000 0xff>,
558 reg-names = "mpu", "sidetone";
559 interrupts = <17>, /* OCP compliant interrupt */
560 <62>, /* TX interrupt */
561 <63>, /* RX interrupt */
563 interrupt-names = "common", "tx", "rx", "sidetone";
564 ti,buffer-size = <1280>;
565 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
568 dma-names = "tx", "rx";
569 clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
570 clock-names = "fck", "ick";
574 mcbsp3: mcbsp@49024000 {
575 compatible = "ti,omap3-mcbsp";
576 reg = <0x49024000 0xff>,
578 reg-names = "mpu", "sidetone";
579 interrupts = <22>, /* OCP compliant interrupt */
580 <89>, /* TX interrupt */
581 <90>, /* RX interrupt */
583 interrupt-names = "common", "tx", "rx", "sidetone";
584 ti,buffer-size = <128>;
585 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
588 dma-names = "tx", "rx";
589 clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
590 clock-names = "fck", "ick";
594 mcbsp4: mcbsp@49026000 {
595 compatible = "ti,omap3-mcbsp";
596 reg = <0x49026000 0xff>;
598 interrupts = <23>, /* OCP compliant interrupt */
599 <54>, /* TX interrupt */
600 <55>; /* RX interrupt */
601 interrupt-names = "common", "tx", "rx";
602 ti,buffer-size = <128>;
603 ti,hwmods = "mcbsp4";
606 dma-names = "tx", "rx";
607 clocks = <&mcbsp4_fck>;
609 #sound-dai-cells = <0>;
613 mcbsp5: mcbsp@48096000 {
614 compatible = "ti,omap3-mcbsp";
615 reg = <0x48096000 0xff>;
617 interrupts = <27>, /* OCP compliant interrupt */
618 <81>, /* TX interrupt */
619 <82>; /* RX interrupt */
620 interrupt-names = "common", "tx", "rx";
621 ti,buffer-size = <128>;
622 ti,hwmods = "mcbsp5";
625 dma-names = "tx", "rx";
626 clocks = <&mcbsp5_fck>;
631 sham: sham@480c3000 {
632 compatible = "ti,omap3-sham";
634 reg = <0x480c3000 0x64>;
640 timer1: timer@48318000 {
641 compatible = "ti,omap3430-timer";
642 reg = <0x48318000 0x400>;
644 ti,hwmods = "timer1";
648 timer2: timer@49032000 {
649 compatible = "ti,omap3430-timer";
650 reg = <0x49032000 0x400>;
652 ti,hwmods = "timer2";
655 timer3: timer@49034000 {
656 compatible = "ti,omap3430-timer";
657 reg = <0x49034000 0x400>;
659 ti,hwmods = "timer3";
662 timer4: timer@49036000 {
663 compatible = "ti,omap3430-timer";
664 reg = <0x49036000 0x400>;
666 ti,hwmods = "timer4";
669 timer5: timer@49038000 {
670 compatible = "ti,omap3430-timer";
671 reg = <0x49038000 0x400>;
673 ti,hwmods = "timer5";
677 timer6: timer@4903a000 {
678 compatible = "ti,omap3430-timer";
679 reg = <0x4903a000 0x400>;
681 ti,hwmods = "timer6";
685 timer7: timer@4903c000 {
686 compatible = "ti,omap3430-timer";
687 reg = <0x4903c000 0x400>;
689 ti,hwmods = "timer7";
693 timer8: timer@4903e000 {
694 compatible = "ti,omap3430-timer";
695 reg = <0x4903e000 0x400>;
697 ti,hwmods = "timer8";
702 timer9: timer@49040000 {
703 compatible = "ti,omap3430-timer";
704 reg = <0x49040000 0x400>;
706 ti,hwmods = "timer9";
710 timer10: timer@48086000 {
711 compatible = "ti,omap3430-timer";
712 reg = <0x48086000 0x400>;
714 ti,hwmods = "timer10";
718 timer11: timer@48088000 {
719 compatible = "ti,omap3430-timer";
720 reg = <0x48088000 0x400>;
722 ti,hwmods = "timer11";
726 timer12: timer@48304000 {
727 compatible = "ti,omap3430-timer";
728 reg = <0x48304000 0x400>;
730 ti,hwmods = "timer12";
735 usbhstll: usbhstll@48062000 {
736 compatible = "ti,usbhs-tll";
737 reg = <0x48062000 0x1000>;
739 ti,hwmods = "usb_tll_hs";
742 usbhshost: usbhshost@48064000 {
743 compatible = "ti,usbhs-host";
744 reg = <0x48064000 0x400>;
745 ti,hwmods = "usb_host_hs";
746 #address-cells = <1>;
750 usbhsohci: ohci@48064400 {
751 compatible = "ti,ohci-omap3";
752 reg = <0x48064400 0x400>;
754 remote-wakeup-connected;
757 usbhsehci: ehci@48064800 {
758 compatible = "ti,ehci-omap";
759 reg = <0x48064800 0x400>;
764 gpmc: gpmc@6e000000 {
765 compatible = "ti,omap3430-gpmc";
767 reg = <0x6e000000 0x02d0>;
772 gpmc,num-waitpins = <4>;
773 #address-cells = <2>;
775 interrupt-controller;
776 #interrupt-cells = <2>;
781 usb_otg_hs: usb_otg_hs@480ab000 {
782 compatible = "ti,omap3-musb";
783 reg = <0x480ab000 0x1000>;
784 interrupts = <92>, <93>;
785 interrupt-names = "mc", "dma";
786 ti,hwmods = "usb_otg_hs";
793 compatible = "ti,omap3-dss";
794 reg = <0x48050000 0x200>;
796 ti,hwmods = "dss_core";
797 clocks = <&dss1_alwon_fck>;
799 #address-cells = <1>;
804 compatible = "ti,omap3-dispc";
805 reg = <0x48050400 0x400>;
807 ti,hwmods = "dss_dispc";
808 clocks = <&dss1_alwon_fck>;
812 dsi: encoder@4804fc00 {
813 compatible = "ti,omap3-dsi";
814 reg = <0x4804fc00 0x200>,
817 reg-names = "proto", "phy", "pll";
820 ti,hwmods = "dss_dsi1";
821 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
822 clock-names = "fck", "sys_clk";
825 rfbi: encoder@48050800 {
826 compatible = "ti,omap3-rfbi";
827 reg = <0x48050800 0x100>;
829 ti,hwmods = "dss_rfbi";
830 clocks = <&dss1_alwon_fck>, <&dss_ick>;
831 clock-names = "fck", "ick";
834 venc: encoder@48050c00 {
835 compatible = "ti,omap3-venc";
836 reg = <0x48050c00 0x100>;
838 ti,hwmods = "dss_venc";
839 clocks = <&dss_tv_fck>;
844 ssi: ssi-controller@48058000 {
845 compatible = "ti,omap3-ssi";
850 reg = <0x48058000 0x1000>,
856 interrupt-names = "gdd_mpu";
858 #address-cells = <1>;
862 ssi_port1: ssi-port@4805a000 {
863 compatible = "ti,omap3-ssi-port";
865 reg = <0x4805a000 0x800>,
874 ssi_port2: ssi-port@4805b000 {
875 compatible = "ti,omap3-ssi-port";
877 reg = <0x4805b000 0x800>,
889 /include/ "omap3xxx-clocks.dtsi"