2 * Device Tree Source for OMAP2 SoC
4 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/bus/ti-sysc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/omap.h>
17 compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
18 interrupt-parent = <&intc>;
36 compatible = "arm,arm1136jf-s";
42 compatible = "arm,arm1136-pmu";
47 compatible = "ti,omap-infra";
49 compatible = "ti,omap2-mpu";
55 compatible = "simple-bus";
59 ti,hwmods = "l3_main";
62 compatible = "ti,omap2-aes";
64 reg = <0x480a6000 0x50>;
65 dmas = <&sdma 9 &sdma 10>;
66 dma-names = "tx", "rx";
70 compatible = "ti,omap2420-1w";
72 reg = <0x480b2000 0x1000>;
76 intc: interrupt-controller@1 {
77 compatible = "ti,omap2-intc";
79 #interrupt-cells = <1>;
80 reg = <0x480FE000 0x1000>;
83 target-module@48056000 {
84 compatible = "ti,sysc-omap2", "ti,sysc";
85 reg = <0x48056000 0x4>,
88 reg-names = "rev", "sysc", "syss";
89 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
91 SYSC_OMAP2_SOFTRESET |
92 SYSC_OMAP2_AUTOIDLE)>;
93 ti,sysc-midle = <SYSC_IDLE_FORCE>,
97 clocks = <&core_l3_ck>;
101 ranges = <0 0x48056000 0x1000>;
103 sdma: dma-controller@0 {
104 compatible = "ti,omap2420-sdma", "ti,omap-sdma";
117 compatible = "ti,omap2-i2c";
119 reg = <0x48070000 0x80>;
120 #address-cells = <1>;
126 compatible = "ti,omap2-i2c";
128 reg = <0x48072000 0x80>;
129 #address-cells = <1>;
134 mcspi1: spi@48098000 {
135 compatible = "ti,omap2-mcspi";
136 ti,hwmods = "mcspi1";
137 reg = <0x48098000 0x100>;
139 dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
140 &sdma 39 &sdma 40 &sdma 41 &sdma 42>;
141 dma-names = "tx0", "rx0", "tx1", "rx1",
142 "tx2", "rx2", "tx3", "rx3";
145 mcspi2: spi@4809a000 {
146 compatible = "ti,omap2-mcspi";
147 ti,hwmods = "mcspi2";
148 reg = <0x4809a000 0x100>;
150 dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
151 dma-names = "tx0", "rx0", "tx1", "rx1";
155 compatible = "ti,omap2-rng";
157 reg = <0x480a0000 0x50>;
161 sham: sham@480a4000 {
162 compatible = "ti,omap2-sham";
164 reg = <0x480a4000 0x64>;
170 uart1: serial@4806a000 {
171 compatible = "ti,omap2-uart";
173 reg = <0x4806a000 0x2000>;
175 dmas = <&sdma 49 &sdma 50>;
176 dma-names = "tx", "rx";
177 clock-frequency = <48000000>;
180 uart2: serial@4806c000 {
181 compatible = "ti,omap2-uart";
183 reg = <0x4806c000 0x400>;
185 dmas = <&sdma 51 &sdma 52>;
186 dma-names = "tx", "rx";
187 clock-frequency = <48000000>;
190 uart3: serial@4806e000 {
191 compatible = "ti,omap2-uart";
193 reg = <0x4806e000 0x400>;
195 dmas = <&sdma 53 &sdma 54>;
196 dma-names = "tx", "rx";
197 clock-frequency = <48000000>;
200 timer2_target: target-module@4802a000 {
201 compatible = "ti,sysc-omap2-timer", "ti,sysc";
202 reg = <0x4802a000 0x4>,
205 reg-names = "rev", "sysc", "syss";
206 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
208 SYSC_OMAP2_ENAWAKEUP |
209 SYSC_OMAP2_SOFTRESET |
210 SYSC_OMAP2_AUTOIDLE)>;
211 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
215 clocks = <&gpt2_fck>, <&gpt2_ick>;
216 clock-names = "fck", "ick";
217 #address-cells = <1>;
219 ranges = <0x0 0x4802a000 0x1000>;
222 compatible = "ti,omap2420-timer";
228 timer3: timer@48078000 {
229 compatible = "ti,omap2420-timer";
230 reg = <0x48078000 0x400>;
232 ti,hwmods = "timer3";
235 timer4: timer@4807a000 {
236 compatible = "ti,omap2420-timer";
237 reg = <0x4807a000 0x400>;
239 ti,hwmods = "timer4";
242 timer5: timer@4807c000 {
243 compatible = "ti,omap2420-timer";
244 reg = <0x4807c000 0x400>;
246 ti,hwmods = "timer5";
250 timer6: timer@4807e000 {
251 compatible = "ti,omap2420-timer";
252 reg = <0x4807e000 0x400>;
254 ti,hwmods = "timer6";
258 timer7: timer@48080000 {
259 compatible = "ti,omap2420-timer";
260 reg = <0x48080000 0x400>;
262 ti,hwmods = "timer7";
266 timer8: timer@48082000 {
267 compatible = "ti,omap2420-timer";
268 reg = <0x48082000 0x400>;
270 ti,hwmods = "timer8";
274 timer9: timer@48084000 {
275 compatible = "ti,omap2420-timer";
276 reg = <0x48084000 0x400>;
278 ti,hwmods = "timer9";
282 timer10: timer@48086000 {
283 compatible = "ti,omap2420-timer";
284 reg = <0x48086000 0x400>;
286 ti,hwmods = "timer10";
290 timer11: timer@48088000 {
291 compatible = "ti,omap2420-timer";
292 reg = <0x48088000 0x400>;
294 ti,hwmods = "timer11";
298 timer12: timer@4808a000 {
299 compatible = "ti,omap2420-timer";
300 reg = <0x4808a000 0x400>;
302 ti,hwmods = "timer12";
307 compatible = "ti,omap2-dss";
308 reg = <0x48050000 0x400>;
310 ti,hwmods = "dss_core";
311 #address-cells = <1>;
316 compatible = "ti,omap2-dispc";
317 reg = <0x48050400 0x400>;
319 ti,hwmods = "dss_dispc";
322 rfbi: encoder@48050800 {
323 compatible = "ti,omap2-rfbi";
324 reg = <0x48050800 0x400>;
326 ti,hwmods = "dss_rfbi";
329 venc: encoder@48050c00 {
330 compatible = "ti,omap2-venc";
331 reg = <0x48050c00 0x400>;
333 ti,hwmods = "dss_venc";