2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: John Crispin <john@phrozen.org>
4 * Sean Wang <sean.wang@mediatek.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/clock/mt2701-clk.h>
19 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
20 #include <dt-bindings/power/mt2701-power.h>
21 #include <dt-bindings/gpio/gpio.h>
22 #include <dt-bindings/phy/phy.h>
23 #include <dt-bindings/reset/mt2701-resets.h>
24 #include <dt-bindings/thermal/thermal.h>
25 #include "skeleton64.dtsi"
28 compatible = "mediatek,mt7623";
29 interrupt-parent = <&sysirq>;
31 cpu_opp_table: opp_table {
32 compatible = "operating-points-v2";
36 opp-hz = /bits/ 64 <98000000>;
37 opp-microvolt = <1050000>;
41 opp-hz = /bits/ 64 <198000000>;
42 opp-microvolt = <1050000>;
46 opp-hz = /bits/ 64 <398000000>;
47 opp-microvolt = <1050000>;
51 opp-hz = /bits/ 64 <598000000>;
52 opp-microvolt = <1050000>;
56 opp-hz = /bits/ 64 <747500000>;
57 opp-microvolt = <1050000>;
61 opp-hz = /bits/ 64 <1040000000>;
62 opp-microvolt = <1150000>;
66 opp-hz = /bits/ 64 <1196000000>;
67 opp-microvolt = <1200000>;
71 opp-hz = /bits/ 64 <1300000000>;
72 opp-microvolt = <1300000>;
79 enable-method = "mediatek,mt6589-smp";
83 compatible = "arm,cortex-a7";
85 clocks = <&infracfg CLK_INFRA_CPUSEL>,
86 <&apmixedsys CLK_APMIXED_MAINPLL>;
87 clock-names = "cpu", "intermediate";
88 operating-points-v2 = <&cpu_opp_table>;
90 cooling-min-level = <0>;
91 cooling-max-level = <7>;
92 clock-frequency = <1300000000>;
97 compatible = "arm,cortex-a7";
99 operating-points-v2 = <&cpu_opp_table>;
100 clock-frequency = <1300000000>;
105 compatible = "arm,cortex-a7";
107 operating-points-v2 = <&cpu_opp_table>;
108 clock-frequency = <1300000000>;
113 compatible = "arm,cortex-a7";
115 operating-points-v2 = <&cpu_opp_table>;
116 clock-frequency = <1300000000>;
120 system_clk: dummy13m {
121 compatible = "fixed-clock";
122 clock-frequency = <13000000>;
126 rtc32k: oscillator@1 {
127 compatible = "fixed-clock";
129 clock-frequency = <32000>;
130 clock-output-names = "rtc32k";
133 clk26m: oscillator@0 {
134 compatible = "fixed-clock";
136 clock-frequency = <26000000>;
137 clock-output-names = "clk26m";
141 cpu_thermal: cpu_thermal {
142 polling-delay-passive = <1000>;
143 polling-delay = <1000>;
145 thermal-sensors = <&thermal 0>;
148 cpu_passive: cpu_passive {
149 temperature = <47000>;
154 cpu_active: cpu_active {
155 temperature = <67000>;
161 temperature = <87000>;
167 temperature = <107000>;
175 trip = <&cpu_passive>;
176 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
180 trip = <&cpu_active>;
181 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
186 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
193 compatible = "arm,armv7-timer";
194 interrupt-parent = <&gic>;
195 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
196 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
197 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
198 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
199 clock-frequency = <13000000>;
200 arm,cpu-registers-not-fw-configured;
203 topckgen: syscon@10000000 {
204 compatible = "mediatek,mt7623-topckgen",
205 "mediatek,mt2701-topckgen",
207 reg = <0 0x10000000 0 0x1000>;
211 infracfg: syscon@10001000 {
212 compatible = "mediatek,mt7623-infracfg",
213 "mediatek,mt2701-infracfg",
215 reg = <0 0x10001000 0 0x1000>;
220 pericfg: syscon@10003000 {
221 compatible = "mediatek,mt7623-pericfg",
222 "mediatek,mt2701-pericfg",
224 reg = <0 0x10003000 0 0x1000>;
229 pio: pinctrl@10005000 {
230 compatible = "mediatek,mt7623-pinctrl",
231 "mediatek,mt2701-pinctrl";
232 reg = <0 0x1000b000 0 0x1000>;
233 mediatek,pctl-regmap = <&syscfg_pctl_a>;
237 interrupt-controller;
238 interrupt-parent = <&gic>;
239 #interrupt-cells = <2>;
240 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
244 syscfg_pctl_a: syscfg@10005000 {
245 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
246 reg = <0 0x10005000 0 0x1000>;
249 scpsys: scpsys@10006000 {
250 compatible = "mediatek,mt7623-scpsys",
251 "mediatek,mt2701-scpsys",
253 #power-domain-cells = <1>;
254 reg = <0 0x10006000 0 0x1000>;
255 infracfg = <&infracfg>;
256 clocks = <&topckgen CLK_TOP_MM_SEL>,
257 <&topckgen CLK_TOP_MFG_SEL>,
258 <&topckgen CLK_TOP_ETHIF_SEL>;
259 clock-names = "mm", "mfg", "ethif";
262 watchdog: watchdog@10007000 {
263 compatible = "mediatek,mt7623-wdt",
264 "mediatek,mt6589-wdt";
265 reg = <0 0x10007000 0 0x100>;
268 timer: timer@10008000 {
269 compatible = "mediatek,mt7623-timer",
270 "mediatek,mt6577-timer";
271 reg = <0 0x10008000 0 0x80>;
272 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
273 clocks = <&system_clk>, <&rtc32k>;
274 clock-names = "system-clk", "rtc-clk";
277 pwrap: pwrap@1000d000 {
278 compatible = "mediatek,mt7623-pwrap",
279 "mediatek,mt2701-pwrap";
280 reg = <0 0x1000d000 0 0x1000>;
282 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
283 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
284 reset-names = "pwrap";
285 clocks = <&infracfg CLK_INFRA_PMICSPI>,
286 <&infracfg CLK_INFRA_PMICWRAP>;
287 clock-names = "spi", "wrap";
291 compatible = "mediatek,mt7623-cir";
292 reg = <0 0x10013000 0 0x1000>;
293 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
294 clocks = <&infracfg CLK_INFRA_IRRX>;
299 sysirq: interrupt-controller@10200100 {
300 compatible = "mediatek,mt7623-sysirq",
301 "mediatek,mt6577-sysirq";
302 interrupt-controller;
303 #interrupt-cells = <3>;
304 interrupt-parent = <&gic>;
305 reg = <0 0x10200100 0 0x1c>;
308 efuse: efuse@10206000 {
309 compatible = "mediatek,mt7623-efuse",
310 "mediatek,mt8173-efuse";
311 reg = <0 0x10206000 0 0x1000>;
312 #address-cells = <1>;
314 thermal_calibration_data: calib@424 {
319 apmixedsys: syscon@10209000 {
320 compatible = "mediatek,mt7623-apmixedsys",
321 "mediatek,mt2701-apmixedsys",
323 reg = <0 0x10209000 0 0x1000>;
328 compatible = "mediatek,mt7623-rng";
329 reg = <0 0x1020f000 0 0x1000>;
330 clocks = <&infracfg CLK_INFRA_TRNG>;
334 gic: interrupt-controller@10211000 {
335 compatible = "arm,cortex-a7-gic";
336 interrupt-controller;
337 #interrupt-cells = <3>;
338 interrupt-parent = <&gic>;
339 reg = <0 0x10211000 0 0x1000>,
340 <0 0x10212000 0 0x2000>,
341 <0 0x10214000 0 0x2000>,
342 <0 0x10216000 0 0x2000>;
345 auxadc: adc@11001000 {
346 compatible = "mediatek,mt7623-auxadc",
347 "mediatek,mt2701-auxadc";
348 reg = <0 0x11001000 0 0x1000>;
349 clocks = <&pericfg CLK_PERI_AUXADC>;
350 clock-names = "main";
351 #io-channel-cells = <1>;
354 uart0: serial@11002000 {
355 compatible = "mediatek,mt7623-uart",
356 "mediatek,mt6577-uart";
357 reg = <0 0x11002000 0 0x400>;
358 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
359 clocks = <&pericfg CLK_PERI_UART0_SEL>,
360 <&pericfg CLK_PERI_UART0>;
361 clock-names = "baud", "bus";
365 uart1: serial@11003000 {
366 compatible = "mediatek,mt7623-uart",
367 "mediatek,mt6577-uart";
368 reg = <0 0x11003000 0 0x400>;
369 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
370 clocks = <&pericfg CLK_PERI_UART1_SEL>,
371 <&pericfg CLK_PERI_UART1>;
372 clock-names = "baud", "bus";
376 uart2: serial@11004000 {
377 compatible = "mediatek,mt7623-uart",
378 "mediatek,mt6577-uart";
379 reg = <0 0x11004000 0 0x400>;
380 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
381 clocks = <&pericfg CLK_PERI_UART2_SEL>,
382 <&pericfg CLK_PERI_UART2>;
383 clock-names = "baud", "bus";
387 uart3: serial@11005000 {
388 compatible = "mediatek,mt7623-uart",
389 "mediatek,mt6577-uart";
390 reg = <0 0x11005000 0 0x400>;
391 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
392 clocks = <&pericfg CLK_PERI_UART3_SEL>,
393 <&pericfg CLK_PERI_UART3>;
394 clock-names = "baud", "bus";
399 compatible = "mediatek,mt7623-pwm";
400 reg = <0 0x11006000 0 0x1000>;
402 clocks = <&topckgen CLK_TOP_PWM_SEL>,
403 <&pericfg CLK_PERI_PWM>,
404 <&pericfg CLK_PERI_PWM1>,
405 <&pericfg CLK_PERI_PWM2>,
406 <&pericfg CLK_PERI_PWM3>,
407 <&pericfg CLK_PERI_PWM4>,
408 <&pericfg CLK_PERI_PWM5>;
409 clock-names = "top", "main", "pwm1", "pwm2",
410 "pwm3", "pwm4", "pwm5";
415 compatible = "mediatek,mt7623-i2c",
416 "mediatek,mt6577-i2c";
417 reg = <0 0x11007000 0 0x70>,
418 <0 0x11000200 0 0x80>;
419 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
421 clocks = <&pericfg CLK_PERI_I2C0>,
422 <&pericfg CLK_PERI_AP_DMA>;
423 clock-names = "main", "dma";
424 #address-cells = <1>;
430 compatible = "mediatek,mt7623-i2c",
431 "mediatek,mt6577-i2c";
432 reg = <0 0x11008000 0 0x70>,
433 <0 0x11000280 0 0x80>;
434 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
436 clocks = <&pericfg CLK_PERI_I2C1>,
437 <&pericfg CLK_PERI_AP_DMA>;
438 clock-names = "main", "dma";
439 #address-cells = <1>;
445 compatible = "mediatek,mt7623-i2c",
446 "mediatek,mt6577-i2c";
447 reg = <0 0x11009000 0 0x70>,
448 <0 0x11000300 0 0x80>;
449 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
451 clocks = <&pericfg CLK_PERI_I2C2>,
452 <&pericfg CLK_PERI_AP_DMA>;
453 clock-names = "main", "dma";
454 #address-cells = <1>;
460 compatible = "mediatek,mt7623-spi",
461 "mediatek,mt2701-spi";
462 #address-cells = <1>;
464 reg = <0 0x1100a000 0 0x100>;
465 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
466 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
467 <&topckgen CLK_TOP_SPI0_SEL>,
468 <&pericfg CLK_PERI_SPI0>;
469 clock-names = "parent-clk", "sel-clk", "spi-clk";
473 thermal: thermal@1100b000 {
474 #thermal-sensor-cells = <1>;
475 compatible = "mediatek,mt7623-thermal",
476 "mediatek,mt2701-thermal";
477 reg = <0 0x1100b000 0 0x1000>;
478 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
479 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
480 clock-names = "therm", "auxadc";
481 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
482 reset-names = "therm";
483 mediatek,auxadc = <&auxadc>;
484 mediatek,apmixedsys = <&apmixedsys>;
485 nvmem-cells = <&thermal_calibration_data>;
486 nvmem-cell-names = "calibration-data";
489 nandc: nfi@1100d000 {
490 compatible = "mediatek,mt7623-nfc",
491 "mediatek,mt2701-nfc";
492 reg = <0 0x1100d000 0 0x1000>;
493 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
494 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
495 clocks = <&pericfg CLK_PERI_NFI>,
496 <&pericfg CLK_PERI_NFI_PAD>;
497 clock-names = "nfi_clk", "pad_clk";
500 #address-cells = <1>;
505 compatible = "mediatek,mt7623-ecc",
506 "mediatek,mt2701-ecc";
507 reg = <0 0x1100e000 0 0x1000>;
508 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
509 clocks = <&pericfg CLK_PERI_NFI_ECC>;
510 clock-names = "nfiecc_clk";
515 compatible = "mediatek,mt7623-spi",
516 "mediatek,mt2701-spi";
517 #address-cells = <1>;
519 reg = <0 0x11016000 0 0x100>;
520 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
521 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
522 <&topckgen CLK_TOP_SPI1_SEL>,
523 <&pericfg CLK_PERI_SPI1>;
524 clock-names = "parent-clk", "sel-clk", "spi-clk";
529 compatible = "mediatek,mt7623-spi",
530 "mediatek,mt2701-spi";
531 #address-cells = <1>;
533 reg = <0 0x11017000 0 0x1000>;
534 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
535 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
536 <&topckgen CLK_TOP_SPI2_SEL>,
537 <&pericfg CLK_PERI_SPI2>;
538 clock-names = "parent-clk", "sel-clk", "spi-clk";
542 afe: audio-controller@11220000 {
543 compatible = "mediatek,mt7623-audio",
544 "mediatek,mt2701-audio";
545 reg = <0 0x11220000 0 0x2000>,
546 <0 0x112a0000 0 0x20000>;
547 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
548 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
550 clocks = <&infracfg CLK_INFRA_AUDIO>,
551 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
552 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
553 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
554 <&topckgen CLK_TOP_AUD_MUX2_DIV>,
555 <&topckgen CLK_TOP_AUD_48K_TIMING>,
556 <&topckgen CLK_TOP_AUD_44K_TIMING>,
557 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
558 <&topckgen CLK_TOP_APLL_SEL>,
559 <&topckgen CLK_TOP_AUD1PLL_98M>,
560 <&topckgen CLK_TOP_AUD2PLL_90M>,
561 <&topckgen CLK_TOP_HADDS2PLL_98M>,
562 <&topckgen CLK_TOP_HADDS2PLL_294M>,
563 <&topckgen CLK_TOP_AUDPLL>,
564 <&topckgen CLK_TOP_AUDPLL_D4>,
565 <&topckgen CLK_TOP_AUDPLL_D8>,
566 <&topckgen CLK_TOP_AUDPLL_D16>,
567 <&topckgen CLK_TOP_AUDPLL_D24>,
568 <&topckgen CLK_TOP_AUDINTBUS_SEL>,
570 <&topckgen CLK_TOP_SYSPLL1_D4>,
571 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
572 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
573 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
574 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
575 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
576 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
577 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
578 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
579 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
580 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
581 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
582 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
583 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
584 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
585 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
586 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
587 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
588 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
589 <&topckgen CLK_TOP_ASM_M_SEL>,
590 <&topckgen CLK_TOP_ASM_H_SEL>,
591 <&topckgen CLK_TOP_UNIVPLL2_D4>,
592 <&topckgen CLK_TOP_UNIVPLL2_D2>,
593 <&topckgen CLK_TOP_SYSPLL_D5>;
595 clock-names = "infra_sys_audio_clk",
596 "top_audio_mux1_sel",
597 "top_audio_mux2_sel",
598 "top_audio_mux1_div",
599 "top_audio_mux2_div",
600 "top_audio_48k_timing",
601 "top_audio_44k_timing",
602 "top_audpll_mux_sel",
606 "top_hadds2_pll_98M",
607 "top_hadds2_pll_294M",
616 "top_aud_k1_src_sel",
617 "top_aud_k2_src_sel",
618 "top_aud_k3_src_sel",
619 "top_aud_k4_src_sel",
620 "top_aud_k5_src_sel",
621 "top_aud_k6_src_sel",
622 "top_aud_k1_src_div",
623 "top_aud_k2_src_div",
624 "top_aud_k3_src_div",
625 "top_aud_k4_src_div",
626 "top_aud_k5_src_div",
627 "top_aud_k6_src_div",
642 compatible = "mediatek,mt7623-mmc",
643 "mediatek,mt8135-mmc";
644 reg = <0 0x11230000 0 0x1000>;
645 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
646 clocks = <&pericfg CLK_PERI_MSDC30_0>,
647 <&topckgen CLK_TOP_MSDC30_0_SEL>;
648 clock-names = "source", "hclk";
653 compatible = "mediatek,mt7623-mmc",
654 "mediatek,mt8135-mmc";
655 reg = <0 0x11240000 0 0x1000>;
656 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
657 clocks = <&pericfg CLK_PERI_MSDC30_1>,
658 <&topckgen CLK_TOP_MSDC30_1_SEL>;
659 clock-names = "source", "hclk";
663 hifsys: syscon@1a000000 {
664 compatible = "mediatek,mt7623-hifsys",
665 "mediatek,mt2701-hifsys",
667 reg = <0 0x1a000000 0 0x1000>;
673 compatible = "mediatek,mt7623-xhci",
674 "mediatek,mt8173-xhci";
675 reg = <0 0x1a1c0000 0 0x1000>,
676 <0 0x1a1c4700 0 0x0100>;
677 reg-names = "mac", "ippc";
678 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
679 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
680 <&topckgen CLK_TOP_ETHIF_SEL>;
681 clock-names = "sys_ck", "free_ck";
682 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
683 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
687 u3phy1: usb-phy@1a1c4000 {
688 compatible = "mediatek,mt7623-u3phy",
689 "mediatek,mt2701-u3phy";
690 reg = <0 0x1a1c4000 0 0x0700>;
692 clock-names = "u3phya_ref";
693 #address-cells = <2>;
698 u2port0: usb-phy@1a1c4800 {
699 reg = <0 0x1a1c4800 0 0x0100>;
704 u3port0: usb-phy@1a1c4900 {
705 reg = <0 0x1a1c4900 0 0x0700>;
712 compatible = "mediatek,mt7623-xhci",
713 "mediatek,mt8173-xhci";
714 reg = <0 0x1a240000 0 0x1000>,
715 <0 0x1a244700 0 0x0100>;
716 reg-names = "mac", "ippc";
717 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
718 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
719 <&topckgen CLK_TOP_ETHIF_SEL>;
720 clock-names = "sys_ck", "free_ck";
721 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
722 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
726 u3phy2: usb-phy@1a244000 {
727 compatible = "mediatek,mt7623-u3phy",
728 "mediatek,mt2701-u3phy";
729 reg = <0 0x1a244000 0 0x0700>;
731 clock-names = "u3phya_ref";
732 #address-cells = <2>;
737 u2port1: usb-phy@1a244800 {
738 reg = <0 0x1a244800 0 0x0100>;
743 u3port1: usb-phy@1a244900 {
744 reg = <0 0x1a244900 0 0x0700>;
750 ethsys: syscon@1b000000 {
751 compatible = "mediatek,mt7623-ethsys",
752 "mediatek,mt2701-ethsys",
754 reg = <0 0x1b000000 0 0x1000>;
758 eth: ethernet@1b100000 {
759 compatible = "mediatek,mt7623-eth",
760 "mediatek,mt2701-eth",
762 reg = <0 0x1b100000 0 0x20000>;
763 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
764 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
765 <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
766 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
767 <ðsys CLK_ETHSYS_ESW>,
768 <ðsys CLK_ETHSYS_GP1>,
769 <ðsys CLK_ETHSYS_GP2>,
770 <&apmixedsys CLK_APMIXED_TRGPLL>;
771 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
772 resets = <ðsys MT2701_ETHSYS_FE_RST>,
773 <ðsys MT2701_ETHSYS_GMAC_RST>,
774 <ðsys MT2701_ETHSYS_PPE_RST>;
775 reset-names = "fe", "gmac", "ppe";
776 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
777 mediatek,ethsys = <ðsys>;
778 mediatek,pctl = <&syscfg_pctl_a>;
779 #address-cells = <1>;
784 crypto: crypto@1b240000 {
785 compatible = "mediatek,mt7623-crypto";
786 reg = <0 0x1b240000 0 0x20000>;
787 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
788 <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
789 <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
790 <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
791 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
792 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
793 <ðsys CLK_ETHSYS_CRYPTO>;
794 clock-names = "ethif","cryp";
795 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;