arch/arm/boot/dts/mt7623.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017-2018 MediaTek Inc.
   4  * Author: John Crispin <john@phrozen.org>
   5  *         Sean Wang <sean.wang@mediatek.com>
   6  *
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/clock/mt2701-clk.h>
  12 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
  13 #include <dt-bindings/power/mt2701-power.h>
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/phy/phy.h>
  16 #include <dt-bindings/reset/mt2701-resets.h>
  17 #include <dt-bindings/thermal/thermal.h>
  18
  19 / {
  20         compatible = "mediatek,mt7623";
  21         interrupt-parent = <&sysirq>;
  22         #address-cells = <2>;
  23         #size-cells = <2>;
  24
  25         cpu_opp_table: opp-table {
  26                 compatible = "operating-points-v2";
  27                 opp-shared;
  28
  29                 opp-98000000 {
  30                         opp-hz = /bits/ 64 <98000000>;
  31                         opp-microvolt = <1050000>;
  32                 };
  33
  34                 opp-198000000 {
  35                         opp-hz = /bits/ 64 <198000000>;
  36                         opp-microvolt = <1050000>;
  37                 };
  38
  39                 opp-398000000 {
  40                         opp-hz = /bits/ 64 <398000000>;
  41                         opp-microvolt = <1050000>;
  42                 };
  43
  44                 opp-598000000 {
  45                         opp-hz = /bits/ 64 <598000000>;
  46                         opp-microvolt = <1050000>;
  47                 };
  48
  49                 opp-747500000 {
  50                         opp-hz = /bits/ 64 <747500000>;
  51                         opp-microvolt = <1050000>;
  52                 };
  53
  54                 opp-1040000000 {
  55                         opp-hz = /bits/ 64 <1040000000>;
  56                         opp-microvolt = <1150000>;
  57                 };
  58
  59                 opp-1196000000 {
  60                         opp-hz = /bits/ 64 <1196000000>;
  61                         opp-microvolt = <1200000>;
  62                 };
  63
  64                 opp-1300000000 {
  65                         opp-hz = /bits/ 64 <1300000000>;
  66                         opp-microvolt = <1300000>;
  67                 };
  68         };
  69
  70         cpus {
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73                 enable-method = "mediatek,mt6589-smp";
  74
  75                 cpu0: cpu@0 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a7";
  78                         reg = <0x0>;
  79                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  80                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  81                         clock-names = "cpu", "intermediate";
  82                         operating-points-v2 = <&cpu_opp_table>;
  83                         #cooling-cells = <2>;
  84                         clock-frequency = <1300000000>;
  85                 };
  86
  87                 cpu1: cpu@1 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a7";
  90                         reg = <0x1>;
  91                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  92                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  93                         clock-names = "cpu", "intermediate";
  94                         operating-points-v2 = <&cpu_opp_table>;
  95                         #cooling-cells = <2>;
  96                         clock-frequency = <1300000000>;
  97                 };
  98
  99                 cpu2: cpu@2 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a7";
 102                         reg = <0x2>;
 103                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
 104                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 105                         clock-names = "cpu", "intermediate";
 106                         operating-points-v2 = <&cpu_opp_table>;
 107                         #cooling-cells = <2>;
 108                         clock-frequency = <1300000000>;
 109                 };
 110
 111                 cpu3: cpu@3 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a7";
 114                         reg = <0x3>;
 115                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
 116                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 117                         clock-names = "cpu", "intermediate";
 118                         operating-points-v2 = <&cpu_opp_table>;
 119                         #cooling-cells = <2>;
 120                         clock-frequency = <1300000000>;
 121                 };
 122         };
 123
 124         pmu {
 125                 compatible = "arm,cortex-a7-pmu";
 126                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
 127                              <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
 128                              <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
 129                              <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
 130                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 131         };
 132
 133         system_clk: dummy13m {
 134                 compatible = "fixed-clock";
 135                 clock-frequency = <13000000>;
 136                 #clock-cells = <0>;
 137         };
 138
 139         rtc32k: oscillator-1 {
 140                 compatible = "fixed-clock";
 141                 #clock-cells = <0>;
 142                 clock-frequency = <32000>;
 143                 clock-output-names = "rtc32k";
 144         };
 145
 146         clk26m: oscillator-0 {
 147                 compatible = "fixed-clock";
 148                 #clock-cells = <0>;
 149                 clock-frequency = <26000000>;
 150                 clock-output-names = "clk26m";
 151         };
 152
 153         thermal-zones {
 154                         cpu_thermal: cpu-thermal {
 155                                 polling-delay-passive = <1000>;
 156                                 polling-delay = <1000>;
 157
 158                                 thermal-sensors = <&thermal 0>;
 159
 160                                 trips {
 161                                         cpu_passive: cpu-passive {
 162                                                 temperature = <47000>;
 163                                                 hysteresis = <2000>;
 164                                                 type = "passive";
 165                                         };
 166
 167                                         cpu_active: cpu-active {
 168                                                 temperature = <67000>;
 169                                                 hysteresis = <2000>;
 170                                                 type = "active";
 171                                         };
 172
 173                                         cpu_hot: cpu-hot {
 174                                                 temperature = <87000>;
 175                                                 hysteresis = <2000>;
 176                                                 type = "hot";
 177                                         };
 178
 179                                         cpu-crit {
 180                                                 temperature = <107000>;
 181                                                 hysteresis = <2000>;
 182                                                 type = "critical";
 183                                         };
 184                                 };
 185
 186                         cooling-maps {
 187                                 map0 {
 188                                         trip = <&cpu_passive>;
 189                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 190                                 };
 191
 192                                 map1 {
 193                                         trip = <&cpu_active>;
 194                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 195                                 };
 196
 197                                 map2 {
 198                                         trip = <&cpu_hot>;
 199                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 200                                 };
 201                         };
 202                 };
 203         };
 204
 205         timer {
 206                 compatible = "arm,armv7-timer";
 207                 interrupt-parent = <&gic>;
 208                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 209                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 210                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 211                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 212                 clock-frequency = <13000000>;
 213                 arm,cpu-registers-not-fw-configured;
 214         };
 215
 216         topckgen: syscon@10000000 {
 217                 compatible = "mediatek,mt7623-topckgen",
 218                              "mediatek,mt2701-topckgen",
 219                              "syscon";
 220                 reg = <0 0x10000000 0 0x1000>;
 221                 #clock-cells = <1>;
 222         };
 223
 224         infracfg: syscon@10001000 {
 225                 compatible = "mediatek,mt7623-infracfg",
 226                              "mediatek,mt2701-infracfg",
 227                              "syscon";
 228                 reg = <0 0x10001000 0 0x1000>;
 229                 #clock-cells = <1>;
 230                 #reset-cells = <1>;
 231         };
 232
 233         pericfg: syscon@10003000 {
 234                 compatible =  "mediatek,mt7623-pericfg",
 235                               "mediatek,mt2701-pericfg",
 236                               "syscon";
 237                 reg = <0 0x10003000 0 0x1000>;
 238                 #clock-cells = <1>;
 239                 #reset-cells = <1>;
 240         };
 241
 242         pio: pinctrl@10005000 {
 243                 compatible = "mediatek,mt7623-pinctrl";
 244                 reg = <0 0x1000b000 0 0x1000>;
 245                 mediatek,pctl-regmap = <&syscfg_pctl_a>;
 246                 pins-are-numbered;
 247                 gpio-controller;
 248                 #gpio-cells = <2>;
 249                 interrupt-controller;
 250                 interrupt-parent = <&gic>;
 251                 #interrupt-cells = <2>;
 252                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 253                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 254         };
 255
 256         syscfg_pctl_a: syscfg@10005000 {
 257                 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
 258                 reg = <0 0x10005000 0 0x1000>;
 259         };
 260
 261         scpsys: scpsys@10006000 {
 262                 compatible = "mediatek,mt7623-scpsys",
 263                              "mediatek,mt2701-scpsys",
 264                              "syscon";
 265                 #power-domain-cells = <1>;
 266                 reg = <0 0x10006000 0 0x1000>;
 267                 infracfg = <&infracfg>;
 268                 clocks = <&topckgen CLK_TOP_MM_SEL>,
 269                          <&topckgen CLK_TOP_MFG_SEL>,
 270                          <&topckgen CLK_TOP_ETHIF_SEL>;
 271                 clock-names = "mm", "mfg", "ethif";
 272         };
 273
 274         watchdog: watchdog@10007000 {
 275                 compatible = "mediatek,mt7623-wdt",
 276                              "mediatek,mt6589-wdt";
 277                 reg = <0 0x10007000 0 0x100>;
 278         };
 279
 280         timer: timer@10008000 {
 281                 compatible = "mediatek,mt7623-timer",
 282                              "mediatek,mt6577-timer";
 283                 reg = <0 0x10008000 0 0x80>;
 284                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 285                 clocks = <&system_clk>, <&rtc32k>;
 286                 clock-names = "system-clk", "rtc-clk";
 287         };
 288
 289         pwrap: pwrap@1000d000 {
 290                 compatible = "mediatek,mt7623-pwrap",
 291                              "mediatek,mt2701-pwrap";
 292                 reg = <0 0x1000d000 0 0x1000>;
 293                 reg-names = "pwrap";
 294                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 295                 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
 296                 reset-names = "pwrap";
 297                 clocks = <&infracfg CLK_INFRA_PMICSPI>,
 298                          <&infracfg CLK_INFRA_PMICWRAP>;
 299                 clock-names = "spi", "wrap";
 300         };
 301
 302         cir: cir@10013000 {
 303                 compatible = "mediatek,mt7623-cir";
 304                 reg = <0 0x10013000 0 0x1000>;
 305                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
 306                 clocks = <&infracfg CLK_INFRA_IRRX>;
 307                 clock-names = "clk";
 308                 status = "disabled";
 309         };
 310
 311         sysirq: interrupt-controller@10200100 {
 312                 compatible = "mediatek,mt7623-sysirq",
 313                              "mediatek,mt6577-sysirq";
 314                 interrupt-controller;
 315                 #interrupt-cells = <3>;
 316                 interrupt-parent = <&gic>;
 317                 reg = <0 0x10200100 0 0x1c>;
 318         };
 319
 320         efuse: efuse@10206000 {
 321                 compatible = "mediatek,mt7623-efuse",
 322                              "mediatek,mt8173-efuse";
 323                 reg = <0 0x10206000 0 0x1000>;
 324                 #address-cells = <1>;
 325                 #size-cells = <1>;
 326                 thermal_calibration_data: calib@424 {
 327                         reg = <0x424 0xc>;
 328                 };
 329         };
 330
 331         apmixedsys: syscon@10209000 {
 332                 compatible = "mediatek,mt7623-apmixedsys",
 333                              "mediatek,mt2701-apmixedsys",
 334                              "syscon";
 335                 reg = <0 0x10209000 0 0x1000>;
 336                 #clock-cells = <1>;
 337         };
 338
 339         rng: rng@1020f000 {
 340                 compatible = "mediatek,mt7623-rng";
 341                 reg = <0 0x1020f000 0 0x1000>;
 342                 clocks = <&infracfg CLK_INFRA_TRNG>;
 343                 clock-names = "rng";
 344         };
 345
 346         gic: interrupt-controller@10211000 {
 347                 compatible = "arm,cortex-a7-gic";
 348                 interrupt-controller;
 349                 #interrupt-cells = <3>;
 350                 interrupt-parent = <&gic>;
 351                 reg = <0 0x10211000 0 0x1000>,
 352                       <0 0x10212000 0 0x2000>,
 353                       <0 0x10214000 0 0x2000>,
 354                       <0 0x10216000 0 0x2000>;
 355         };
 356
 357         auxadc: adc@11001000 {
 358                 compatible = "mediatek,mt7623-auxadc",
 359                              "mediatek,mt2701-auxadc";
 360                 reg = <0 0x11001000 0 0x1000>;
 361                 clocks = <&pericfg CLK_PERI_AUXADC>;
 362                 clock-names = "main";
 363                 #io-channel-cells = <1>;
 364         };
 365
 366         uart0: serial@11002000 {
 367                 compatible = "mediatek,mt7623-uart",
 368                              "mediatek,mt6577-uart";
 369                 reg = <0 0x11002000 0 0x400>;
 370                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 371                 clocks = <&pericfg CLK_PERI_UART0_SEL>,
 372                          <&pericfg CLK_PERI_UART0>;
 373                 clock-names = "baud", "bus";
 374                 status = "disabled";
 375         };
 376
 377         uart1: serial@11003000 {
 378                 compatible = "mediatek,mt7623-uart",
 379                              "mediatek,mt6577-uart";
 380                 reg = <0 0x11003000 0 0x400>;
 381                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 382                 clocks = <&pericfg CLK_PERI_UART1_SEL>,
 383                          <&pericfg CLK_PERI_UART1>;
 384                 clock-names = "baud", "bus";
 385                 status = "disabled";
 386         };
 387
 388         uart2: serial@11004000 {
 389                 compatible = "mediatek,mt7623-uart",
 390                              "mediatek,mt6577-uart";
 391                 reg = <0 0x11004000 0 0x400>;
 392                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 393                 clocks = <&pericfg CLK_PERI_UART2_SEL>,
 394                          <&pericfg CLK_PERI_UART2>;
 395                 clock-names = "baud", "bus";
 396                 status = "disabled";
 397         };
 398
 399         uart3: serial@11005000 {
 400                 compatible = "mediatek,mt7623-uart",
 401                              "mediatek,mt6577-uart";
 402                 reg = <0 0x11005000 0 0x400>;
 403                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 404                 clocks = <&pericfg CLK_PERI_UART3_SEL>,
 405                          <&pericfg CLK_PERI_UART3>;
 406                 clock-names = "baud", "bus";
 407                 status = "disabled";
 408         };
 409
 410         pwm: pwm@11006000 {
 411                 compatible = "mediatek,mt7623-pwm";
 412                 reg = <0 0x11006000 0 0x1000>;
 413                 #pwm-cells = <2>;
 414                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 415                          <&pericfg CLK_PERI_PWM>,
 416                          <&pericfg CLK_PERI_PWM1>,
 417                          <&pericfg CLK_PERI_PWM2>,
 418                          <&pericfg CLK_PERI_PWM3>,
 419                          <&pericfg CLK_PERI_PWM4>,
 420                          <&pericfg CLK_PERI_PWM5>;
 421                 clock-names = "top", "main", "pwm1", "pwm2",
 422                               "pwm3", "pwm4", "pwm5";
 423                 status = "disabled";
 424         };
 425
 426         i2c0: i2c@11007000 {
 427                 compatible = "mediatek,mt7623-i2c",
 428                              "mediatek,mt6577-i2c";
 429                 reg = <0 0x11007000 0 0x70>,
 430                       <0 0x11000200 0 0x80>;
 431                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
 432                 clock-div = <16>;
 433                 clocks = <&pericfg CLK_PERI_I2C0>,
 434                          <&pericfg CLK_PERI_AP_DMA>;
 435                 clock-names = "main", "dma";
 436                 #address-cells = <1>;
 437                 #size-cells = <0>;
 438                 status = "disabled";
 439         };
 440
 441         i2c1: i2c@11008000 {
 442                 compatible = "mediatek,mt7623-i2c",
 443                              "mediatek,mt6577-i2c";
 444                 reg = <0 0x11008000 0 0x70>,
 445                       <0 0x11000280 0 0x80>;
 446                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
 447                 clock-div = <16>;
 448                 clocks = <&pericfg CLK_PERI_I2C1>,
 449                          <&pericfg CLK_PERI_AP_DMA>;
 450                 clock-names = "main", "dma";
 451                 #address-cells = <1>;
 452                 #size-cells = <0>;
 453                 status = "disabled";
 454         };
 455
 456         i2c2: i2c@11009000 {
 457                 compatible = "mediatek,mt7623-i2c",
 458                              "mediatek,mt6577-i2c";
 459                 reg = <0 0x11009000 0 0x70>,
 460                       <0 0x11000300 0 0x80>;
 461                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
 462                 clock-div = <16>;
 463                 clocks = <&pericfg CLK_PERI_I2C2>,
 464                          <&pericfg CLK_PERI_AP_DMA>;
 465                 clock-names = "main", "dma";
 466                 #address-cells = <1>;
 467                 #size-cells = <0>;
 468                 status = "disabled";
 469         };
 470
 471         spi0: spi@1100a000 {
 472                 compatible = "mediatek,mt7623-spi",
 473                              "mediatek,mt2701-spi";
 474                 #address-cells = <1>;
 475                 #size-cells = <0>;
 476                 reg = <0 0x1100a000 0 0x100>;
 477                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 478                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 479                          <&topckgen CLK_TOP_SPI0_SEL>,
 480                          <&pericfg CLK_PERI_SPI0>;
 481                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 482                 status = "disabled";
 483         };
 484
 485         thermal: thermal@1100b000 {
 486                 #thermal-sensor-cells = <1>;
 487                 compatible = "mediatek,mt7623-thermal",
 488                              "mediatek,mt2701-thermal";
 489                 reg = <0 0x1100b000 0 0x1000>;
 490                 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 491                 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 492                 clock-names = "therm", "auxadc";
 493                 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
 494                 reset-names = "therm";
 495                 mediatek,auxadc = <&auxadc>;
 496                 mediatek,apmixedsys = <&apmixedsys>;
 497                 nvmem-cells = <&thermal_calibration_data>;
 498                 nvmem-cell-names = "calibration-data";
 499         };
 500
 501         btif: serial@1100c000 {
 502                 compatible = "mediatek,mt7623-btif",
 503                              "mediatek,mtk-btif";
 504                 reg = <0 0x1100c000 0 0x1000>;
 505                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>;
 506                 clocks = <&pericfg CLK_PERI_BTIF>;
 507                 clock-names = "main";
 508                 reg-shift = <2>;
 509                 reg-io-width = <4>;
 510                 status = "disabled";
 511         };
 512
 513         nandc: nfi@1100d000 {
 514                 compatible = "mediatek,mt7623-nfc",
 515                              "mediatek,mt2701-nfc";
 516                 reg = <0 0x1100d000 0 0x1000>;
 517                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
 518                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 519                 clocks = <&pericfg CLK_PERI_NFI>,
 520                          <&pericfg CLK_PERI_NFI_PAD>;
 521                 clock-names = "nfi_clk", "pad_clk";
 522                 status = "disabled";
 523                 ecc-engine = <&bch>;
 524                 #address-cells = <1>;
 525                 #size-cells = <0>;
 526         };
 527
 528         bch: ecc@1100e000 {
 529                 compatible = "mediatek,mt7623-ecc",
 530                              "mediatek,mt2701-ecc";
 531                 reg = <0 0x1100e000 0 0x1000>;
 532                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 533                 clocks = <&pericfg CLK_PERI_NFI_ECC>;
 534                 clock-names = "nfiecc_clk";
 535                 status = "disabled";
 536         };
 537
 538         nor_flash: spi@11014000 {
 539                 compatible = "mediatek,mt7623-nor",
 540                              "mediatek,mt8173-nor";
 541                 reg = <0 0x11014000 0 0x1000>;
 542                 clocks = <&pericfg CLK_PERI_FLASH>,
 543                          <&topckgen CLK_TOP_FLASH_SEL>;
 544                 clock-names = "spi", "sf";
 545                 #address-cells = <1>;
 546                 #size-cells = <0>;
 547                 status = "disabled";
 548         };
 549
 550         spi1: spi@11016000 {
 551                 compatible = "mediatek,mt7623-spi",
 552                              "mediatek,mt2701-spi";
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 reg = <0 0x11016000 0 0x100>;
 556                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 557                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 558                          <&topckgen CLK_TOP_SPI1_SEL>,
 559                          <&pericfg CLK_PERI_SPI1>;
 560                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 561                 status = "disabled";
 562         };
 563
 564         spi2: spi@11017000 {
 565                 compatible = "mediatek,mt7623-spi",
 566                              "mediatek,mt2701-spi";
 567                 #address-cells = <1>;
 568                 #size-cells = <0>;
 569                 reg = <0 0x11017000 0 0x1000>;
 570                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
 571                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 572                          <&topckgen CLK_TOP_SPI2_SEL>,
 573                          <&pericfg CLK_PERI_SPI2>;
 574                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 575                 status = "disabled";
 576         };
 577
 578         audsys: clock-controller@11220000 {
 579                 compatible = "mediatek,mt7623-audsys",
 580                              "mediatek,mt2701-audsys",
 581                              "syscon";
 582                 reg = <0 0x11220000 0 0x2000>;
 583                 #clock-cells = <1>;
 584
 585                 afe: audio-controller {
 586                         compatible = "mediatek,mt7623-audio",
 587                                      "mediatek,mt2701-audio";
 588                         interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
 589                                       <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 590                         interrupt-names = "afe", "asys";
 591                         power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 592
 593                         clocks = <&infracfg CLK_INFRA_AUDIO>,
 594                                  <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 595                                  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 596                                  <&topckgen CLK_TOP_AUD_48K_TIMING>,
 597                                  <&topckgen CLK_TOP_AUD_44K_TIMING>,
 598                                  <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
 599                                  <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
 600                                  <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
 601                                  <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
 602                                  <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
 603                                  <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
 604                                  <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
 605                                  <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
 606                                  <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
 607                                  <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
 608                                  <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
 609                                  <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
 610                                  <&audsys CLK_AUD_I2SO1>,
 611                                  <&audsys CLK_AUD_I2SO2>,
 612                                  <&audsys CLK_AUD_I2SO3>,
 613                                  <&audsys CLK_AUD_I2SO4>,
 614                                  <&audsys CLK_AUD_I2SIN1>,
 615                                  <&audsys CLK_AUD_I2SIN2>,
 616                                  <&audsys CLK_AUD_I2SIN3>,
 617                                  <&audsys CLK_AUD_I2SIN4>,
 618                                  <&audsys CLK_AUD_ASRCO1>,
 619                                  <&audsys CLK_AUD_ASRCO2>,
 620                                  <&audsys CLK_AUD_ASRCO3>,
 621                                  <&audsys CLK_AUD_ASRCO4>,
 622                                  <&audsys CLK_AUD_AFE>,
 623                                  <&audsys CLK_AUD_AFE_CONN>,
 624                                  <&audsys CLK_AUD_A1SYS>,
 625                                  <&audsys CLK_AUD_A2SYS>,
 626                                  <&audsys CLK_AUD_AFE_MRGIF>;
 627
 628                         clock-names = "infra_sys_audio_clk",
 629                                       "top_audio_mux1_sel",
 630                                       "top_audio_mux2_sel",
 631                                       "top_audio_a1sys_hp",
 632                                       "top_audio_a2sys_hp",
 633                                       "i2s0_src_sel",
 634                                       "i2s1_src_sel",
 635                                       "i2s2_src_sel",
 636                                       "i2s3_src_sel",
 637                                       "i2s0_src_div",
 638                                       "i2s1_src_div",
 639                                       "i2s2_src_div",
 640                                       "i2s3_src_div",
 641                                       "i2s0_mclk_en",
 642                                       "i2s1_mclk_en",
 643                                       "i2s2_mclk_en",
 644                                       "i2s3_mclk_en",
 645                                       "i2so0_hop_ck",
 646                                       "i2so1_hop_ck",
 647                                       "i2so2_hop_ck",
 648                                       "i2so3_hop_ck",
 649                                       "i2si0_hop_ck",
 650                                       "i2si1_hop_ck",
 651                                       "i2si2_hop_ck",
 652                                       "i2si3_hop_ck",
 653                                       "asrc0_out_ck",
 654                                       "asrc1_out_ck",
 655                                       "asrc2_out_ck",
 656                                       "asrc3_out_ck",
 657                                       "audio_afe_pd",
 658                                       "audio_afe_conn_pd",
 659                                       "audio_a1sys_pd",
 660                                       "audio_a2sys_pd",
 661                                       "audio_mrgif_pd";
 662
 663                         assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 664                                           <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 665                                           <&topckgen CLK_TOP_AUD_MUX1_DIV>,
 666                                           <&topckgen CLK_TOP_AUD_MUX2_DIV>;
 667                         assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
 668                                                  <&topckgen CLK_TOP_AUD2PLL_90M>;
 669                         assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
 670                 };
 671         };
 672
 673         mmc0: mmc@11230000 {
 674                 compatible = "mediatek,mt7623-mmc",
 675                              "mediatek,mt2701-mmc";
 676                 reg = <0 0x11230000 0 0x1000>;
 677                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
 678                 clocks = <&pericfg CLK_PERI_MSDC30_0>,
 679                          <&topckgen CLK_TOP_MSDC30_0_SEL>;
 680                 clock-names = "source", "hclk";
 681                 status = "disabled";
 682         };
 683
 684         mmc1: mmc@11240000 {
 685                 compatible = "mediatek,mt7623-mmc",
 686                              "mediatek,mt2701-mmc";
 687                 reg = <0 0x11240000 0 0x1000>;
 688                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
 689                 clocks = <&pericfg CLK_PERI_MSDC30_1>,
 690                          <&topckgen CLK_TOP_MSDC30_1_SEL>;
 691                 clock-names = "source", "hclk";
 692                 status = "disabled";
 693         };
 694
 695         hifsys: syscon@1a000000 {
 696                 compatible = "mediatek,mt7623-hifsys",
 697                              "mediatek,mt2701-hifsys",
 698                              "syscon";
 699                 reg = <0 0x1a000000 0 0x1000>;
 700                 #clock-cells = <1>;
 701                 #reset-cells = <1>;
 702         };
 703
 704         pcie: pcie@1a140000 {
 705                 compatible = "mediatek,mt7623-pcie";
 706                 device_type = "pci";
 707                 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
 708                       <0 0x1a142000 0 0x1000>, /* Port0 registers */
 709                       <0 0x1a143000 0 0x1000>, /* Port1 registers */
 710                       <0 0x1a144000 0 0x1000>; /* Port2 registers */
 711                 reg-names = "subsys", "port0", "port1", "port2";
 712                 #address-cells = <3>;
 713                 #size-cells = <2>;
 714                 #interrupt-cells = <1>;
 715                 interrupt-map-mask = <0xf800 0 0 0>;
 716                 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
 717                                 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
 718                                 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
 719                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 720                          <&hifsys CLK_HIFSYS_PCIE0>,
 721                          <&hifsys CLK_HIFSYS_PCIE1>,
 722                          <&hifsys CLK_HIFSYS_PCIE2>;
 723                 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
 724                 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
 725                          <&hifsys MT2701_HIFSYS_PCIE1_RST>,
 726                          <&hifsys MT2701_HIFSYS_PCIE2_RST>;
 727                 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
 728                 phys = <&pcie0_port PHY_TYPE_PCIE>,
 729                        <&pcie1_port PHY_TYPE_PCIE>,
 730                        <&u3port1 PHY_TYPE_PCIE>;
 731                 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
 732                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 733                 bus-range = <0x00 0xff>;
 734                 status = "disabled";
 735                 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
 736                           0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
 737
 738                 pcie@0,0 {
 739                         reg = <0x0000 0 0 0 0>;
 740                         #address-cells = <3>;
 741                         #size-cells = <2>;
 742                         #interrupt-cells = <1>;
 743                         interrupt-map-mask = <0 0 0 0>;
 744                         interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
 745                         ranges;
 746                         num-lanes = <1>;
 747                         status = "disabled";
 748                 };
 749
 750                 pcie@1,0 {
 751                         reg = <0x0800 0 0 0 0>;
 752                         #address-cells = <3>;
 753                         #size-cells = <2>;
 754                         #interrupt-cells = <1>;
 755                         interrupt-map-mask = <0 0 0 0>;
 756                         interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
 757                         ranges;
 758                         num-lanes = <1>;
 759                         status = "disabled";
 760                 };
 761
 762                 pcie@2,0 {
 763                         reg = <0x1000 0 0 0 0>;
 764                         #address-cells = <3>;
 765                         #size-cells = <2>;
 766                         #interrupt-cells = <1>;
 767                         interrupt-map-mask = <0 0 0 0>;
 768                         interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
 769                         ranges;
 770                         num-lanes = <1>;
 771                         status = "disabled";
 772                 };
 773         };
 774
 775         pcie0_phy: pcie-phy@1a149000 {
 776                 compatible = "mediatek,generic-tphy-v1";
 777                 reg = <0 0x1a149000 0 0x0700>;
 778                 #address-cells = <2>;
 779                 #size-cells = <2>;
 780                 ranges;
 781                 status = "disabled";
 782
 783                 pcie0_port: pcie-phy@1a149900 {
 784                         reg = <0 0x1a149900 0 0x0700>;
 785                         clocks = <&clk26m>;
 786                         clock-names = "ref";
 787                         #phy-cells = <1>;
 788                         status = "okay";
 789                 };
 790         };
 791
 792         pcie1_phy: pcie-phy@1a14a000 {
 793                 compatible = "mediatek,generic-tphy-v1";
 794                 reg = <0 0x1a14a000 0 0x0700>;
 795                 #address-cells = <2>;
 796                 #size-cells = <2>;
 797                 ranges;
 798                 status = "disabled";
 799
 800                 pcie1_port: pcie-phy@1a14a900 {
 801                         reg = <0 0x1a14a900 0 0x0700>;
 802                         clocks = <&clk26m>;
 803                         clock-names = "ref";
 804                         #phy-cells = <1>;
 805                         status = "okay";
 806                 };
 807         };
 808
 809         usb1: usb@1a1c0000 {
 810                 compatible = "mediatek,mt7623-xhci",
 811                              "mediatek,mt8173-xhci";
 812                 reg = <0 0x1a1c0000 0 0x1000>,
 813                       <0 0x1a1c4700 0 0x0100>;
 814                 reg-names = "mac", "ippc";
 815                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
 816                 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
 817                          <&topckgen CLK_TOP_ETHIF_SEL>;
 818                 clock-names = "sys_ck", "ref_ck";
 819                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 820                 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
 821                 status = "disabled";
 822         };
 823
 824         u3phy1: usb-phy@1a1c4000 {
 825                 compatible = "mediatek,mt7623-u3phy",
 826                              "mediatek,mt2701-u3phy";
 827                 reg = <0 0x1a1c4000 0 0x0700>;
 828                 #address-cells = <2>;
 829                 #size-cells = <2>;
 830                 ranges;
 831                 status = "disabled";
 832
 833                 u2port0: usb-phy@1a1c4800 {
 834                         reg = <0 0x1a1c4800 0 0x0100>;
 835                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 836                         clock-names = "ref";
 837                         #phy-cells = <1>;
 838                         status = "okay";
 839                 };
 840
 841                 u3port0: usb-phy@1a1c4900 {
 842                         reg = <0 0x1a1c4900 0 0x0700>;
 843                         clocks = <&clk26m>;
 844                         clock-names = "ref";
 845                         #phy-cells = <1>;
 846                         status = "okay";
 847                 };
 848         };
 849
 850         usb2: usb@1a240000 {
 851                 compatible = "mediatek,mt7623-xhci",
 852                              "mediatek,mt8173-xhci";
 853                 reg = <0 0x1a240000 0 0x1000>,
 854                       <0 0x1a244700 0 0x0100>;
 855                 reg-names = "mac", "ippc";
 856                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
 857                 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
 858                          <&topckgen CLK_TOP_ETHIF_SEL>;
 859                 clock-names = "sys_ck", "ref_ck";
 860                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 861                 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
 862                 status = "disabled";
 863         };
 864
 865         u3phy2: usb-phy@1a244000 {
 866                 compatible = "mediatek,mt7623-u3phy",
 867                              "mediatek,mt2701-u3phy";
 868                 reg = <0 0x1a244000 0 0x0700>;
 869                 #address-cells = <2>;
 870                 #size-cells = <2>;
 871                 ranges;
 872                 status = "disabled";
 873
 874                 u2port1: usb-phy@1a244800 {
 875                         reg = <0 0x1a244800 0 0x0100>;
 876                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 877                         clock-names = "ref";
 878                         #phy-cells = <1>;
 879                         status = "okay";
 880                 };
 881
 882                 u3port1: usb-phy@1a244900 {
 883                         reg = <0 0x1a244900 0 0x0700>;
 884                         clocks = <&clk26m>;
 885                         clock-names = "ref";
 886                         #phy-cells = <1>;
 887                         status = "okay";
 888                 };
 889         };
 890
 891         ethsys: syscon@1b000000 {
 892                 compatible = "mediatek,mt7623-ethsys",
 893                              "mediatek,mt2701-ethsys",
 894                              "syscon";
 895                 reg = <0 0x1b000000 0 0x1000>;
 896                 #clock-cells = <1>;
 897                 #reset-cells = <1>;
 898         };
 899
 900         hsdma: dma-controller@1b007000 {
 901                 compatible = "mediatek,mt7623-hsdma";
 902                 reg = <0 0x1b007000 0 0x1000>;
 903                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
 904                 clocks = <&ethsys CLK_ETHSYS_HSDMA>;
 905                 clock-names = "hsdma";
 906                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 907                 #dma-cells = <1>;
 908         };
 909
 910         eth: ethernet@1b100000 {
 911                 compatible = "mediatek,mt7623-eth",
 912                              "mediatek,mt2701-eth",
 913                              "syscon";
 914                 reg = <0 0x1b100000 0 0x20000>;
 915                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
 916                              <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
 917                              <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
 918                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 919                          <&ethsys CLK_ETHSYS_ESW>,
 920                          <&ethsys CLK_ETHSYS_GP1>,
 921                          <&ethsys CLK_ETHSYS_GP2>,
 922                          <&apmixedsys CLK_APMIXED_TRGPLL>;
 923                 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
 924                 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
 925                          <&ethsys MT2701_ETHSYS_GMAC_RST>,
 926                          <&ethsys MT2701_ETHSYS_PPE_RST>;
 927                 reset-names = "fe", "gmac", "ppe";
 928                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 929                 mediatek,ethsys = <&ethsys>;
 930                 mediatek,pctl = <&syscfg_pctl_a>;
 931                 #address-cells = <1>;
 932                 #size-cells = <0>;
 933                 status = "disabled";
 934         };
 935
 936         crypto: crypto@1b240000 {
 937                 compatible = "mediatek,eip97-crypto";
 938                 reg = <0 0x1b240000 0 0x20000>;
 939                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
 940                              <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
 941                              <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
 942                              <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
 943                              <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
 944                 clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
 945                 clock-names = "cryp";
 946                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 947                 status = "disabled";
 948         };
 949 };
 950
 951 &pio {
 952         cir_pins_a:cir-default {
 953                 pins-cir {
 954                         pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
 955                         bias-disable;
 956                 };
 957         };
 958
 959         i2c0_pins_a: i2c0-default {
 960                 pins-i2c0 {
 961                         pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
 962                                  <MT7623_PIN_76_SCL0_FUNC_SCL0>;
 963                         bias-disable;
 964                 };
 965         };
 966
 967         i2c1_pins_a: i2c1-default {
 968                 pin-i2c1 {
 969                         pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
 970                                  <MT7623_PIN_58_SCL1_FUNC_SCL1>;
 971                         bias-disable;
 972                 };
 973         };
 974
 975         i2c1_pins_b: i2c1-alt {
 976                 pin-i2c1 {
 977                         pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>,
 978                                  <MT7623_PIN_243_UCTS2_FUNC_SDA1>;
 979                         bias-disable;
 980                 };
 981         };
 982
 983         i2c2_pins_a: i2c2-default {
 984                 pin-i2c2 {
 985                         pinmux = <MT7623_PIN_77_SDA2_FUNC_SDA2>,
 986                                  <MT7623_PIN_78_SCL2_FUNC_SCL2>;
 987                         bias-disable;
 988                 };
 989         };
 990
 991         i2c2_pins_b: i2c2-alt {
 992                 pin-i2c2 {
 993                         pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>,
 994                                  <MT7623_PIN_123_HTPLG_FUNC_SCL2>;
 995                         bias-disable;
 996                 };
 997         };
 998
 999         i2s0_pins_a: i2s0-default {
1000                 pin-i2s0 {
1001                         pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
1002                                  <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
1003                                  <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
1004                                  <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
1005                                  <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
1006                         drive-strength = <MTK_DRIVE_12mA>;
1007                         bias-pull-down;
1008                 };
1009         };
1010
1011         i2s1_pins_a: i2s1-default {
1012                 pin-i2s1 {
1013                         pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
1014                                  <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
1015                                  <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
1016                                  <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
1017                                  <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
1018                         drive-strength = <MTK_DRIVE_12mA>;
1019                         bias-pull-down;
1020                 };
1021         };
1022
1023         key_pins_a: keys-alt {
1024                 pins-keys {
1025                         pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
1026                                  <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
1027                         input-enable;
1028                 };
1029         };
1030
1031         led_pins_a: leds-alt {
1032                 pins-leds {
1033                         pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
1034                                  <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
1035                                  <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
1036                 };
1037         };
1038
1039         mmc0_pins_default: mmc0default {
1040                 pins-cmd-dat {
1041                         pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1042                                  <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1043                                  <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1044                                  <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1045                                  <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1046                                  <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1047                                  <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1048                                  <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1049                                  <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1050                         input-enable;
1051                         bias-pull-up;
1052                 };
1053
1054                 pins-clk {
1055                         pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1056                         bias-pull-down;
1057                 };
1058
1059                 pins-rst {
1060                         pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1061                         bias-pull-up;
1062                 };
1063         };
1064
1065         mmc0_pins_uhs: mmc0 {
1066                 pins-cmd-dat {
1067                         pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1068                                  <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1069                                  <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1070                                  <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1071                                  <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1072                                  <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1073                                  <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1074                                  <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1075                                  <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1076                         input-enable;
1077                         drive-strength = <MTK_DRIVE_2mA>;
1078                         bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1079                 };
1080
1081                 pins-clk {
1082                         pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1083                         drive-strength = <MTK_DRIVE_2mA>;
1084                         bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1085                 };
1086
1087                 pins-rst {
1088                         pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1089                         bias-pull-up;
1090                 };
1091         };
1092
1093         mmc1_pins_default: mmc1default {
1094                 pins-cmd-dat {
1095                         pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1096                                  <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1097                                  <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1098                                  <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1099                                  <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1100                         input-enable;
1101                         drive-strength = <MTK_DRIVE_4mA>;
1102                         bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1103                 };
1104
1105                 pins-clk {
1106                         pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1107                         bias-pull-down;
1108                         drive-strength = <MTK_DRIVE_4mA>;
1109                 };
1110
1111                 pins-wp {
1112                         pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
1113                         input-enable;
1114                         bias-pull-up;
1115                 };
1116
1117                 pins-insert {
1118                         pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
1119                         bias-pull-up;
1120                 };
1121         };
1122
1123         mmc1_pins_uhs: mmc1 {
1124                 pins-cmd-dat {
1125                         pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1126                                  <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1127                                  <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1128                                  <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1129                                  <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1130                         input-enable;
1131                         drive-strength = <MTK_DRIVE_4mA>;
1132                         bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1133                 };
1134
1135                 pins-clk {
1136                         pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1137                         drive-strength = <MTK_DRIVE_4mA>;
1138                         bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1139                 };
1140         };
1141
1142         nand_pins_default: nanddefault {
1143                 pins-ale {
1144                         pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
1145                         drive-strength = <MTK_DRIVE_8mA>;
1146                         bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1147                 };
1148
1149                 pins-dat {
1150                         pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
1151                                  <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
1152                                  <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
1153                                  <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
1154                                  <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
1155                                  <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
1156                                  <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
1157                                  <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
1158                                  <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
1159                         input-enable;
1160                         drive-strength = <MTK_DRIVE_8mA>;
1161                         bias-pull-up;
1162                 };
1163
1164                 pins-we {
1165                         pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
1166                         drive-strength = <MTK_DRIVE_8mA>;
1167                         bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1168                 };
1169         };
1170
1171         pcie_default: pcie_pin_default {
1172                 pins_cmd_dat {
1173                         pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
1174                                  <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
1175                         bias-disable;
1176                 };
1177         };
1178
1179         pwm_pins_a: pwm-default {
1180                 pins-pwm {
1181                         pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
1182                                  <MT7623_PIN_204_PWM1_FUNC_PWM1>,
1183                                  <MT7623_PIN_205_PWM2_FUNC_PWM2>,
1184                                  <MT7623_PIN_206_PWM3_FUNC_PWM3>,
1185                                  <MT7623_PIN_207_PWM4_FUNC_PWM4>;
1186                 };
1187         };
1188
1189         spi0_pins_a: spi0-default {
1190                 pins-spi {
1191                         pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
1192                                 <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
1193                                 <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
1194                                 <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
1195                         bias-disable;
1196                 };
1197         };
1198
1199         spi1_pins_a: spi1-default {
1200                 pins-spi {
1201                         pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>,
1202                                 <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>,
1203                                 <MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>,
1204                                 <MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>;
1205                 };
1206         };
1207
1208         spi2_pins_a: spi2-default {
1209                 pins-spi {
1210                         pinmux = <MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS>,
1211                                  <MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK>,
1212                                  <MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI>,
1213                                  <MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO>;
1214                 };
1215         };
1216
1217         uart0_pins_a: uart0-default {
1218                 pins-dat {
1219                         pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
1220                                  <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
1221                 };
1222         };
1223
1224         uart1_pins_a: uart1-default {
1225                 pins-dat {
1226                         pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
1227                                  <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
1228                 };
1229         };
1230
1231         uart2_pins_a: uart2-default {
1232                 pins-dat {
1233                         pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
1234                                  <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
1235                 };
1236         };
1237
1238         uart2_pins_b: uart2-alt {
1239                 pins-dat {
1240                         pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
1241                                  <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
1242                 };
1243         };
1244 };