arch/arm/boot/dts/mt7623.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: John Crispin <john@phrozen.org>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18 #include <dt-bindings/clock/mt2701-clk.h>
  19 #include <dt-bindings/pinctrl/mt7623-pinfunc.h>
  20 #include <dt-bindings/power/mt2701-power.h>
  21 #include <dt-bindings/gpio/gpio.h>
  22 #include <dt-bindings/phy/phy.h>
  23 #include <dt-bindings/reset/mt2701-resets.h>
  24 #include <dt-bindings/thermal/thermal.h>
  25 #include "skeleton64.dtsi"
  26
  27 / {
  28         compatible = "mediatek,mt7623";
  29         interrupt-parent = <&sysirq>;
  30
  31         cpu_opp_table: opp_table {
  32                 compatible = "operating-points-v2";
  33                 opp-shared;
  34
  35                 opp-98000000 {
  36                         opp-hz = /bits/ 64 <98000000>;
  37                         opp-microvolt = <1050000>;
  38                 };
  39
  40                 opp-198000000 {
  41                         opp-hz = /bits/ 64 <198000000>;
  42                         opp-microvolt = <1050000>;
  43                 };
  44
  45                 opp-398000000 {
  46                         opp-hz = /bits/ 64 <398000000>;
  47                         opp-microvolt = <1050000>;
  48                 };
  49
  50                 opp-598000000 {
  51                         opp-hz = /bits/ 64 <598000000>;
  52                         opp-microvolt = <1050000>;
  53                 };
  54
  55                 opp-747500000 {
  56                         opp-hz = /bits/ 64 <747500000>;
  57                         opp-microvolt = <1050000>;
  58                 };
  59
  60                 opp-1040000000 {
  61                         opp-hz = /bits/ 64 <1040000000>;
  62                         opp-microvolt = <1150000>;
  63                 };
  64
  65                 opp-1196000000 {
  66                         opp-hz = /bits/ 64 <1196000000>;
  67                         opp-microvolt = <1200000>;
  68                 };
  69
  70                 opp-1300000000 {
  71                         opp-hz = /bits/ 64 <1300000000>;
  72                         opp-microvolt = <1300000>;
  73                 };
  74         };
  75
  76         cpus {
  77                 #address-cells = <1>;
  78                 #size-cells = <0>;
  79                 enable-method = "mediatek,mt6589-smp";
  80
  81                 cpu0: cpu@0 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a7";
  84                         reg = <0x0>;
  85                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
  86                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
  87                         clock-names = "cpu", "intermediate";
  88                         operating-points-v2 = <&cpu_opp_table>;
  89                         #cooling-cells = <2>;
  90                         cooling-min-level = <0>;
  91                         cooling-max-level = <7>;
  92                         clock-frequency = <1300000000>;
  93                 };
  94
  95                 cpu1: cpu@1 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a7";
  98                         reg = <0x1>;
  99                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
 100                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 101                         clock-names = "cpu", "intermediate";
 102                         operating-points-v2 = <&cpu_opp_table>;
 103                         clock-frequency = <1300000000>;
 104                 };
 105
 106                 cpu2: cpu@2 {
 107                         device_type = "cpu";
 108                         compatible = "arm,cortex-a7";
 109                         reg = <0x2>;
 110                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
 111                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 112                         clock-names = "cpu", "intermediate";
 113                         operating-points-v2 = <&cpu_opp_table>;
 114                         clock-frequency = <1300000000>;
 115                 };
 116
 117                 cpu3: cpu@3 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a7";
 120                         reg = <0x3>;
 121                         clocks = <&infracfg CLK_INFRA_CPUSEL>,
 122                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 123                         clock-names = "cpu", "intermediate";
 124                         operating-points-v2 = <&cpu_opp_table>;
 125                         clock-frequency = <1300000000>;
 126                 };
 127         };
 128
 129         system_clk: dummy13m {
 130                 compatible = "fixed-clock";
 131                 clock-frequency = <13000000>;
 132                 #clock-cells = <0>;
 133         };
 134
 135         rtc32k: oscillator@1 {
 136                 compatible = "fixed-clock";
 137                 #clock-cells = <0>;
 138                 clock-frequency = <32000>;
 139                 clock-output-names = "rtc32k";
 140         };
 141
 142         clk26m: oscillator@0 {
 143                 compatible = "fixed-clock";
 144                 #clock-cells = <0>;
 145                 clock-frequency = <26000000>;
 146                 clock-output-names = "clk26m";
 147         };
 148
 149         thermal-zones {
 150                         cpu_thermal: cpu_thermal {
 151                                 polling-delay-passive = <1000>;
 152                                 polling-delay = <1000>;
 153
 154                                 thermal-sensors = <&thermal 0>;
 155
 156                                 trips {
 157                                         cpu_passive: cpu_passive {
 158                                                 temperature = <47000>;
 159                                                 hysteresis = <2000>;
 160                                                 type = "passive";
 161                                         };
 162
 163                                         cpu_active: cpu_active {
 164                                                 temperature = <67000>;
 165                                                 hysteresis = <2000>;
 166                                                 type = "active";
 167                                         };
 168
 169                                         cpu_hot: cpu_hot {
 170                                                 temperature = <87000>;
 171                                                 hysteresis = <2000>;
 172                                                 type = "hot";
 173                                         };
 174
 175                                         cpu_crit {
 176                                                 temperature = <107000>;
 177                                                 hysteresis = <2000>;
 178                                                 type = "critical";
 179                                         };
 180                                 };
 181
 182                         cooling-maps {
 183                                 map0 {
 184                                         trip = <&cpu_passive>;
 185                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 186                                 };
 187
 188                                 map1 {
 189                                         trip = <&cpu_active>;
 190                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 191                                 };
 192
 193                                 map2 {
 194                                         trip = <&cpu_hot>;
 195                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 196                                 };
 197                         };
 198                 };
 199         };
 200
 201         timer {
 202                 compatible = "arm,armv7-timer";
 203                 interrupt-parent = <&gic>;
 204                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 205                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 206                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 207                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 208                 clock-frequency = <13000000>;
 209                 arm,cpu-registers-not-fw-configured;
 210         };
 211
 212         topckgen: syscon@10000000 {
 213                 compatible = "mediatek,mt7623-topckgen",
 214                              "mediatek,mt2701-topckgen",
 215                              "syscon";
 216                 reg = <0 0x10000000 0 0x1000>;
 217                 #clock-cells = <1>;
 218         };
 219
 220         infracfg: syscon@10001000 {
 221                 compatible = "mediatek,mt7623-infracfg",
 222                              "mediatek,mt2701-infracfg",
 223                              "syscon";
 224                 reg = <0 0x10001000 0 0x1000>;
 225                 #clock-cells = <1>;
 226                 #reset-cells = <1>;
 227         };
 228
 229         pericfg: syscon@10003000 {
 230                 compatible =  "mediatek,mt7623-pericfg",
 231                               "mediatek,mt2701-pericfg",
 232                               "syscon";
 233                 reg = <0 0x10003000 0 0x1000>;
 234                 #clock-cells = <1>;
 235                 #reset-cells = <1>;
 236         };
 237
 238         pio: pinctrl@10005000 {
 239                 compatible = "mediatek,mt7623-pinctrl";
 240                 reg = <0 0x1000b000 0 0x1000>;
 241                 mediatek,pctl-regmap = <&syscfg_pctl_a>;
 242                 pins-are-numbered;
 243                 gpio-controller;
 244                 #gpio-cells = <2>;
 245                 interrupt-controller;
 246                 interrupt-parent = <&gic>;
 247                 #interrupt-cells = <2>;
 248                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 249                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 250         };
 251
 252         syscfg_pctl_a: syscfg@10005000 {
 253                 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
 254                 reg = <0 0x10005000 0 0x1000>;
 255         };
 256
 257         scpsys: scpsys@10006000 {
 258                 compatible = "mediatek,mt7623-scpsys",
 259                              "mediatek,mt2701-scpsys",
 260                              "syscon";
 261                 #power-domain-cells = <1>;
 262                 reg = <0 0x10006000 0 0x1000>;
 263                 infracfg = <&infracfg>;
 264                 clocks = <&topckgen CLK_TOP_MM_SEL>,
 265                          <&topckgen CLK_TOP_MFG_SEL>,
 266                          <&topckgen CLK_TOP_ETHIF_SEL>;
 267                 clock-names = "mm", "mfg", "ethif";
 268         };
 269
 270         watchdog: watchdog@10007000 {
 271                 compatible = "mediatek,mt7623-wdt",
 272                              "mediatek,mt6589-wdt";
 273                 reg = <0 0x10007000 0 0x100>;
 274         };
 275
 276         timer: timer@10008000 {
 277                 compatible = "mediatek,mt7623-timer",
 278                              "mediatek,mt6577-timer";
 279                 reg = <0 0x10008000 0 0x80>;
 280                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
 281                 clocks = <&system_clk>, <&rtc32k>;
 282                 clock-names = "system-clk", "rtc-clk";
 283         };
 284
 285         pwrap: pwrap@1000d000 {
 286                 compatible = "mediatek,mt7623-pwrap",
 287                              "mediatek,mt2701-pwrap";
 288                 reg = <0 0x1000d000 0 0x1000>;
 289                 reg-names = "pwrap";
 290                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 291                 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
 292                 reset-names = "pwrap";
 293                 clocks = <&infracfg CLK_INFRA_PMICSPI>,
 294                          <&infracfg CLK_INFRA_PMICWRAP>;
 295                 clock-names = "spi", "wrap";
 296         };
 297
 298         cir: cir@10013000 {
 299                 compatible = "mediatek,mt7623-cir";
 300                 reg = <0 0x10013000 0 0x1000>;
 301                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
 302                 clocks = <&infracfg CLK_INFRA_IRRX>;
 303                 clock-names = "clk";
 304                 status = "disabled";
 305         };
 306
 307         sysirq: interrupt-controller@10200100 {
 308                 compatible = "mediatek,mt7623-sysirq",
 309                              "mediatek,mt6577-sysirq";
 310                 interrupt-controller;
 311                 #interrupt-cells = <3>;
 312                 interrupt-parent = <&gic>;
 313                 reg = <0 0x10200100 0 0x1c>;
 314         };
 315
 316         efuse: efuse@10206000 {
 317                 compatible = "mediatek,mt7623-efuse",
 318                              "mediatek,mt8173-efuse";
 319                 reg = <0 0x10206000 0 0x1000>;
 320                 #address-cells = <1>;
 321                 #size-cells = <1>;
 322                 thermal_calibration_data: calib@424 {
 323                         reg = <0x424 0xc>;
 324                 };
 325         };
 326
 327         apmixedsys: syscon@10209000 {
 328                 compatible = "mediatek,mt7623-apmixedsys",
 329                              "mediatek,mt2701-apmixedsys",
 330                              "syscon";
 331                 reg = <0 0x10209000 0 0x1000>;
 332                 #clock-cells = <1>;
 333         };
 334
 335         rng: rng@1020f000 {
 336                 compatible = "mediatek,mt7623-rng";
 337                 reg = <0 0x1020f000 0 0x1000>;
 338                 clocks = <&infracfg CLK_INFRA_TRNG>;
 339                 clock-names = "rng";
 340         };
 341
 342         gic: interrupt-controller@10211000 {
 343                 compatible = "arm,cortex-a7-gic";
 344                 interrupt-controller;
 345                 #interrupt-cells = <3>;
 346                 interrupt-parent = <&gic>;
 347                 reg = <0 0x10211000 0 0x1000>,
 348                       <0 0x10212000 0 0x2000>,
 349                       <0 0x10214000 0 0x2000>,
 350                       <0 0x10216000 0 0x2000>;
 351         };
 352
 353         auxadc: adc@11001000 {
 354                 compatible = "mediatek,mt7623-auxadc",
 355                              "mediatek,mt2701-auxadc";
 356                 reg = <0 0x11001000 0 0x1000>;
 357                 clocks = <&pericfg CLK_PERI_AUXADC>;
 358                 clock-names = "main";
 359                 #io-channel-cells = <1>;
 360         };
 361
 362         uart0: serial@11002000 {
 363                 compatible = "mediatek,mt7623-uart",
 364                              "mediatek,mt6577-uart";
 365                 reg = <0 0x11002000 0 0x400>;
 366                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
 367                 clocks = <&pericfg CLK_PERI_UART0_SEL>,
 368                          <&pericfg CLK_PERI_UART0>;
 369                 clock-names = "baud", "bus";
 370                 status = "disabled";
 371         };
 372
 373         uart1: serial@11003000 {
 374                 compatible = "mediatek,mt7623-uart",
 375                              "mediatek,mt6577-uart";
 376                 reg = <0 0x11003000 0 0x400>;
 377                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
 378                 clocks = <&pericfg CLK_PERI_UART1_SEL>,
 379                          <&pericfg CLK_PERI_UART1>;
 380                 clock-names = "baud", "bus";
 381                 status = "disabled";
 382         };
 383
 384         uart2: serial@11004000 {
 385                 compatible = "mediatek,mt7623-uart",
 386                              "mediatek,mt6577-uart";
 387                 reg = <0 0x11004000 0 0x400>;
 388                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
 389                 clocks = <&pericfg CLK_PERI_UART2_SEL>,
 390                          <&pericfg CLK_PERI_UART2>;
 391                 clock-names = "baud", "bus";
 392                 status = "disabled";
 393         };
 394
 395         uart3: serial@11005000 {
 396                 compatible = "mediatek,mt7623-uart",
 397                              "mediatek,mt6577-uart";
 398                 reg = <0 0x11005000 0 0x400>;
 399                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
 400                 clocks = <&pericfg CLK_PERI_UART3_SEL>,
 401                          <&pericfg CLK_PERI_UART3>;
 402                 clock-names = "baud", "bus";
 403                 status = "disabled";
 404         };
 405
 406         pwm: pwm@11006000 {
 407                 compatible = "mediatek,mt7623-pwm";
 408                 reg = <0 0x11006000 0 0x1000>;
 409                 #pwm-cells = <2>;
 410                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 411                          <&pericfg CLK_PERI_PWM>,
 412                          <&pericfg CLK_PERI_PWM1>,
 413                          <&pericfg CLK_PERI_PWM2>,
 414                          <&pericfg CLK_PERI_PWM3>,
 415                          <&pericfg CLK_PERI_PWM4>,
 416                          <&pericfg CLK_PERI_PWM5>;
 417                 clock-names = "top", "main", "pwm1", "pwm2",
 418                               "pwm3", "pwm4", "pwm5";
 419                 status = "disabled";
 420         };
 421
 422         i2c0: i2c@11007000 {
 423                 compatible = "mediatek,mt7623-i2c",
 424                              "mediatek,mt6577-i2c";
 425                 reg = <0 0x11007000 0 0x70>,
 426                       <0 0x11000200 0 0x80>;
 427                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
 428                 clock-div = <16>;
 429                 clocks = <&pericfg CLK_PERI_I2C0>,
 430                          <&pericfg CLK_PERI_AP_DMA>;
 431                 clock-names = "main", "dma";
 432                 #address-cells = <1>;
 433                 #size-cells = <0>;
 434                 status = "disabled";
 435         };
 436
 437         i2c1: i2c@11008000 {
 438                 compatible = "mediatek,mt7623-i2c",
 439                              "mediatek,mt6577-i2c";
 440                 reg = <0 0x11008000 0 0x70>,
 441                       <0 0x11000280 0 0x80>;
 442                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
 443                 clock-div = <16>;
 444                 clocks = <&pericfg CLK_PERI_I2C1>,
 445                          <&pericfg CLK_PERI_AP_DMA>;
 446                 clock-names = "main", "dma";
 447                 #address-cells = <1>;
 448                 #size-cells = <0>;
 449                 status = "disabled";
 450         };
 451
 452         i2c2: i2c@11009000 {
 453                 compatible = "mediatek,mt7623-i2c",
 454                              "mediatek,mt6577-i2c";
 455                 reg = <0 0x11009000 0 0x70>,
 456                       <0 0x11000300 0 0x80>;
 457                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
 458                 clock-div = <16>;
 459                 clocks = <&pericfg CLK_PERI_I2C2>,
 460                          <&pericfg CLK_PERI_AP_DMA>;
 461                 clock-names = "main", "dma";
 462                 #address-cells = <1>;
 463                 #size-cells = <0>;
 464                 status = "disabled";
 465         };
 466
 467         spi0: spi@1100a000 {
 468                 compatible = "mediatek,mt7623-spi",
 469                              "mediatek,mt2701-spi";
 470                 #address-cells = <1>;
 471                 #size-cells = <0>;
 472                 reg = <0 0x1100a000 0 0x100>;
 473                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 474                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 475                          <&topckgen CLK_TOP_SPI0_SEL>,
 476                          <&pericfg CLK_PERI_SPI0>;
 477                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 478                 status = "disabled";
 479         };
 480
 481         thermal: thermal@1100b000 {
 482                 #thermal-sensor-cells = <1>;
 483                 compatible = "mediatek,mt7623-thermal",
 484                              "mediatek,mt2701-thermal";
 485                 reg = <0 0x1100b000 0 0x1000>;
 486                 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 487                 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 488                 clock-names = "therm", "auxadc";
 489                 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
 490                 reset-names = "therm";
 491                 mediatek,auxadc = <&auxadc>;
 492                 mediatek,apmixedsys = <&apmixedsys>;
 493                 nvmem-cells = <&thermal_calibration_data>;
 494                 nvmem-cell-names = "calibration-data";
 495         };
 496
 497         nandc: nfi@1100d000 {
 498                 compatible = "mediatek,mt7623-nfc",
 499                              "mediatek,mt2701-nfc";
 500                 reg = <0 0x1100d000 0 0x1000>;
 501                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
 502                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 503                 clocks = <&pericfg CLK_PERI_NFI>,
 504                          <&pericfg CLK_PERI_NFI_PAD>;
 505                 clock-names = "nfi_clk", "pad_clk";
 506                 status = "disabled";
 507                 ecc-engine = <&bch>;
 508                 #address-cells = <1>;
 509                 #size-cells = <0>;
 510         };
 511
 512         bch: ecc@1100e000 {
 513                 compatible = "mediatek,mt7623-ecc",
 514                              "mediatek,mt2701-ecc";
 515                 reg = <0 0x1100e000 0 0x1000>;
 516                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 517                 clocks = <&pericfg CLK_PERI_NFI_ECC>;
 518                 clock-names = "nfiecc_clk";
 519                 status = "disabled";
 520         };
 521
 522         spi1: spi@11016000 {
 523                 compatible = "mediatek,mt7623-spi",
 524                              "mediatek,mt2701-spi";
 525                 #address-cells = <1>;
 526                 #size-cells = <0>;
 527                 reg = <0 0x11016000 0 0x100>;
 528                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 529                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 530                          <&topckgen CLK_TOP_SPI1_SEL>,
 531                          <&pericfg CLK_PERI_SPI1>;
 532                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 533                 status = "disabled";
 534         };
 535
 536         spi2: spi@11017000 {
 537                 compatible = "mediatek,mt7623-spi",
 538                              "mediatek,mt2701-spi";
 539                 #address-cells = <1>;
 540                 #size-cells = <0>;
 541                 reg = <0 0x11017000 0 0x1000>;
 542                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
 543                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 544                          <&topckgen CLK_TOP_SPI2_SEL>,
 545                          <&pericfg CLK_PERI_SPI2>;
 546                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 547                 status = "disabled";
 548         };
 549
 550         afe: audio-controller@11220000 {
 551                 compatible = "mediatek,mt7623-audio",
 552                              "mediatek,mt2701-audio";
 553                 reg = <0 0x11220000 0 0x2000>,
 554                       <0 0x112a0000 0 0x20000>;
 555                 interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
 556                               <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 557                 interrupt-names = "afe", "asys";
 558                 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 559
 560                 clocks = <&infracfg CLK_INFRA_AUDIO>,
 561                          <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 562                          <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 563                          <&topckgen CLK_TOP_AUD_MUX1_DIV>,
 564                          <&topckgen CLK_TOP_AUD_MUX2_DIV>,
 565                          <&topckgen CLK_TOP_AUD_48K_TIMING>,
 566                          <&topckgen CLK_TOP_AUD_44K_TIMING>,
 567                          <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
 568                          <&topckgen CLK_TOP_APLL_SEL>,
 569                          <&topckgen CLK_TOP_AUD1PLL_98M>,
 570                          <&topckgen CLK_TOP_AUD2PLL_90M>,
 571                          <&topckgen CLK_TOP_HADDS2PLL_98M>,
 572                          <&topckgen CLK_TOP_HADDS2PLL_294M>,
 573                          <&topckgen CLK_TOP_AUDPLL>,
 574                          <&topckgen CLK_TOP_AUDPLL_D4>,
 575                          <&topckgen CLK_TOP_AUDPLL_D8>,
 576                          <&topckgen CLK_TOP_AUDPLL_D16>,
 577                          <&topckgen CLK_TOP_AUDPLL_D24>,
 578                          <&topckgen CLK_TOP_AUDINTBUS_SEL>,
 579                          <&clk26m>,
 580                          <&topckgen CLK_TOP_SYSPLL1_D4>,
 581                          <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
 582                          <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
 583                          <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
 584                          <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
 585                          <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
 586                          <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
 587                          <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
 588                          <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
 589                          <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
 590                          <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
 591                          <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
 592                          <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
 593                          <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
 594                          <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
 595                          <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
 596                          <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
 597                          <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
 598                          <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
 599                          <&topckgen CLK_TOP_ASM_M_SEL>,
 600                          <&topckgen CLK_TOP_ASM_H_SEL>,
 601                          <&topckgen CLK_TOP_UNIVPLL2_D4>,
 602                          <&topckgen CLK_TOP_UNIVPLL2_D2>,
 603                          <&topckgen CLK_TOP_SYSPLL_D5>;
 604
 605                 clock-names = "infra_sys_audio_clk",
 606                          "top_audio_mux1_sel",
 607                          "top_audio_mux2_sel",
 608                          "top_audio_mux1_div",
 609                          "top_audio_mux2_div",
 610                          "top_audio_48k_timing",
 611                          "top_audio_44k_timing",
 612                          "top_audpll_mux_sel",
 613                          "top_apll_sel",
 614                          "top_aud1_pll_98M",
 615                          "top_aud2_pll_90M",
 616                          "top_hadds2_pll_98M",
 617                          "top_hadds2_pll_294M",
 618                          "top_audpll",
 619                          "top_audpll_d4",
 620                          "top_audpll_d8",
 621                          "top_audpll_d16",
 622                          "top_audpll_d24",
 623                          "top_audintbus_sel",
 624                          "clk_26m",
 625                          "top_syspll1_d4",
 626                          "top_aud_k1_src_sel",
 627                          "top_aud_k2_src_sel",
 628                          "top_aud_k3_src_sel",
 629                          "top_aud_k4_src_sel",
 630                          "top_aud_k5_src_sel",
 631                          "top_aud_k6_src_sel",
 632                          "top_aud_k1_src_div",
 633                          "top_aud_k2_src_div",
 634                          "top_aud_k3_src_div",
 635                          "top_aud_k4_src_div",
 636                          "top_aud_k5_src_div",
 637                          "top_aud_k6_src_div",
 638                          "top_aud_i2s1_mclk",
 639                          "top_aud_i2s2_mclk",
 640                          "top_aud_i2s3_mclk",
 641                          "top_aud_i2s4_mclk",
 642                          "top_aud_i2s5_mclk",
 643                          "top_aud_i2s6_mclk",
 644                          "top_asm_m_sel",
 645                          "top_asm_h_sel",
 646                          "top_univpll2_d4",
 647                          "top_univpll2_d2",
 648                          "top_syspll_d5";
 649         };
 650
 651         mmc0: mmc@11230000 {
 652                 compatible = "mediatek,mt7623-mmc",
 653                              "mediatek,mt2701-mmc";
 654                 reg = <0 0x11230000 0 0x1000>;
 655                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
 656                 clocks = <&pericfg CLK_PERI_MSDC30_0>,
 657                          <&topckgen CLK_TOP_MSDC30_0_SEL>;
 658                 clock-names = "source", "hclk";
 659                 status = "disabled";
 660         };
 661
 662         mmc1: mmc@11240000 {
 663                 compatible = "mediatek,mt7623-mmc",
 664                              "mediatek,mt2701-mmc";
 665                 reg = <0 0x11240000 0 0x1000>;
 666                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
 667                 clocks = <&pericfg CLK_PERI_MSDC30_1>,
 668                          <&topckgen CLK_TOP_MSDC30_1_SEL>;
 669                 clock-names = "source", "hclk";
 670                 status = "disabled";
 671         };
 672
 673         hifsys: syscon@1a000000 {
 674                 compatible = "mediatek,mt7623-hifsys",
 675                              "mediatek,mt2701-hifsys",
 676                              "syscon";
 677                 reg = <0 0x1a000000 0 0x1000>;
 678                 #clock-cells = <1>;
 679                 #reset-cells = <1>;
 680         };
 681
 682         usb1: usb@1a1c0000 {
 683                 compatible = "mediatek,mt7623-xhci",
 684                              "mediatek,mt8173-xhci";
 685                 reg = <0 0x1a1c0000 0 0x1000>,
 686                       <0 0x1a1c4700 0 0x0100>;
 687                 reg-names = "mac", "ippc";
 688                 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
 689                 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
 690                          <&topckgen CLK_TOP_ETHIF_SEL>;
 691                 clock-names = "sys_ck", "ref_ck";
 692                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 693                 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
 694                 status = "disabled";
 695         };
 696
 697         u3phy1: usb-phy@1a1c4000 {
 698                 compatible = "mediatek,mt7623-u3phy",
 699                              "mediatek,mt2701-u3phy";
 700                 reg = <0 0x1a1c4000 0 0x0700>;
 701                 #address-cells = <2>;
 702                 #size-cells = <2>;
 703                 ranges;
 704                 status = "disabled";
 705
 706                 u2port0: usb-phy@1a1c4800 {
 707                         reg = <0 0x1a1c4800 0 0x0100>;
 708                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 709                         clock-names = "ref";
 710                         #phy-cells = <1>;
 711                         status = "okay";
 712                 };
 713
 714                 u3port0: usb-phy@1a1c4900 {
 715                         reg = <0 0x1a1c4900 0 0x0700>;
 716                         clocks = <&clk26m>;
 717                         clock-names = "ref";
 718                         #phy-cells = <1>;
 719                         status = "okay";
 720                 };
 721         };
 722
 723         usb2: usb@1a240000 {
 724                 compatible = "mediatek,mt7623-xhci",
 725                              "mediatek,mt8173-xhci";
 726                 reg = <0 0x1a240000 0 0x1000>,
 727                       <0 0x1a244700 0 0x0100>;
 728                 reg-names = "mac", "ippc";
 729                 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
 730                 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
 731                          <&topckgen CLK_TOP_ETHIF_SEL>;
 732                 clock-names = "sys_ck", "ref_ck";
 733                 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
 734                 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
 735                 status = "disabled";
 736         };
 737
 738         u3phy2: usb-phy@1a244000 {
 739                 compatible = "mediatek,mt7623-u3phy",
 740                              "mediatek,mt2701-u3phy";
 741                 reg = <0 0x1a244000 0 0x0700>;
 742                 #address-cells = <2>;
 743                 #size-cells = <2>;
 744                 ranges;
 745                 status = "disabled";
 746
 747                 u2port1: usb-phy@1a244800 {
 748                         reg = <0 0x1a244800 0 0x0100>;
 749                         clocks = <&topckgen CLK_TOP_USB_PHY48M>;
 750                         clock-names = "ref";
 751                         #phy-cells = <1>;
 752                         status = "okay";
 753                 };
 754
 755                 u3port1: usb-phy@1a244900 {
 756                         reg = <0 0x1a244900 0 0x0700>;
 757                         clocks = <&clk26m>;
 758                         clock-names = "ref";
 759                         #phy-cells = <1>;
 760                         status = "okay";
 761                 };
 762         };
 763
 764         ethsys: syscon@1b000000 {
 765                 compatible = "mediatek,mt7623-ethsys",
 766                              "mediatek,mt2701-ethsys",
 767                              "syscon";
 768                 reg = <0 0x1b000000 0 0x1000>;
 769                 #clock-cells = <1>;
 770                 #reset-cells = <1>;
 771         };
 772
 773         eth: ethernet@1b100000 {
 774                 compatible = "mediatek,mt7623-eth",
 775                              "mediatek,mt2701-eth",
 776                              "syscon";
 777                 reg = <0 0x1b100000 0 0x20000>;
 778                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
 779                              <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
 780                              <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
 781                 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
 782                          <&ethsys CLK_ETHSYS_ESW>,
 783                          <&ethsys CLK_ETHSYS_GP1>,
 784                          <&ethsys CLK_ETHSYS_GP2>,
 785                          <&apmixedsys CLK_APMIXED_TRGPLL>;
 786                 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
 787                 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
 788                          <&ethsys MT2701_ETHSYS_GMAC_RST>,
 789                          <&ethsys MT2701_ETHSYS_PPE_RST>;
 790                 reset-names = "fe", "gmac", "ppe";
 791                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 792                 mediatek,ethsys = <&ethsys>;
 793                 mediatek,pctl = <&syscfg_pctl_a>;
 794                 #address-cells = <1>;
 795                 #size-cells = <0>;
 796                 status = "disabled";
 797         };
 798
 799         crypto: crypto@1b240000 {
 800                 compatible = "mediatek,eip97-crypto";
 801                 reg = <0 0x1b240000 0 0x20000>;
 802                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
 803                              <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
 804                              <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
 805                              <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
 806                              <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
 807                 clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
 808                 clock-names = "cryp";
 809                 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
 810                 status = "disabled";
 811         };
 812 };