1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2020 thingy.jp.
4 * Author: Daniel Palmer <daniel@thingy.jp>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/mstar-msc313-mpll.h>
14 interrupt-parent = <&gic>;
22 compatible = "arm,cortex-a7";
28 compatible = "arm,armv7-timer";
29 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
30 | IRQ_TYPE_LEVEL_LOW)>,
31 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
32 | IRQ_TYPE_LEVEL_LOW)>,
33 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
34 | IRQ_TYPE_LEVEL_LOW)>,
35 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
36 | IRQ_TYPE_LEVEL_LOW)>;
38 * we shouldn't need this but the vendor
41 clock-frequency = <6000000>;
45 compatible = "arm,cortex-a7-pmu";
46 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
47 interrupt-affinity = <&cpu0>;
53 compatible = "fixed-clock";
54 clock-frequency = <24000000>;
59 compatible = "fixed-clock";
60 clock-frequency = <32768>;
66 compatible = "simple-bus";
69 ranges = <0x16001000 0x16001000 0x00007000>,
70 <0x1f000000 0x1f000000 0x00400000>,
71 <0xa0000000 0xa0000000 0x20000>;
73 gic: interrupt-controller@16001000 {
74 compatible = "arm,cortex-a7-gic";
75 reg = <0x16001000 0x1000>,
79 #interrupt-cells = <3>;
81 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2)
82 | IRQ_TYPE_LEVEL_LOW)>;
86 compatible = "simple-bus";
87 reg = <0x1f000000 0x00400000>;
90 ranges = <0x0 0x1f000000 0x00400000>;
92 pmsleep: syscon@1c00 {
93 compatible = "mstar,msc313-pmsleep", "syscon";
98 compatible = "syscon-reboot";
104 intc_fiq: interrupt-controller@201310 {
105 compatible = "mstar,mst-intc";
106 reg = <0x201310 0x40>;
107 #interrupt-cells = <3>;
108 interrupt-controller;
109 interrupt-parent = <&gic>;
110 mstar,irqs-map-range = <96 127>;
113 intc_irq: interrupt-controller@201350 {
114 compatible = "mstar,mst-intc";
115 reg = <0x201350 0x40>;
116 #interrupt-cells = <3>;
117 interrupt-controller;
118 interrupt-parent = <&gic>;
119 mstar,irqs-map-range = <32 95>;
123 l3bridge: l3bridge@204400 {
124 compatible = "mstar,l3bridge";
125 reg = <0x204400 0x200>;
129 compatible = "mstar,msc313-mpll";
131 reg = <0x206000 0x200>;
137 reg = <0x207800 0x200>;
139 #interrupt-cells = <2>;
140 interrupt-controller;
141 interrupt-parent = <&intc_fiq>;
145 pm_uart: uart@221000 {
146 compatible = "ns16550a";
147 reg = <0x221000 0x100>;
149 interrupts-extended = <&intc_irq GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
150 clock-frequency = <172000000>;
156 compatible = "mmio-sram";
157 reg = <0xa0000000 0x10000>;