1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2020 thingy.jp.
4 * Author: Daniel Palmer <daniel@thingy.jp>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
21 compatible = "arm,cortex-a7";
27 compatible = "arm,armv7-timer";
28 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
29 | IRQ_TYPE_LEVEL_LOW)>,
30 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2)
31 | IRQ_TYPE_LEVEL_LOW)>,
32 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2)
33 | IRQ_TYPE_LEVEL_LOW)>,
34 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2)
35 | IRQ_TYPE_LEVEL_LOW)>;
37 * we shouldn't need this but the vendor
40 clock-frequency = <6000000>;
44 compatible = "arm,cortex-a7-pmu";
45 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
46 interrupt-affinity = <&cpu0>;
50 compatible = "simple-bus";
53 ranges = <0x16001000 0x16001000 0x00007000>,
54 <0x1f000000 0x1f000000 0x00400000>,
55 <0xa0000000 0xa0000000 0x20000>;
57 gic: interrupt-controller@16001000 {
58 compatible = "arm,cortex-a7-gic";
59 reg = <0x16001000 0x1000>,
63 #interrupt-cells = <3>;
65 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2)
66 | IRQ_TYPE_LEVEL_LOW)>;
70 compatible = "simple-bus";
71 reg = <0x1f000000 0x00400000>;
74 ranges = <0x0 0x1f000000 0x00400000>;
76 pmsleep: syscon@1c00 {
77 compatible = "mstar,msc313-pmsleep", "syscon";
82 compatible = "syscon-reboot";
88 l3bridge: l3bridge@204400 {
89 compatible = "mstar,l3bridge";
90 reg = <0x204400 0x200>;
93 pm_uart: uart@221000 {
94 compatible = "ns16550a";
95 reg = <0x221000 0x100>;
97 clock-frequency = <172000000>;
103 compatible = "mmio-sram";
104 reg = <0xa0000000 0x10000>;