arch/arm/boot/dts/mmp3.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 /*
   3  *  Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
   4  */
   5
   6 #include <dt-bindings/clock/marvell,mmp2.h>
   7 #include <dt-bindings/power/marvell,mmp2.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17                 enable-method = "marvell,mmp3-smp";
  18
  19                 cpu@0 {
  20                         compatible = "marvell,pj4b";
  21                         device_type = "cpu";
  22                         next-level-cache = <&l2>;
  23                         reg = <0>;
  24                 };
  25
  26                 cpu@1 {
  27                         compatible = "marvell,pj4b";
  28                         device_type = "cpu";
  29                         next-level-cache = <&l2>;
  30                         reg = <1>;
  31                 };
  32         };
  33
  34         soc {
  35                 #address-cells = <1>;
  36                 #size-cells = <1>;
  37                 compatible = "simple-bus";
  38                 interrupt-parent = <&gic>;
  39                 ranges;
  40
  41                 axi@d4200000 {
  42                         compatible = "simple-bus";
  43                         #address-cells = <1>;
  44                         #size-cells = <1>;
  45                         reg = <0xd4200000 0x00200000>;
  46                         ranges;
  47
  48                         interrupt-controller@d4282000 {
  49                                 compatible = "marvell,mmp3-intc";
  50                                 interrupt-controller;
  51                                 #interrupt-cells = <1>;
  52                                 reg = <0xd4282000 0x1000>,
  53                                       <0xd4284000 0x100>;
  54                                 mrvl,intc-nr-irqs = <64>;
  55                         };
  56
  57                         pmic_mux: interrupt-controller@d4282150 {
  58                                 compatible = "mrvl,mmp2-mux-intc";
  59                                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
  60                                 interrupt-controller;
  61                                 #interrupt-cells = <1>;
  62                                 reg = <0x150 0x4>, <0x168 0x4>;
  63                                 reg-names = "mux status", "mux mask";
  64                                 mrvl,intc-nr-irqs = <4>;
  65                         };
  66
  67                         rtc_mux: interrupt-controller@d4282154 {
  68                                 compatible = "mrvl,mmp2-mux-intc";
  69                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
  70                                 interrupt-controller;
  71                                 #interrupt-cells = <1>;
  72                                 reg = <0x154 0x4>, <0x16c 0x4>;
  73                                 reg-names = "mux status", "mux mask";
  74                                 mrvl,intc-nr-irqs = <2>;
  75                         };
  76
  77                         hsi3_mux: interrupt-controller@d42821bc {
  78                                 compatible = "mrvl,mmp2-mux-intc";
  79                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
  80                                 interrupt-controller;
  81                                 #interrupt-cells = <1>;
  82                                 reg = <0x1bc 0x4>, <0x1a4 0x4>;
  83                                 reg-names = "mux status", "mux mask";
  84                                 mrvl,intc-nr-irqs = <3>;
  85                         };
  86
  87                         gpu_mux: interrupt-controller@d42821c0 {
  88                                 compatible = "mrvl,mmp2-mux-intc";
  89                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  90                                 interrupt-controller;
  91                                 #interrupt-cells = <1>;
  92                                 reg = <0x1c0 0x4>, <0x1a8 0x4>;
  93                                 reg-names = "mux status", "mux mask";
  94                                 mrvl,intc-nr-irqs = <3>;
  95                         };
  96
  97                         twsi_mux: interrupt-controller@d4282158 {
  98                                 compatible = "mrvl,mmp2-mux-intc";
  99                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 100                                 interrupt-controller;
 101                                 #interrupt-cells = <1>;
 102                                 reg = <0x158 0x4>, <0x170 0x4>;
 103                                 reg-names = "mux status", "mux mask";
 104                                 mrvl,intc-nr-irqs = <5>;
 105                         };
 106
 107                         hsi2_mux: interrupt-controller@d42821c4 {
 108                                 compatible = "mrvl,mmp2-mux-intc";
 109                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 110                                 interrupt-controller;
 111                                 #interrupt-cells = <1>;
 112                                 reg = <0x1c4 0x4>, <0x1ac 0x4>;
 113                                 reg-names = "mux status", "mux mask";
 114                                 mrvl,intc-nr-irqs = <2>;
 115                         };
 116
 117                         dxo_mux: interrupt-controller@d42821c8 {
 118                                 compatible = "mrvl,mmp2-mux-intc";
 119                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 120                                 interrupt-controller;
 121                                 #interrupt-cells = <1>;
 122                                 reg = <0x1c8 0x4>, <0x1b0 0x4>;
 123                                 reg-names = "mux status", "mux mask";
 124                                 mrvl,intc-nr-irqs = <2>;
 125                         };
 126
 127                         misc1_mux: interrupt-controller@d428215c {
 128                                 compatible = "mrvl,mmp2-mux-intc";
 129                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 130                                 interrupt-controller;
 131                                 #interrupt-cells = <1>;
 132                                 reg = <0x15c 0x4>, <0x174 0x4>;
 133                                 reg-names = "mux status", "mux mask";
 134                                 mrvl,intc-nr-irqs = <31>;
 135                         };
 136
 137                         ci_mux: interrupt-controller@d42821cc {
 138                                 compatible = "mrvl,mmp2-mux-intc";
 139                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 140                                 interrupt-controller;
 141                                 #interrupt-cells = <1>;
 142                                 reg = <0x1cc 0x4>, <0x1b4 0x4>;
 143                                 reg-names = "mux status", "mux mask";
 144                                 mrvl,intc-nr-irqs = <2>;
 145                         };
 146
 147                         ssp_mux: interrupt-controller@d4282160 {
 148                                 compatible = "mrvl,mmp2-mux-intc";
 149                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 150                                 interrupt-controller;
 151                                 #interrupt-cells = <1>;
 152                                 reg = <0x160 0x4>, <0x178 0x4>;
 153                                 reg-names = "mux status", "mux mask";
 154                                 mrvl,intc-nr-irqs = <2>;
 155                         };
 156
 157                         hsi1_mux: interrupt-controller@d4282184 {
 158                                 compatible = "mrvl,mmp2-mux-intc";
 159                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 160                                 interrupt-controller;
 161                                 #interrupt-cells = <1>;
 162                                 reg = <0x184 0x4>, <0x17c 0x4>;
 163                                 reg-names = "mux status", "mux mask";
 164                                 mrvl,intc-nr-irqs = <4>;
 165                         };
 166
 167                         misc2_mux: interrupt-controller@d4282188 {
 168                                 compatible = "mrvl,mmp2-mux-intc";
 169                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 170                                 interrupt-controller;
 171                                 #interrupt-cells = <1>;
 172                                 reg = <0x188 0x4>, <0x180 0x4>;
 173                                 reg-names = "mux status", "mux mask";
 174                                 mrvl,intc-nr-irqs = <20>;
 175                         };
 176
 177                         hsi0_mux: interrupt-controller@d42821d0 {
 178                                 compatible = "mrvl,mmp2-mux-intc";
 179                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 180                                 interrupt-controller;
 181                                 #interrupt-cells = <1>;
 182                                 reg = <0x1d0 0x4>, <0x1b8 0x4>;
 183                                 reg-names = "mux status", "mux mask";
 184                                 mrvl,intc-nr-irqs = <5>;
 185                         };
 186
 187                         usb_otg_phy0: usb-phy@d4207000 {
 188                                 compatible = "marvell,mmp3-usb-phy";
 189                                 reg = <0xd4207000 0x40>;
 190                                 #phy-cells = <0>;
 191                                 status = "disabled";
 192                         };
 193
 194                         usb_otg0: usb@d4208000 {
 195                                 compatible = "marvell,pxau2o-ehci";
 196                                 reg = <0xd4208000 0x200>;
 197                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 198                                 clocks = <&soc_clocks MMP2_CLK_USB>;
 199                                 clock-names = "USBCLK";
 200                                 phys = <&usb_otg_phy0>;
 201                                 phy-names = "usb";
 202                                 status = "disabled";
 203                         };
 204
 205                         hsic_phy0: usb-phy@f0001800 {
 206                                 compatible = "marvell,mmp3-hsic-phy";
 207                                 reg = <0xf0001800 0x40>;
 208                                 #phy-cells = <0>;
 209                                 status = "disabled";
 210                         };
 211
 212                         hsic0: usb@f0001000 {
 213                                 compatible = "marvell,pxau2o-ehci";
 214                                 reg = <0xf0001000 0x200>;
 215                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 216                                 clocks = <&soc_clocks MMP2_CLK_USBHSIC0>;
 217                                 clock-names = "USBCLK";
 218                                 phys = <&hsic_phy0>;
 219                                 phy-names = "usb";
 220                                 phy_type = "hsic";
 221                                 #address-cells = <0x01>;
 222                                 #size-cells = <0x00>;
 223                                 status = "disabled";
 224                         };
 225
 226                         hsic_phy1: usb-phy@f0002800 {
 227                                 compatible = "marvell,mmp3-hsic-phy";
 228                                 reg = <0xf0002800 0x40>;
 229                                 #phy-cells = <0>;
 230                                 status = "disabled";
 231                         };
 232
 233                         hsic1: usb@f0002000 {
 234                                 compatible = "marvell,pxau2o-ehci";
 235                                 reg = <0xf0002000 0x200>;
 236                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 237                                 clocks = <&soc_clocks MMP2_CLK_USBHSIC1>;
 238                                 clock-names = "USBCLK";
 239                                 phys = <&hsic_phy1>;
 240                                 phy-names = "usb";
 241                                 phy_type = "hsic";
 242                                 #address-cells = <0x01>;
 243                                 #size-cells = <0x00>;
 244                                 status = "disabled";
 245                         };
 246
 247                         mmc1: mmc@d4280000 {
 248                                 compatible = "mrvl,pxav3-mmc";
 249                                 reg = <0xd4280000 0x120>;
 250                                 clocks = <&soc_clocks MMP2_CLK_SDH0>;
 251                                 clock-names = "io";
 252                                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 253                                 status = "disabled";
 254                         };
 255
 256                         mmc2: mmc@d4280800 {
 257                                 compatible = "mrvl,pxav3-mmc";
 258                                 reg = <0xd4280800 0x120>;
 259                                 clocks = <&soc_clocks MMP2_CLK_SDH1>;
 260                                 clock-names = "io";
 261                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 262                                 status = "disabled";
 263                         };
 264
 265                         mmc3: mmc@d4281000 {
 266                                 compatible = "mrvl,pxav3-mmc";
 267                                 reg = <0xd4281000 0x120>;
 268                                 clocks = <&soc_clocks MMP2_CLK_SDH2>;
 269                                 clock-names = "io";
 270                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 271                                 status = "disabled";
 272                         };
 273
 274                         mmc4: mmc@d4281800 {
 275                                 compatible = "mrvl,pxav3-mmc";
 276                                 reg = <0xd4281800 0x120>;
 277                                 clocks = <&soc_clocks MMP2_CLK_SDH3>;
 278                                 clock-names = "io";
 279                                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 280                                 status = "disabled";
 281                         };
 282
 283                         mmc5: mmc@d4217000 {
 284                                 compatible = "mrvl,pxav3-mmc";
 285                                 reg = <0xd4217000 0x120>;
 286                                 clocks = <&soc_clocks MMP3_CLK_SDH4>;
 287                                 clock-names = "io";
 288                                 interrupt-parent = <&hsi1_mux>;
 289                                 interrupts = <0>;
 290                                 status = "disabled";
 291                         };
 292
 293                         camera0: camera@d420a000 {
 294                                 compatible = "marvell,mmp2-ccic";
 295                                 reg = <0xd420a000 0x800>;
 296                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 297                                 clocks = <&soc_clocks MMP2_CLK_CCIC0>;
 298                                 clock-names = "axi";
 299                                 #clock-cells = <0>;
 300                                 clock-output-names = "mclk";
 301                                 status = "disabled";
 302                         };
 303
 304                         camera1: camera@d420a800 {
 305                                 compatible = "marvell,mmp2-ccic";
 306                                 reg = <0xd420a800 0x800>;
 307                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 308                                 clocks = <&soc_clocks MMP2_CLK_CCIC1>;
 309                                 clock-names = "axi";
 310                                 #clock-cells = <0>;
 311                                 clock-output-names = "mclk";
 312                                 status = "disabled";
 313                         };
 314
 315                         gpu_3d: gpu@d420d000 {
 316                                 compatible = "vivante,gc";
 317                                 reg = <0xd420d000 0x2000>;
 318                                 interrupt-parent = <&gpu_mux>;
 319                                 interrupts = <0>;
 320                                 status = "disabled";
 321                                 clocks = <&soc_clocks MMP3_CLK_GPU_3D>,
 322                                          <&soc_clocks MMP3_CLK_GPU_BUS>;
 323                                 clock-names = "core", "bus";
 324                                 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
 325                         };
 326
 327                         gpu_2d: gpu@d420f000 {
 328                                 compatible = "vivante,gc";
 329                                 reg = <0xd420f000 0x2000>;
 330                                 interrupt-parent = <&gpu_mux>;
 331                                 interrupts = <2>;
 332                                 status = "disabled";
 333                                 clocks = <&soc_clocks MMP3_CLK_GPU_2D>,
 334                                          <&soc_clocks MMP3_CLK_GPU_BUS>;
 335                                 clock-names = "core", "bus";
 336                                 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
 337                         };
 338                 };
 339
 340                 apb@d4000000 {
 341                         compatible = "simple-bus";
 342                         #address-cells = <1>;
 343                         #size-cells = <1>;
 344                         reg = <0xd4000000 0x00200000>;
 345                         ranges;
 346
 347                         timer: timer@d4014000 {
 348                                 compatible = "mrvl,mmp-timer";
 349                                 reg = <0xd4014000 0x100>;
 350                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 351                                 clocks = <&soc_clocks MMP2_CLK_TIMER>;
 352                         };
 353
 354                         uart1: serial@d4030000 {
 355                                 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
 356                                 reg = <0xd4030000 0x1000>;
 357                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 358                                 clocks = <&soc_clocks MMP2_CLK_UART0>;
 359                                 resets = <&soc_clocks MMP2_CLK_UART0>;
 360                                 reg-shift = <2>;
 361                                 status = "disabled";
 362                         };
 363
 364                         uart2: serial@d4017000 {
 365                                 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
 366                                 reg = <0xd4017000 0x1000>;
 367                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 368                                 clocks = <&soc_clocks MMP2_CLK_UART1>;
 369                                 resets = <&soc_clocks MMP2_CLK_UART1>;
 370                                 reg-shift = <2>;
 371                                 status = "disabled";
 372                         };
 373
 374                         uart3: serial@d4018000 {
 375                                 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
 376                                 reg = <0xd4018000 0x1000>;
 377                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 378                                 clocks = <&soc_clocks MMP2_CLK_UART2>;
 379                                 resets = <&soc_clocks MMP2_CLK_UART2>;
 380                                 reg-shift = <2>;
 381                                 status = "disabled";
 382                         };
 383
 384                         uart4: serial@d4016000 {
 385                                 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
 386                                 reg = <0xd4016000 0x1000>;
 387                                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 388                                 clocks = <&soc_clocks MMP2_CLK_UART3>;
 389                                 resets = <&soc_clocks MMP2_CLK_UART3>;
 390                                 reg-shift = <2>;
 391                                 status = "disabled";
 392                         };
 393
 394                         gpio: gpio@d4019000 {
 395                                 compatible = "marvell,mmp2-gpio";
 396                                 #address-cells = <1>;
 397                                 #size-cells = <1>;
 398                                 reg = <0xd4019000 0x1000>;
 399                                 gpio-controller;
 400                                 #gpio-cells = <2>;
 401                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 402                                 interrupt-names = "gpio_mux";
 403                                 clocks = <&soc_clocks MMP2_CLK_GPIO>;
 404                                 resets = <&soc_clocks MMP2_CLK_GPIO>;
 405                                 interrupt-controller;
 406                                 #interrupt-cells = <2>;
 407                                 ranges;
 408
 409                                 gcb0: gpio@d4019000 {
 410                                         reg = <0xd4019000 0x4>;
 411                                 };
 412
 413                                 gcb1: gpio@d4019004 {
 414                                         reg = <0xd4019004 0x4>;
 415                                 };
 416
 417                                 gcb2: gpio@d4019008 {
 418                                         reg = <0xd4019008 0x4>;
 419                                 };
 420
 421                                 gcb3: gpio@d4019100 {
 422                                         reg = <0xd4019100 0x4>;
 423                                 };
 424
 425                                 gcb4: gpio@d4019104 {
 426                                         reg = <0xd4019104 0x4>;
 427                                 };
 428
 429                                 gcb5: gpio@d4019108 {
 430                                         reg = <0xd4019108 0x4>;
 431                                 };
 432                         };
 433
 434                         twsi1: i2c@d4011000 {
 435                                 compatible = "mrvl,mmp-twsi";
 436                                 reg = <0xd4011000 0x70>;
 437                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 438                                 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
 439                                 resets = <&soc_clocks MMP2_CLK_TWSI0>;
 440                                 #address-cells = <1>;
 441                                 #size-cells = <0>;
 442                                 mrvl,i2c-fast-mode;
 443                                 status = "disabled";
 444                         };
 445
 446                         twsi2: i2c@d4031000 {
 447                                 compatible = "mrvl,mmp-twsi";
 448                                 reg = <0xd4031000 0x70>;
 449                                 interrupt-parent = <&twsi_mux>;
 450                                 interrupts = <0>;
 451                                 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
 452                                 resets = <&soc_clocks MMP2_CLK_TWSI1>;
 453                                 #address-cells = <1>;
 454                                 #size-cells = <0>;
 455                                 status = "disabled";
 456                         };
 457
 458                         twsi3: i2c@d4032000 {
 459                                 compatible = "mrvl,mmp-twsi";
 460                                 reg = <0xd4032000 0x70>;
 461                                 interrupt-parent = <&twsi_mux>;
 462                                 interrupts = <1>;
 463                                 clocks = <&soc_clocks MMP2_CLK_TWSI2>;
 464                                 resets = <&soc_clocks MMP2_CLK_TWSI2>;
 465                                 #address-cells = <1>;
 466                                 #size-cells = <0>;
 467                                 status = "disabled";
 468                         };
 469
 470                         twsi4: i2c@d4033000 {
 471                                 compatible = "mrvl,mmp-twsi";
 472                                 reg = <0xd4033000 0x70>;
 473                                 interrupt-parent = <&twsi_mux>;
 474                                 interrupts = <2>;
 475                                 clocks = <&soc_clocks MMP2_CLK_TWSI3>;
 476                                 resets = <&soc_clocks MMP2_CLK_TWSI3>;
 477                                 #address-cells = <1>;
 478                                 #size-cells = <0>;
 479                                 status = "disabled";
 480                         };
 481
 482
 483                         twsi5: i2c@d4033800 {
 484                                 compatible = "mrvl,mmp-twsi";
 485                                 reg = <0xd4033800 0x70>;
 486                                 interrupt-parent = <&twsi_mux>;
 487                                 interrupts = <3>;
 488                                 clocks = <&soc_clocks MMP2_CLK_TWSI4>;
 489                                 resets = <&soc_clocks MMP2_CLK_TWSI4>;
 490                                 #address-cells = <1>;
 491                                 #size-cells = <0>;
 492                                 status = "disabled";
 493                         };
 494
 495                         twsi6: i2c@d4034000 {
 496                                 compatible = "mrvl,mmp-twsi";
 497                                 reg = <0xd4034000 0x70>;
 498                                 interrupt-parent = <&twsi_mux>;
 499                                 interrupts = <4>;
 500                                 clocks = <&soc_clocks MMP2_CLK_TWSI5>;
 501                                 resets = <&soc_clocks MMP2_CLK_TWSI5>;
 502                                 #address-cells = <1>;
 503                                 #size-cells = <0>;
 504                                 status = "disabled";
 505                         };
 506
 507                         rtc: rtc@d4010000 {
 508                                 compatible = "mrvl,mmp-rtc";
 509                                 reg = <0xd4010000 0x1000>;
 510                                 interrupts = <1>, <0>;
 511                                 interrupt-names = "rtc 1Hz", "rtc alarm";
 512                                 interrupt-parent = <&rtc_mux>;
 513                                 clocks = <&soc_clocks MMP2_CLK_RTC>;
 514                                 resets = <&soc_clocks MMP2_CLK_RTC>;
 515                                 status = "disabled";
 516                         };
 517
 518                         ssp1: spi@d4035000 {
 519                                 compatible = "marvell,mmp2-ssp";
 520                                 reg = <0xd4035000 0x1000>;
 521                                 clocks = <&soc_clocks MMP2_CLK_SSP0>;
 522                                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 523                                 #address-cells = <1>;
 524                                 #size-cells = <0>;
 525                                 status = "disabled";
 526                         };
 527
 528                         ssp2: spi@d4036000 {
 529                                 compatible = "marvell,mmp2-ssp";
 530                                 reg = <0xd4036000 0x1000>;
 531                                 clocks = <&soc_clocks MMP2_CLK_SSP1>;
 532                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 533                                 #address-cells = <1>;
 534                                 #size-cells = <0>;
 535                                 status = "disabled";
 536                         };
 537
 538                         ssp3: spi@d4037000 {
 539                                 compatible = "marvell,mmp2-ssp";
 540                                 reg = <0xd4037000 0x1000>;
 541                                 clocks = <&soc_clocks MMP2_CLK_SSP2>;
 542                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 543                                 #address-cells = <1>;
 544                                 #size-cells = <0>;
 545                                 status = "disabled";
 546                         };
 547
 548                         ssp4: spi@d4039000 {
 549                                 compatible = "marvell,mmp2-ssp";
 550                                 reg = <0xd4039000 0x1000>;
 551                                 clocks = <&soc_clocks MMP2_CLK_SSP3>;
 552                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 553                                 #address-cells = <1>;
 554                                 #size-cells = <0>;
 555                                 status = "disabled";
 556                         };
 557                 };
 558
 559                 l2: cache-controller@d0020000 {
 560                         compatible = "marvell,tauros3-cache", "arm,pl310-cache";
 561                         reg = <0xd0020000 0x1000>;
 562                         cache-unified;
 563                         cache-level = <2>;
 564                 };
 565
 566                 soc_clocks: clocks@d4050000 {
 567                         compatible = "marvell,mmp3-clock";
 568                         reg = <0xd4050000 0x1000>,
 569                               <0xd4282800 0x400>,
 570                               <0xd4015000 0x1000>;
 571                         reg-names = "mpmu", "apmu", "apbc";
 572                         #clock-cells = <1>;
 573                         #reset-cells = <1>;
 574                         #power-domain-cells = <1>;
 575                 };
 576
 577                 snoop-control-unit@e0000000 {
 578                         compatible = "arm,arm11mp-scu";
 579                         reg = <0xe0000000 0x100>;
 580                 };
 581
 582                 gic: interrupt-controller@e0001000 {
 583                         compatible = "arm,arm11mp-gic";
 584                         interrupt-controller;
 585                         #interrupt-cells = <3>;
 586                         reg = <0xe0001000 0x1000>,
 587                               <0xe0000100 0x100>;
 588                 };
 589
 590                 local-timer@e0000600 {
 591                         compatible = "arm,arm11mp-twd-timer";
 592                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 593                                                   IRQ_TYPE_EDGE_RISING)>;
 594                         reg = <0xe0000600 0x20>;
 595                 };
 596
 597                 watchdog@e0000620 {
 598                         compatible = "arm,arm11mp-twd-wdt";
 599                         reg = <0xe0000620 0x20>;
 600                         interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 601                                                   IRQ_TYPE_EDGE_RISING)>;
 602                 };
 603         };
 604 };