1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Marvell Technology Group Ltd.
4 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
7 #include <dt-bindings/clock/marvell,mmp2.h>
8 #include <dt-bindings/power/marvell,mmp2.h>
26 compatible = "simple-bus";
27 interrupt-parent = <&intc>;
31 compatible = "marvell,tauros2-cache";
32 marvell,tauros2-cache-features = <0x3>;
35 axi@d4200000 { /* AXI */
36 compatible = "mrvl,axi-bus", "simple-bus";
39 reg = <0xd4200000 0x00200000>;
43 compatible = "vivante,gc";
44 reg = <0xd420d000 0x4000>;
47 clocks = <&soc_clocks MMP2_CLK_GPU_3D>,
48 <&soc_clocks MMP2_CLK_GPU_BUS>;
49 clock-names = "core", "bus";
50 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
53 intc: interrupt-controller@d4282000 {
54 compatible = "mrvl,mmp2-intc";
56 #interrupt-cells = <1>;
57 reg = <0xd4282000 0x1000>;
58 mrvl,intc-nr-irqs = <64>;
61 intcmux4: interrupt-controller@d4282150 {
62 compatible = "mrvl,mmp2-mux-intc";
65 #interrupt-cells = <1>;
66 reg = <0x150 0x4>, <0x168 0x4>;
67 reg-names = "mux status", "mux mask";
68 mrvl,intc-nr-irqs = <2>;
71 intcmux5: interrupt-controller@d4282154 {
72 compatible = "mrvl,mmp2-mux-intc";
75 #interrupt-cells = <1>;
76 reg = <0x154 0x4>, <0x16c 0x4>;
77 reg-names = "mux status", "mux mask";
78 mrvl,intc-nr-irqs = <2>;
79 mrvl,clr-mfp-irq = <1>;
82 intcmux9: interrupt-controller@d4282180 {
83 compatible = "mrvl,mmp2-mux-intc";
86 #interrupt-cells = <1>;
87 reg = <0x180 0x4>, <0x17c 0x4>;
88 reg-names = "mux status", "mux mask";
89 mrvl,intc-nr-irqs = <3>;
92 intcmux17: interrupt-controller@d4282158 {
93 compatible = "mrvl,mmp2-mux-intc";
96 #interrupt-cells = <1>;
97 reg = <0x158 0x4>, <0x170 0x4>;
98 reg-names = "mux status", "mux mask";
99 mrvl,intc-nr-irqs = <5>;
102 intcmux35: interrupt-controller@d428215c {
103 compatible = "mrvl,mmp2-mux-intc";
105 interrupt-controller;
106 #interrupt-cells = <1>;
107 reg = <0x15c 0x4>, <0x174 0x4>;
108 reg-names = "mux status", "mux mask";
109 mrvl,intc-nr-irqs = <15>;
112 intcmux51: interrupt-controller@d4282160 {
113 compatible = "mrvl,mmp2-mux-intc";
115 interrupt-controller;
116 #interrupt-cells = <1>;
117 reg = <0x160 0x4>, <0x178 0x4>;
118 reg-names = "mux status", "mux mask";
119 mrvl,intc-nr-irqs = <2>;
122 intcmux55: interrupt-controller@d4282188 {
123 compatible = "mrvl,mmp2-mux-intc";
125 interrupt-controller;
126 #interrupt-cells = <1>;
127 reg = <0x188 0x4>, <0x184 0x4>;
128 reg-names = "mux status", "mux mask";
129 mrvl,intc-nr-irqs = <2>;
132 usb_phy0: usb-phy@d4207000 {
133 compatible = "marvell,mmp2-usb-phy";
134 reg = <0xd4207000 0x40>;
139 usb_otg0: usb-otg@d4208000 {
140 compatible = "marvell,pxau2o-ehci";
141 reg = <0xd4208000 0x200>;
143 clocks = <&soc_clocks MMP2_CLK_USB>;
144 clock-names = "USBCLK";
151 compatible = "mrvl,pxav3-mmc";
152 reg = <0xd4280000 0x120>;
153 clocks = <&soc_clocks MMP2_CLK_SDH0>;
160 compatible = "mrvl,pxav3-mmc";
161 reg = <0xd4280800 0x120>;
162 clocks = <&soc_clocks MMP2_CLK_SDH1>;
169 compatible = "mrvl,pxav3-mmc";
170 reg = <0xd4281000 0x120>;
171 clocks = <&soc_clocks MMP2_CLK_SDH2>;
178 compatible = "mrvl,pxav3-mmc";
179 reg = <0xd4281800 0x120>;
180 clocks = <&soc_clocks MMP2_CLK_SDH3>;
186 camera0: camera@d420a000 {
187 compatible = "marvell,mmp2-ccic";
188 reg = <0xd420a000 0x800>;
190 clocks = <&soc_clocks MMP2_CLK_CCIC0>;
193 clock-output-names = "mclk";
197 camera1: camera@d420a800 {
198 compatible = "marvell,mmp2-ccic";
199 reg = <0xd420a800 0x800>;
201 clocks = <&soc_clocks MMP2_CLK_CCIC1>;
204 clock-output-names = "mclk";
208 adma0: dma-controller@d42a0800 {
209 compatible = "marvell,adma-1.0";
210 reg = <0xd42a0800 0x100>;
218 adma1: dma-controller@d42a0900 {
219 compatible = "marvell,adma-1.0";
220 reg = <0xd42a0900 0x100>;
226 audio_clk: clocks@d42a0c30 {
227 compatible = "marvell,mmp2-audio-clock";
228 reg = <0xd42a0c30 0x10>;
229 clock-names = "audio", "vctcxo", "i2s0", "i2s1";
230 clocks = <&soc_clocks MMP2_CLK_AUDIO>,
231 <&soc_clocks MMP2_CLK_VCTCXO>,
232 <&soc_clocks MMP2_CLK_I2S0>,
233 <&soc_clocks MMP2_CLK_I2S1>;
234 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
239 sspa0: audio-controller@d42a0c00 {
240 compatible = "marvell,mmp-sspa";
241 reg = <0xd42a0c00 0x30>,
244 clock-names = "audio", "bitclk";
245 clocks = <&soc_clocks MMP2_CLK_AUDIO>,
247 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
248 #sound-dai-cells = <0>;
252 sspa1: audio-controller@d42a0d00 {
253 compatible = "marvell,mmp-sspa";
254 reg = <0xd42a0d00 0x30>,
257 clock-names = "audio", "bitclk";
258 clocks = <&soc_clocks MMP2_CLK_AUDIO>,
260 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
261 #sound-dai-cells = <0>;
266 apb@d4000000 { /* APB */
267 compatible = "mrvl,apb-bus", "simple-bus";
268 #address-cells = <1>;
270 reg = <0xd4000000 0x00200000>;
273 dma-controller@d4000000 {
274 compatible = "marvell,pdma-1.0";
275 reg = <0xd4000000 0x10000>;
277 #dma-channels = <16>;
281 timer0: timer@d4014000 {
282 compatible = "mrvl,mmp-timer";
283 reg = <0xd4014000 0x100>;
285 clocks = <&soc_clocks MMP2_CLK_TIMER>;
288 uart1: serial@d4030000 {
289 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
290 reg = <0xd4030000 0x1000>;
292 clocks = <&soc_clocks MMP2_CLK_UART0>;
293 resets = <&soc_clocks MMP2_CLK_UART0>;
298 uart2: serial@d4017000 {
299 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
300 reg = <0xd4017000 0x1000>;
302 clocks = <&soc_clocks MMP2_CLK_UART1>;
303 resets = <&soc_clocks MMP2_CLK_UART1>;
308 uart3: serial@d4018000 {
309 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
310 reg = <0xd4018000 0x1000>;
312 clocks = <&soc_clocks MMP2_CLK_UART2>;
313 resets = <&soc_clocks MMP2_CLK_UART2>;
318 uart4: serial@d4016000 {
319 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
320 reg = <0xd4016000 0x1000>;
322 clocks = <&soc_clocks MMP2_CLK_UART3>;
323 resets = <&soc_clocks MMP2_CLK_UART3>;
328 gpio: gpio@d4019000 {
329 compatible = "marvell,mmp2-gpio";
330 #address-cells = <1>;
332 reg = <0xd4019000 0x1000>;
336 interrupt-names = "gpio_mux";
337 clocks = <&soc_clocks MMP2_CLK_GPIO>;
338 resets = <&soc_clocks MMP2_CLK_GPIO>;
339 interrupt-controller;
340 #interrupt-cells = <2>;
343 gcb0: gpio@d4019000 {
344 reg = <0xd4019000 0x4>;
347 gcb1: gpio@d4019004 {
348 reg = <0xd4019004 0x4>;
351 gcb2: gpio@d4019008 {
352 reg = <0xd4019008 0x4>;
355 gcb3: gpio@d4019100 {
356 reg = <0xd4019100 0x4>;
359 gcb4: gpio@d4019104 {
360 reg = <0xd4019104 0x4>;
363 gcb5: gpio@d4019108 {
364 reg = <0xd4019108 0x4>;
368 twsi1: i2c@d4011000 {
369 compatible = "mrvl,mmp-twsi";
370 reg = <0xd4011000 0x1000>;
372 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
373 resets = <&soc_clocks MMP2_CLK_TWSI0>;
374 #address-cells = <1>;
380 twsi2: i2c@d4031000 {
381 compatible = "mrvl,mmp-twsi";
382 reg = <0xd4031000 0x1000>;
383 interrupt-parent = <&intcmux17>;
385 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
386 resets = <&soc_clocks MMP2_CLK_TWSI1>;
387 #address-cells = <1>;
392 twsi3: i2c@d4032000 {
393 compatible = "mrvl,mmp-twsi";
394 reg = <0xd4032000 0x1000>;
395 interrupt-parent = <&intcmux17>;
397 clocks = <&soc_clocks MMP2_CLK_TWSI2>;
398 resets = <&soc_clocks MMP2_CLK_TWSI2>;
399 #address-cells = <1>;
404 twsi4: i2c@d4033000 {
405 compatible = "mrvl,mmp-twsi";
406 reg = <0xd4033000 0x1000>;
407 interrupt-parent = <&intcmux17>;
409 clocks = <&soc_clocks MMP2_CLK_TWSI3>;
410 resets = <&soc_clocks MMP2_CLK_TWSI3>;
411 #address-cells = <1>;
417 twsi5: i2c@d4033800 {
418 compatible = "mrvl,mmp-twsi";
419 reg = <0xd4033800 0x1000>;
420 interrupt-parent = <&intcmux17>;
422 clocks = <&soc_clocks MMP2_CLK_TWSI4>;
423 resets = <&soc_clocks MMP2_CLK_TWSI4>;
424 #address-cells = <1>;
429 twsi6: i2c@d4034000 {
430 compatible = "mrvl,mmp-twsi";
431 reg = <0xd4034000 0x1000>;
432 interrupt-parent = <&intcmux17>;
434 clocks = <&soc_clocks MMP2_CLK_TWSI5>;
435 resets = <&soc_clocks MMP2_CLK_TWSI5>;
436 #address-cells = <1>;
442 compatible = "mrvl,mmp-rtc";
443 reg = <0xd4010000 0x1000>;
444 interrupts = <1>, <0>;
445 interrupt-names = "rtc 1Hz", "rtc alarm";
446 interrupt-parent = <&intcmux5>;
447 clocks = <&soc_clocks MMP2_CLK_RTC>;
448 resets = <&soc_clocks MMP2_CLK_RTC>;
453 compatible = "marvell,mmp2-ssp";
454 reg = <0xd4035000 0x1000>;
455 clocks = <&soc_clocks MMP2_CLK_SSP0>;
457 #address-cells = <1>;
463 compatible = "marvell,mmp2-ssp";
464 reg = <0xd4036000 0x1000>;
465 clocks = <&soc_clocks MMP2_CLK_SSP1>;
467 #address-cells = <1>;
473 compatible = "marvell,mmp2-ssp";
474 reg = <0xd4037000 0x1000>;
475 clocks = <&soc_clocks MMP2_CLK_SSP2>;
477 #address-cells = <1>;
483 compatible = "marvell,mmp2-ssp";
484 reg = <0xd4039000 0x1000>;
485 clocks = <&soc_clocks MMP2_CLK_SSP3>;
487 #address-cells = <1>;
493 asram: sram@e0000000 {
494 compatible = "mmio-sram";
495 reg = <0xe0000000 0x10000>;
496 ranges = <0 0xe0000000 0x10000>;
497 #address-cells = <1>;
503 compatible = "marvell,mmp2-clock";
504 reg = <0xd4050000 0x2000>,
507 reg-names = "mpmu", "apmu", "apbc";
510 #power-domain-cells = <1>;