1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8b-gpio.h>
9 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
20 compatible = "arm,cortex-a5";
21 next-level-cache = <&L2>;
23 enable-method = "amlogic,meson8b-smp";
24 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
25 operating-points-v2 = <&cpu_opp_table>;
26 clocks = <&clkc CLKID_CPUCLK>;
31 compatible = "arm,cortex-a5";
32 next-level-cache = <&L2>;
34 enable-method = "amlogic,meson8b-smp";
35 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
36 operating-points-v2 = <&cpu_opp_table>;
37 clocks = <&clkc CLKID_CPUCLK>;
42 compatible = "arm,cortex-a5";
43 next-level-cache = <&L2>;
45 enable-method = "amlogic,meson8b-smp";
46 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
47 operating-points-v2 = <&cpu_opp_table>;
48 clocks = <&clkc CLKID_CPUCLK>;
53 compatible = "arm,cortex-a5";
54 next-level-cache = <&L2>;
56 enable-method = "amlogic,meson8b-smp";
57 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
58 operating-points-v2 = <&cpu_opp_table>;
59 clocks = <&clkc CLKID_CPUCLK>;
63 cpu_opp_table: opp-table {
64 compatible = "operating-points-v2";
68 opp-hz = /bits/ 64 <96000000>;
69 opp-microvolt = <860000>;
72 opp-hz = /bits/ 64 <192000000>;
73 opp-microvolt = <860000>;
76 opp-hz = /bits/ 64 <312000000>;
77 opp-microvolt = <860000>;
80 opp-hz = /bits/ 64 <408000000>;
81 opp-microvolt = <860000>;
84 opp-hz = /bits/ 64 <504000000>;
85 opp-microvolt = <860000>;
88 opp-hz = /bits/ 64 <600000000>;
89 opp-microvolt = <860000>;
92 opp-hz = /bits/ 64 <720000000>;
93 opp-microvolt = <860000>;
96 opp-hz = /bits/ 64 <816000000>;
97 opp-microvolt = <900000>;
100 opp-hz = /bits/ 64 <1008000000>;
101 opp-microvolt = <1140000>;
104 opp-hz = /bits/ 64 <1200000000>;
105 opp-microvolt = <1140000>;
108 opp-hz = /bits/ 64 <1320000000>;
109 opp-microvolt = <1140000>;
112 opp-hz = /bits/ 64 <1488000000>;
113 opp-microvolt = <1140000>;
116 opp-hz = /bits/ 64 <1536000000>;
117 opp-microvolt = <1140000>;
121 gpu_opp_table: gpu-opp-table {
122 compatible = "operating-points-v2";
125 opp-hz = /bits/ 64 <255000000>;
126 opp-microvolt = <1100000>;
129 opp-hz = /bits/ 64 <364300000>;
130 opp-microvolt = <1100000>;
133 opp-hz = /bits/ 64 <425000000>;
134 opp-microvolt = <1100000>;
137 opp-hz = /bits/ 64 <510000000>;
138 opp-microvolt = <1100000>;
141 opp-hz = /bits/ 64 <637500000>;
142 opp-microvolt = <1100000>;
148 compatible = "arm,cortex-a5-pmu";
149 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
153 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
157 #address-cells = <1>;
161 /* 2 MiB reserved for Hardware ROM Firmware? */
163 reg = <0x0 0x200000>;
168 mmcbus: bus@c8000000 {
169 compatible = "simple-bus";
170 reg = <0xc8000000 0x8000>;
171 #address-cells = <1>;
173 ranges = <0x0 0xc8000000 0x8000>;
176 compatible = "simple-bus";
177 reg = <0x6000 0x400>;
178 #address-cells = <1>;
180 ranges = <0x0 0x6000 0x400>;
182 canvas: video-lut@48 {
183 compatible = "amlogic,meson8b-canvas",
191 compatible = "simple-bus";
192 reg = <0xd0000000 0x200000>;
193 #address-cells = <1>;
195 ranges = <0x0 0xd0000000 0x200000>;
198 compatible = "amlogic,meson8b-mali", "arm,mali-450";
199 reg = <0xc0000 0x40000>;
200 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
208 interrupt-names = "gp", "gpmmu", "pp", "pmu",
209 "pp0", "ppmmu0", "pp1", "ppmmu1";
210 resets = <&reset RESET_MALI>;
211 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
212 clock-names = "bus", "core";
213 operating-points-v2 = <&gpu_opp_table>;
220 compatible = "amlogic,meson8b-pmu", "syscon";
224 pinctrl_aobus: pinctrl@84 {
225 compatible = "amlogic,meson8b-aobus-pinctrl";
227 #address-cells = <1>;
231 gpio_ao: ao-bank@14 {
235 reg-names = "mux", "pull", "gpio";
238 gpio-ranges = <&pinctrl_aobus 0 0 16>;
241 uart_ao_a_pins: uart_ao_a {
243 groups = "uart_tx_ao_a", "uart_rx_ao_a";
244 function = "uart_ao";
249 ir_recv_pins: remote {
251 groups = "remote_input";
260 reset: reset-controller@4404 {
261 compatible = "amlogic,meson8b-reset";
266 analog_top: analog-top@81a8 {
267 compatible = "amlogic,meson8b-analog-top", "syscon";
272 compatible = "amlogic,meson8b-pwm";
279 compatible = "amlogic,meson8b-clk-measure";
283 pinctrl_cbus: pinctrl@9880 {
284 compatible = "amlogic,meson8b-cbus-pinctrl";
286 #address-cells = <1>;
295 reg-names = "mux", "pull", "pull-enable", "gpio";
298 gpio-ranges = <&pinctrl_cbus 0 0 83>;
301 eth_rgmii_pins: eth-rgmii {
303 groups = "eth_tx_clk",
318 function = "ethernet";
323 eth_rmii_pins: eth-rmii {
325 groups = "eth_tx_en",
334 function = "ethernet";
341 groups = "i2c_sda_a", "i2c_sck_a";
349 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
350 "sd_d3_b", "sd_clk_b", "sd_cmd_b";
356 pwm_c1_pins: pwm-c1 {
364 uart_b0_pins: uart-b0 {
366 groups = "uart_tx_b0",
373 uart_b0_cts_rts_pins: uart-b0-cts-rts {
375 groups = "uart_cts_b0",
386 compatible = "amlogic,meson8b-smp-sram";
393 compatible = "amlogic,meson8b-efuse";
394 clocks = <&clkc CLKID_EFUSE>;
395 clock-names = "core";
397 temperature_calib: calib@1f4 {
398 /* only the upper two bytes are relevant */
404 compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
406 reg = <0xc9410000 0x10000
409 clocks = <&clkc CLKID_ETH>,
412 clock-names = "stmmaceth", "clkin0", "clkin1";
414 resets = <&reset RESET_ETHERNET>;
415 reset-names = "stmmaceth";
419 compatible = "amlogic,meson-gpio-intc",
420 "amlogic,meson8b-gpio-intc";
425 clkc: clock-controller {
426 compatible = "amlogic,meson8-clkc";
433 compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
434 clocks = <&clkc CLKID_RNG0>;
435 clock-names = "core";
439 clocks = <&clkc CLKID_CLK81>;
443 clocks = <&clkc CLKID_I2C>;
447 clocks = <&clkc CLKID_I2C>;
451 arm,data-latency = <3 3 3>;
452 arm,tag-latency = <2 2 2>;
453 arm,filter-ranges = <0x100000 0xc0000000>;
455 prefetch-instr = <1>;
461 compatible = "arm,cortex-a5-scu";
466 compatible = "arm,cortex-a5-global-timer";
468 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
469 clocks = <&clkc CLKID_PERIPH>;
472 * the arm_global_timer driver currently does not handle clock
473 * rate changes. Keep it disabled for now.
479 compatible = "arm,cortex-a5-twd-timer";
481 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
482 clocks = <&clkc CLKID_PERIPH>;
487 compatible = "amlogic,meson8b-pwm";
491 compatible = "amlogic,meson8b-pwm";
495 compatible = "amlogic,meson8b-rtc";
496 resets = <&reset RESET_RTC>;
500 compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
501 clocks = <&clkc CLKID_XTAL>,
502 <&clkc CLKID_SAR_ADC>;
503 clock-names = "clkin", "core";
504 amlogic,hhi-sysctrl = <&hhi>;
505 nvmem-cells = <&temperature_calib>;
506 nvmem-cell-names = "temperature_calib";
510 compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
511 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
512 clock-names = "core", "clkin";
516 clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
517 clock-names = "xtal", "pclk";
521 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
522 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
523 clock-names = "baud", "xtal", "pclk";
527 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
528 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
529 clock-names = "baud", "xtal", "pclk";
533 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
534 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
535 clock-names = "baud", "xtal", "pclk";
539 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
540 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
541 clock-names = "baud", "xtal", "pclk";
545 compatible = "amlogic,meson8b-usb", "snps,dwc2";
546 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
551 compatible = "amlogic,meson8b-usb", "snps,dwc2";
552 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
557 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
558 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
559 clock-names = "usb_general", "usb";
560 resets = <&reset RESET_USB_OTG>;
564 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
565 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
566 clock-names = "usb_general", "usb";
567 resets = <&reset RESET_USB_OTG>;
571 compatible = "amlogic,meson8b-wdt";