1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
21 compatible = "arm,cortex-a5";
22 next-level-cache = <&L2>;
24 enable-method = "amlogic,meson8b-smp";
25 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
26 operating-points-v2 = <&cpu_opp_table>;
27 clocks = <&clkc CLKID_CPUCLK>;
32 compatible = "arm,cortex-a5";
33 next-level-cache = <&L2>;
35 enable-method = "amlogic,meson8b-smp";
36 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
37 operating-points-v2 = <&cpu_opp_table>;
38 clocks = <&clkc CLKID_CPUCLK>;
43 compatible = "arm,cortex-a5";
44 next-level-cache = <&L2>;
46 enable-method = "amlogic,meson8b-smp";
47 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
48 operating-points-v2 = <&cpu_opp_table>;
49 clocks = <&clkc CLKID_CPUCLK>;
54 compatible = "arm,cortex-a5";
55 next-level-cache = <&L2>;
57 enable-method = "amlogic,meson8b-smp";
58 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
59 operating-points-v2 = <&cpu_opp_table>;
60 clocks = <&clkc CLKID_CPUCLK>;
64 cpu_opp_table: opp-table {
65 compatible = "operating-points-v2";
69 opp-hz = /bits/ 64 <96000000>;
70 opp-microvolt = <860000>;
73 opp-hz = /bits/ 64 <192000000>;
74 opp-microvolt = <860000>;
77 opp-hz = /bits/ 64 <312000000>;
78 opp-microvolt = <860000>;
81 opp-hz = /bits/ 64 <408000000>;
82 opp-microvolt = <860000>;
85 opp-hz = /bits/ 64 <504000000>;
86 opp-microvolt = <860000>;
89 opp-hz = /bits/ 64 <600000000>;
90 opp-microvolt = <860000>;
93 opp-hz = /bits/ 64 <720000000>;
94 opp-microvolt = <860000>;
97 opp-hz = /bits/ 64 <816000000>;
98 opp-microvolt = <900000>;
101 opp-hz = /bits/ 64 <1008000000>;
102 opp-microvolt = <1140000>;
105 opp-hz = /bits/ 64 <1200000000>;
106 opp-microvolt = <1140000>;
109 opp-hz = /bits/ 64 <1320000000>;
110 opp-microvolt = <1140000>;
113 opp-hz = /bits/ 64 <1488000000>;
114 opp-microvolt = <1140000>;
117 opp-hz = /bits/ 64 <1536000000>;
118 opp-microvolt = <1140000>;
122 gpu_opp_table: gpu-opp-table {
123 compatible = "operating-points-v2";
126 opp-hz = /bits/ 64 <255000000>;
127 opp-microvolt = <1100000>;
130 opp-hz = /bits/ 64 <364285714>;
131 opp-microvolt = <1100000>;
134 opp-hz = /bits/ 64 <425000000>;
135 opp-microvolt = <1100000>;
138 opp-hz = /bits/ 64 <510000000>;
139 opp-microvolt = <1100000>;
142 opp-hz = /bits/ 64 <637500000>;
143 opp-microvolt = <1100000>;
149 compatible = "arm,cortex-a5-pmu";
150 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
154 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
158 #address-cells = <1>;
162 /* 2 MiB reserved for Hardware ROM Firmware? */
164 reg = <0x0 0x200000>;
169 mmcbus: bus@c8000000 {
170 compatible = "simple-bus";
171 reg = <0xc8000000 0x8000>;
172 #address-cells = <1>;
174 ranges = <0x0 0xc8000000 0x8000>;
176 ddr_clkc: clock-controller@400 {
177 compatible = "amlogic,meson8b-ddr-clkc";
180 clock-names = "xtal";
185 compatible = "simple-bus";
186 reg = <0x6000 0x400>;
187 #address-cells = <1>;
189 ranges = <0x0 0x6000 0x400>;
191 canvas: video-lut@48 {
192 compatible = "amlogic,meson8b-canvas",
200 compatible = "simple-bus";
201 reg = <0xd0000000 0x200000>;
202 #address-cells = <1>;
204 ranges = <0x0 0xd0000000 0x200000>;
207 compatible = "amlogic,meson8b-mali", "arm,mali-450";
208 reg = <0xc0000 0x40000>;
209 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
217 interrupt-names = "gp", "gpmmu", "pp", "pmu",
218 "pp0", "ppmmu0", "pp1", "ppmmu1";
219 resets = <&reset RESET_MALI>;
220 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
221 clock-names = "bus", "core";
222 operating-points-v2 = <&gpu_opp_table>;
229 compatible = "amlogic,meson8b-pmu", "syscon";
233 pinctrl_aobus: pinctrl@84 {
234 compatible = "amlogic,meson8b-aobus-pinctrl";
236 #address-cells = <1>;
240 gpio_ao: ao-bank@14 {
244 reg-names = "mux", "pull", "gpio";
247 gpio-ranges = <&pinctrl_aobus 0 0 16>;
250 uart_ao_a_pins: uart_ao_a {
252 groups = "uart_tx_ao_a", "uart_rx_ao_a";
253 function = "uart_ao";
258 ir_recv_pins: remote {
260 groups = "remote_input";
269 reset: reset-controller@4404 {
270 compatible = "amlogic,meson8b-reset";
275 analog_top: analog-top@81a8 {
276 compatible = "amlogic,meson8b-analog-top", "syscon";
281 compatible = "amlogic,meson8b-pwm";
288 compatible = "amlogic,meson8b-clk-measure";
292 pinctrl_cbus: pinctrl@9880 {
293 compatible = "amlogic,meson8b-cbus-pinctrl";
295 #address-cells = <1>;
304 reg-names = "mux", "pull", "pull-enable", "gpio";
307 gpio-ranges = <&pinctrl_cbus 0 0 83>;
310 eth_rgmii_pins: eth-rgmii {
312 groups = "eth_tx_clk",
327 function = "ethernet";
332 eth_rmii_pins: eth-rmii {
334 groups = "eth_tx_en",
343 function = "ethernet";
350 groups = "i2c_sda_a", "i2c_sck_a";
358 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
359 "sd_d3_b", "sd_clk_b", "sd_cmd_b";
365 pwm_c1_pins: pwm-c1 {
381 uart_b0_pins: uart-b0 {
383 groups = "uart_tx_b0",
390 uart_b0_cts_rts_pins: uart-b0-cts-rts {
392 groups = "uart_cts_b0",
403 compatible = "amlogic,meson8b-smp-sram";
410 compatible = "amlogic,meson8b-efuse";
411 clocks = <&clkc CLKID_EFUSE>;
412 clock-names = "core";
414 temperature_calib: calib@1f4 {
415 /* only the upper two bytes are relevant */
421 compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
423 reg = <0xc9410000 0x10000
426 clocks = <&clkc CLKID_ETH>,
429 clock-names = "stmmaceth", "clkin0", "clkin1";
430 rx-fifo-depth = <4096>;
431 tx-fifo-depth = <2048>;
433 resets = <&reset RESET_ETHERNET>;
434 reset-names = "stmmaceth";
438 compatible = "amlogic,meson-gpio-intc",
439 "amlogic,meson8b-gpio-intc";
444 clkc: clock-controller {
445 compatible = "amlogic,meson8b-clkc";
446 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
447 clock-names = "xtal", "ddr_pll";
454 compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
455 clocks = <&clkc CLKID_RNG0>;
456 clock-names = "core";
460 clocks = <&clkc CLKID_CLK81>;
464 clocks = <&clkc CLKID_I2C>;
468 clocks = <&clkc CLKID_I2C>;
472 arm,data-latency = <3 3 3>;
473 arm,tag-latency = <2 2 2>;
474 arm,filter-ranges = <0x100000 0xc0000000>;
476 prefetch-instr = <1>;
482 compatible = "arm,cortex-a5-scu";
487 compatible = "arm,cortex-a5-global-timer";
489 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
490 clocks = <&clkc CLKID_PERIPH>;
493 * the arm_global_timer driver currently does not handle clock
494 * rate changes. Keep it disabled for now.
500 compatible = "arm,cortex-a5-twd-timer";
502 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
503 clocks = <&clkc CLKID_PERIPH>;
508 compatible = "amlogic,meson8b-pwm";
512 compatible = "amlogic,meson8b-pwm";
516 compatible = "amlogic,meson8b-rtc";
517 resets = <&reset RESET_RTC>;
521 compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
522 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
523 clock-names = "clkin", "core";
524 amlogic,hhi-sysctrl = <&hhi>;
525 nvmem-cells = <&temperature_calib>;
526 nvmem-cell-names = "temperature_calib";
530 compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
531 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
532 clock-names = "core", "clkin";
536 clocks = <&xtal>, <&clkc CLKID_CLK81>;
537 clock-names = "xtal", "pclk";
541 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
542 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
543 clock-names = "baud", "xtal", "pclk";
547 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
548 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
549 clock-names = "baud", "xtal", "pclk";
553 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
554 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
555 clock-names = "baud", "xtal", "pclk";
559 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
560 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
561 clock-names = "baud", "xtal", "pclk";
565 compatible = "amlogic,meson8b-usb", "snps,dwc2";
566 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
571 compatible = "amlogic,meson8b-usb", "snps,dwc2";
572 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
577 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
578 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
579 clock-names = "usb_general", "usb";
580 resets = <&reset RESET_USB_OTG>;
584 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
585 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
586 clock-names = "usb_general", "usb";
587 resets = <&reset RESET_USB_OTG>;
591 compatible = "amlogic,meson8b-wdt";