1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
8 #include <dt-bindings/clock/meson8b-clkc.h>
9 #include <dt-bindings/gpio/meson8b-gpio.h>
10 #include <dt-bindings/power/meson8-power.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
13 #include <dt-bindings/thermal/thermal.h>
23 compatible = "arm,cortex-a5";
24 next-level-cache = <&L2>;
26 enable-method = "amlogic,meson8b-smp";
27 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
28 operating-points-v2 = <&cpu_opp_table>;
29 clocks = <&clkc CLKID_CPUCLK>;
30 #cooling-cells = <2>; /* min followed by max */
35 compatible = "arm,cortex-a5";
36 next-level-cache = <&L2>;
38 enable-method = "amlogic,meson8b-smp";
39 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
40 operating-points-v2 = <&cpu_opp_table>;
41 clocks = <&clkc CLKID_CPUCLK>;
42 #cooling-cells = <2>; /* min followed by max */
47 compatible = "arm,cortex-a5";
48 next-level-cache = <&L2>;
50 enable-method = "amlogic,meson8b-smp";
51 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
52 operating-points-v2 = <&cpu_opp_table>;
53 clocks = <&clkc CLKID_CPUCLK>;
54 #cooling-cells = <2>; /* min followed by max */
59 compatible = "arm,cortex-a5";
60 next-level-cache = <&L2>;
62 enable-method = "amlogic,meson8b-smp";
63 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
64 operating-points-v2 = <&cpu_opp_table>;
65 clocks = <&clkc CLKID_CPUCLK>;
66 #cooling-cells = <2>; /* min followed by max */
70 cpu_opp_table: opp-table {
71 compatible = "operating-points-v2";
75 opp-hz = /bits/ 64 <96000000>;
76 opp-microvolt = <860000>;
79 opp-hz = /bits/ 64 <192000000>;
80 opp-microvolt = <860000>;
83 opp-hz = /bits/ 64 <312000000>;
84 opp-microvolt = <860000>;
87 opp-hz = /bits/ 64 <408000000>;
88 opp-microvolt = <860000>;
91 opp-hz = /bits/ 64 <504000000>;
92 opp-microvolt = <860000>;
95 opp-hz = /bits/ 64 <600000000>;
96 opp-microvolt = <860000>;
99 opp-hz = /bits/ 64 <720000000>;
100 opp-microvolt = <860000>;
103 opp-hz = /bits/ 64 <816000000>;
104 opp-microvolt = <900000>;
107 opp-hz = /bits/ 64 <1008000000>;
108 opp-microvolt = <1140000>;
111 opp-hz = /bits/ 64 <1200000000>;
112 opp-microvolt = <1140000>;
115 opp-hz = /bits/ 64 <1320000000>;
116 opp-microvolt = <1140000>;
119 opp-hz = /bits/ 64 <1488000000>;
120 opp-microvolt = <1140000>;
123 opp-hz = /bits/ 64 <1536000000>;
124 opp-microvolt = <1140000>;
128 gpu_opp_table: gpu-opp-table {
129 compatible = "operating-points-v2";
132 opp-hz = /bits/ 64 <255000000>;
133 opp-microvolt = <1100000>;
136 opp-hz = /bits/ 64 <364285714>;
137 opp-microvolt = <1100000>;
140 opp-hz = /bits/ 64 <425000000>;
141 opp-microvolt = <1100000>;
144 opp-hz = /bits/ 64 <510000000>;
145 opp-microvolt = <1100000>;
148 opp-hz = /bits/ 64 <637500000>;
149 opp-microvolt = <1100000>;
155 compatible = "arm,cortex-a5-pmu";
156 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
160 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
164 #address-cells = <1>;
168 /* 2 MiB reserved for Hardware ROM Firmware? */
170 reg = <0x0 0x200000>;
177 polling-delay-passive = <250>; /* milliseconds */
178 polling-delay = <1000>; /* milliseconds */
179 thermal-sensors = <&thermal_sensor>;
183 trip = <&soc_passive>;
184 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
185 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
186 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
187 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
188 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
193 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
194 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
195 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
196 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
197 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
202 soc_passive: soc-passive {
203 temperature = <80000>; /* millicelsius */
204 hysteresis = <2000>; /* millicelsius */
209 temperature = <90000>; /* millicelsius */
210 hysteresis = <2000>; /* millicelsius */
214 soc_critical: soc-critical {
215 temperature = <110000>; /* millicelsius */
216 hysteresis = <2000>; /* millicelsius */
223 mmcbus: bus@c8000000 {
224 compatible = "simple-bus";
225 reg = <0xc8000000 0x8000>;
226 #address-cells = <1>;
228 ranges = <0x0 0xc8000000 0x8000>;
230 ddr_clkc: clock-controller@400 {
231 compatible = "amlogic,meson8b-ddr-clkc";
234 clock-names = "xtal";
239 compatible = "simple-bus";
240 reg = <0x6000 0x400>;
241 #address-cells = <1>;
243 ranges = <0x0 0x6000 0x400>;
245 canvas: video-lut@48 {
246 compatible = "amlogic,meson8b-canvas",
254 compatible = "simple-bus";
255 reg = <0xd0000000 0x200000>;
256 #address-cells = <1>;
258 ranges = <0x0 0xd0000000 0x200000>;
261 compatible = "amlogic,meson8b-mali", "arm,mali-450";
262 reg = <0xc0000 0x40000>;
263 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
271 interrupt-names = "gp", "gpmmu", "pp", "pmu",
272 "pp0", "ppmmu0", "pp1", "ppmmu1";
273 resets = <&reset RESET_MALI>;
274 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
275 clock-names = "bus", "core";
276 operating-points-v2 = <&gpu_opp_table>;
277 #cooling-cells = <2>; /* min followed by max */
284 compatible = "amlogic,meson8b-pmu", "syscon";
288 pinctrl_aobus: pinctrl@84 {
289 compatible = "amlogic,meson8b-aobus-pinctrl";
291 #address-cells = <1>;
295 gpio_ao: ao-bank@14 {
299 reg-names = "mux", "pull", "gpio";
302 gpio-ranges = <&pinctrl_aobus 0 0 16>;
305 uart_ao_a_pins: uart_ao_a {
307 groups = "uart_tx_ao_a", "uart_rx_ao_a";
308 function = "uart_ao";
313 ir_recv_pins: remote {
315 groups = "remote_input";
324 compatible= "amlogic,meson8b-ao-arc", "amlogic,meson-mx-ao-arc";
325 amlogic,secbus2 = <&secbus2>;
326 sram = <&ao_arc_sram>;
327 resets = <&reset RESET_MEDIA_CPU>;
328 clocks = <&clkc CLKID_AO_MEDIA_CPU>;
332 reset: reset-controller@4404 {
333 compatible = "amlogic,meson8b-reset";
338 analog_top: analog-top@81a8 {
339 compatible = "amlogic,meson8b-analog-top", "syscon";
344 compatible = "amlogic,meson8b-pwm";
351 compatible = "amlogic,meson8b-clk-measure";
355 pinctrl_cbus: pinctrl@9880 {
356 compatible = "amlogic,meson8b-cbus-pinctrl";
358 #address-cells = <1>;
367 reg-names = "mux", "pull", "pull-enable", "gpio";
370 gpio-ranges = <&pinctrl_cbus 0 0 83>;
373 eth_rgmii_pins: eth-rgmii {
375 groups = "eth_tx_clk",
390 function = "ethernet";
395 eth_rmii_pins: eth-rmii {
397 groups = "eth_tx_en",
406 function = "ethernet";
413 groups = "i2c_sda_a", "i2c_sck_a";
421 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
422 "sd_d3_b", "sd_clk_b", "sd_cmd_b";
428 sdxc_c_pins: sdxc-c {
430 groups = "sdxc_d0_c", "sdxc_d13_c",
431 "sdxc_d47_c", "sdxc_clk_c",
438 pwm_c1_pins: pwm-c1 {
454 uart_b0_pins: uart-b0 {
456 groups = "uart_tx_b0",
463 uart_b0_cts_rts_pins: uart-b0-cts-rts {
465 groups = "uart_cts_b0",
475 ao_arc_sram: ao-arc-sram@0 {
476 compatible = "amlogic,meson8b-ao-arc-sram";
482 compatible = "amlogic,meson8b-smp-sram";
489 compatible = "amlogic,meson8b-efuse";
490 clocks = <&clkc CLKID_EFUSE>;
491 clock-names = "core";
493 temperature_calib: calib@1f4 {
494 /* only the upper two bytes are relevant */
500 compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
502 reg = <0xc9410000 0x10000
505 clocks = <&clkc CLKID_ETH>,
508 <&clkc CLKID_FCLK_DIV2>;
509 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
510 rx-fifo-depth = <4096>;
511 tx-fifo-depth = <2048>;
513 resets = <&reset RESET_ETHERNET>;
514 reset-names = "stmmaceth";
516 power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
520 compatible = "amlogic,meson-gpio-intc",
521 "amlogic,meson8b-gpio-intc";
526 clkc: clock-controller {
527 compatible = "amlogic,meson8b-clkc";
528 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
529 clock-names = "xtal", "ddr_pll";
534 pwrc: power-controller {
535 compatible = "amlogic,meson8b-pwrc";
536 #power-domain-cells = <1>;
537 amlogic,ao-sysctrl = <&pmu>;
538 resets = <&reset RESET_DBLK>,
539 <&reset RESET_PIC_DC>,
540 <&reset RESET_HDMI_APB>,
541 <&reset RESET_HDMI_SYSTEM_RESET>,
542 <&reset RESET_VENCI>,
543 <&reset RESET_VENCP>,
544 <&reset RESET_VDAC_4>,
545 <&reset RESET_VENCL>,
549 reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system",
550 "venci", "vencp", "vdac", "vencl", "viu",
552 clocks = <&clkc CLKID_VPU>;
554 assigned-clocks = <&clkc CLKID_VPU>;
555 assigned-clock-rates = <182142857>;
560 compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
561 clocks = <&clkc CLKID_RNG0>;
562 clock-names = "core";
566 clocks = <&clkc CLKID_CLK81>;
570 clocks = <&clkc CLKID_I2C>;
574 clocks = <&clkc CLKID_I2C>;
578 arm,data-latency = <3 3 3>;
579 arm,tag-latency = <2 2 2>;
580 arm,filter-ranges = <0x100000 0xc0000000>;
582 prefetch-instr = <1>;
588 compatible = "arm,cortex-a5-scu";
593 compatible = "arm,cortex-a5-global-timer";
595 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
596 clocks = <&clkc CLKID_PERIPH>;
599 * the arm_global_timer driver currently does not handle clock
600 * rate changes. Keep it disabled for now.
606 compatible = "arm,cortex-a5-twd-timer";
608 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
609 clocks = <&clkc CLKID_PERIPH>;
614 compatible = "amlogic,meson8b-pwm";
618 compatible = "amlogic,meson8b-pwm";
622 compatible = "amlogic,meson8b-rtc";
623 resets = <&reset RESET_RTC>;
627 compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
628 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
629 clock-names = "clkin", "core";
630 amlogic,hhi-sysctrl = <&hhi>;
631 nvmem-cells = <&temperature_calib>;
632 nvmem-cell-names = "temperature_calib";
636 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
638 <&clkc CLKID_FCLK_DIV4>,
639 <&clkc CLKID_FCLK_DIV3>,
640 <&clkc CLKID_FCLK_DIV5>,
642 clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
646 secbus2: system-controller@4000 {
647 compatible = "amlogic,meson8b-secbus2", "syscon";
648 reg = <0x4000 0x2000>;
653 compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
654 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
655 clock-names = "core", "clkin";
659 clocks = <&xtal>, <&clkc CLKID_CLK81>;
660 clock-names = "xtal", "pclk";
664 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
665 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
666 clock-names = "baud", "xtal", "pclk";
670 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
671 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
672 clock-names = "baud", "xtal", "pclk";
676 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
677 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
678 clock-names = "baud", "xtal", "pclk";
682 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
683 clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
684 clock-names = "baud", "xtal", "pclk";
688 compatible = "amlogic,meson8b-usb", "snps,dwc2";
689 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
694 compatible = "amlogic,meson8b-usb", "snps,dwc2";
695 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
700 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
701 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
702 clock-names = "usb_general", "usb";
703 resets = <&reset RESET_USB_OTG>;
707 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
708 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
709 clock-names = "usb_general", "usb";
710 resets = <&reset RESET_USB_OTG>;
714 compatible = "amlogic,meson8b-wdt";