arch/arm/boot/dts/meson8.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright 2014 Carlo Caione <carlo@caione.org>
   4  */
   5
   6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
   7 #include <dt-bindings/clock/meson8b-clkc.h>
   8 #include <dt-bindings/gpio/meson8-gpio.h>
   9 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
  10 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
  11 #include "meson.dtsi"
  12
  13 / {
  14         model = "Amlogic Meson8 SoC";
  15         compatible = "amlogic,meson8";
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 cpu0: cpu@200 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a9";
  24                         next-level-cache = <&L2>;
  25                         reg = <0x200>;
  26                         enable-method = "amlogic,meson8-smp";
  27                         resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
  28                         operating-points-v2 = <&cpu_opp_table>;
  29                         clocks = <&clkc CLKID_CPUCLK>;
  30                 };
  31
  32                 cpu1: cpu@201 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a9";
  35                         next-level-cache = <&L2>;
  36                         reg = <0x201>;
  37                         enable-method = "amlogic,meson8-smp";
  38                         resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
  39                         operating-points-v2 = <&cpu_opp_table>;
  40                         clocks = <&clkc CLKID_CPUCLK>;
  41                 };
  42
  43                 cpu2: cpu@202 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a9";
  46                         next-level-cache = <&L2>;
  47                         reg = <0x202>;
  48                         enable-method = "amlogic,meson8-smp";
  49                         resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
  50                         operating-points-v2 = <&cpu_opp_table>;
  51                         clocks = <&clkc CLKID_CPUCLK>;
  52                 };
  53
  54                 cpu3: cpu@203 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a9";
  57                         next-level-cache = <&L2>;
  58                         reg = <0x203>;
  59                         enable-method = "amlogic,meson8-smp";
  60                         resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
  61                         operating-points-v2 = <&cpu_opp_table>;
  62                         clocks = <&clkc CLKID_CPUCLK>;
  63                 };
  64         };
  65
  66         cpu_opp_table: opp-table {
  67                 compatible = "operating-points-v2";
  68                 opp-shared;
  69
  70                 opp-96000000 {
  71                         opp-hz = /bits/ 64 <96000000>;
  72                         opp-microvolt = <825000>;
  73                 };
  74                 opp-192000000 {
  75                         opp-hz = /bits/ 64 <192000000>;
  76                         opp-microvolt = <825000>;
  77                 };
  78                 opp-312000000 {
  79                         opp-hz = /bits/ 64 <312000000>;
  80                         opp-microvolt = <825000>;
  81                 };
  82                 opp-408000000 {
  83                         opp-hz = /bits/ 64 <408000000>;
  84                         opp-microvolt = <825000>;
  85                 };
  86                 opp-504000000 {
  87                         opp-hz = /bits/ 64 <504000000>;
  88                         opp-microvolt = <825000>;
  89                 };
  90                 opp-600000000 {
  91                         opp-hz = /bits/ 64 <600000000>;
  92                         opp-microvolt = <850000>;
  93                 };
  94                 opp-720000000 {
  95                         opp-hz = /bits/ 64 <720000000>;
  96                         opp-microvolt = <850000>;
  97                 };
  98                 opp-816000000 {
  99                         opp-hz = /bits/ 64 <816000000>;
 100                         opp-microvolt = <875000>;
 101                 };
 102                 opp-1008000000 {
 103                         opp-hz = /bits/ 64 <1008000000>;
 104                         opp-microvolt = <925000>;
 105                 };
 106                 opp-1200000000 {
 107                         opp-hz = /bits/ 64 <1200000000>;
 108                         opp-microvolt = <975000>;
 109                 };
 110                 opp-1416000000 {
 111                         opp-hz = /bits/ 64 <1416000000>;
 112                         opp-microvolt = <1025000>;
 113                 };
 114                 opp-1608000000 {
 115                         opp-hz = /bits/ 64 <1608000000>;
 116                         opp-microvolt = <1100000>;
 117                 };
 118                 opp-1800000000 {
 119                         status = "disabled";
 120                         opp-hz = /bits/ 64 <1800000000>;
 121                         opp-microvolt = <1125000>;
 122                 };
 123                 opp-1992000000 {
 124                         status = "disabled";
 125                         opp-hz = /bits/ 64 <1992000000>;
 126                         opp-microvolt = <1150000>;
 127                 };
 128         };
 129
 130         gpu_opp_table: gpu-opp-table {
 131                 compatible = "operating-points-v2";
 132
 133                 opp-182142857 {
 134                         opp-hz = /bits/ 64 <182142857>;
 135                         opp-microvolt = <1150000>;
 136                 };
 137                 opp-318750000 {
 138                         opp-hz = /bits/ 64 <318750000>;
 139                         opp-microvolt = <1150000>;
 140                 };
 141                 opp-425000000 {
 142                         opp-hz = /bits/ 64 <425000000>;
 143                         opp-microvolt = <1150000>;
 144                 };
 145                 opp-510000000 {
 146                         opp-hz = /bits/ 64 <510000000>;
 147                         opp-microvolt = <1150000>;
 148                 };
 149                 opp-637500000 {
 150                         opp-hz = /bits/ 64 <637500000>;
 151                         opp-microvolt = <1150000>;
 152                         turbo-mode;
 153                 };
 154         };
 155
 156         pmu {
 157                 compatible = "arm,cortex-a9-pmu";
 158                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 159                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 160                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 161                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 162                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 163         };
 164
 165         reserved-memory {
 166                 #address-cells = <1>;
 167                 #size-cells = <1>;
 168                 ranges;
 169
 170                 /* 2 MiB reserved for Hardware ROM Firmware? */
 171                 hwrom@0 {
 172                         reg = <0x0 0x200000>;
 173                         no-map;
 174                 };
 175
 176                 /*
 177                  * 1 MiB reserved for the "ARM Power Firmware": this is ARM
 178                  * code which is responsible for system suspend. It loads a
 179                  * piece of ARC code ("arc_power" in the vendor u-boot tree)
 180                  * into SRAM, executes that and shuts down the (last) ARM core.
 181                  * The arc_power firmware then checks various wakeup sources
 182                  * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
 183                  * simply the power key) and re-starts the ARM core once it
 184                  * detects a wakeup request.
 185                  */
 186                 power-firmware@4f00000 {
 187                         reg = <0x4f00000 0x100000>;
 188                         no-map;
 189                 };
 190         };
 191
 192         mmcbus: bus@c8000000 {
 193                 compatible = "simple-bus";
 194                 reg = <0xc8000000 0x8000>;
 195                 #address-cells = <1>;
 196                 #size-cells = <1>;
 197                 ranges = <0x0 0xc8000000 0x8000>;
 198
 199                 ddr_clkc: clock-controller@400 {
 200                         compatible = "amlogic,meson8-ddr-clkc";
 201                         reg = <0x400 0x20>;
 202                         clocks = <&xtal>;
 203                         clock-names = "xtal";
 204                         #clock-cells = <1>;
 205                 };
 206
 207                 dmcbus: bus@6000 {
 208                         compatible = "simple-bus";
 209                         reg = <0x6000 0x400>;
 210                         #address-cells = <1>;
 211                         #size-cells = <1>;
 212                         ranges = <0x0 0x6000 0x400>;
 213
 214                         canvas: video-lut@20 {
 215                                 compatible = "amlogic,meson8-canvas",
 216                                              "amlogic,canvas";
 217                                 reg = <0x20 0x14>;
 218                         };
 219                 };
 220         };
 221
 222         apb: bus@d0000000 {
 223                 compatible = "simple-bus";
 224                 reg = <0xd0000000 0x200000>;
 225                 #address-cells = <1>;
 226                 #size-cells = <1>;
 227                 ranges = <0x0 0xd0000000 0x200000>;
 228
 229                 mali: gpu@c0000 {
 230                         compatible = "amlogic,meson8-mali", "arm,mali-450";
 231                         reg = <0xc0000 0x40000>;
 232                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 233                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 234                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 235                                      <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 236                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 237                                      <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 238                                      <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
 239                                      <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 240                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 241                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 242                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 243                                      <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 244                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
 245                                      <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
 247                                      <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
 248                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 249                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 250                         interrupt-names = "gp", "gpmmu", "pp", "pmu",
 251                                           "pp0", "ppmmu0", "pp1", "ppmmu1",
 252                                           "pp2", "ppmmu2", "pp4", "ppmmu4",
 253                                           "pp5", "ppmmu5", "pp6", "ppmmu6";
 254                         resets = <&reset RESET_MALI>;
 255                         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
 256                         clock-names = "bus", "core";
 257                         operating-points-v2 = <&gpu_opp_table>;
 258                 };
 259         };
 260 }; /* end of / */
 261
 262 &aobus {
 263         pmu: pmu@e0 {
 264                 compatible = "amlogic,meson8-pmu", "syscon";
 265                 reg = <0xe0 0x18>;
 266         };
 267
 268         pinctrl_aobus: pinctrl@84 {
 269                 compatible = "amlogic,meson8-aobus-pinctrl";
 270                 reg = <0x84 0xc>;
 271                 #address-cells = <1>;
 272                 #size-cells = <1>;
 273                 ranges;
 274
 275                 gpio_ao: ao-bank@14 {
 276                         reg = <0x14 0x4>,
 277                               <0x2c 0x4>,
 278                               <0x24 0x8>;
 279                         reg-names = "mux", "pull", "gpio";
 280                         gpio-controller;
 281                         #gpio-cells = <2>;
 282                         gpio-ranges = <&pinctrl_aobus 0 0 16>;
 283                 };
 284
 285                 uart_ao_a_pins: uart_ao_a {
 286                         mux {
 287                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 288                                 function = "uart_ao";
 289                                 bias-disable;
 290                         };
 291                 };
 292
 293                 i2c_ao_pins: i2c_mst_ao {
 294                         mux {
 295                                 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
 296                                 function = "i2c_mst_ao";
 297                                 bias-disable;
 298                         };
 299                 };
 300
 301                 ir_recv_pins: remote {
 302                         mux {
 303                                 groups = "remote_input";
 304                                 function = "remote";
 305                                 bias-disable;
 306                         };
 307                 };
 308
 309                 pwm_f_ao_pins: pwm-f-ao {
 310                         mux {
 311                                 groups = "pwm_f_ao";
 312                                 function = "pwm_f_ao";
 313                                 bias-disable;
 314                         };
 315                 };
 316         };
 317 };
 318
 319 &cbus {
 320         reset: reset-controller@4404 {
 321                 compatible = "amlogic,meson8b-reset";
 322                 reg = <0x4404 0x9c>;
 323                 #reset-cells = <1>;
 324         };
 325
 326         analog_top: analog-top@81a8 {
 327                 compatible = "amlogic,meson8-analog-top", "syscon";
 328                 reg = <0x81a8 0x14>;
 329         };
 330
 331         pwm_ef: pwm@86c0 {
 332                 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 333                 reg = <0x86c0 0x10>;
 334                 #pwm-cells = <3>;
 335                 status = "disabled";
 336         };
 337
 338         clock-measure@8758 {
 339                 compatible = "amlogic,meson8-clk-measure";
 340                 reg = <0x8758 0x1c>;
 341         };
 342
 343         pinctrl_cbus: pinctrl@9880 {
 344                 compatible = "amlogic,meson8-cbus-pinctrl";
 345                 reg = <0x9880 0x10>;
 346                 #address-cells = <1>;
 347                 #size-cells = <1>;
 348                 ranges;
 349
 350                 gpio: banks@80b0 {
 351                         reg = <0x80b0 0x28>,
 352                               <0x80e8 0x18>,
 353                               <0x8120 0x18>,
 354                               <0x8030 0x30>;
 355                         reg-names = "mux", "pull", "pull-enable", "gpio";
 356                         gpio-controller;
 357                         #gpio-cells = <2>;
 358                         gpio-ranges = <&pinctrl_cbus 0 0 120>;
 359                 };
 360
 361                 sd_a_pins: sd-a {
 362                         mux {
 363                                 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
 364                                         "sd_d3_a", "sd_clk_a", "sd_cmd_a";
 365                                 function = "sd_a";
 366                                 bias-disable;
 367                         };
 368                 };
 369
 370                 sd_b_pins: sd-b {
 371                         mux {
 372                                 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
 373                                         "sd_d3_b", "sd_clk_b", "sd_cmd_b";
 374                                 function = "sd_b";
 375                                 bias-disable;
 376                         };
 377                 };
 378
 379                 sd_c_pins: sd-c {
 380                         mux {
 381                                 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
 382                                         "sd_d3_c", "sd_clk_c", "sd_cmd_c";
 383                                 function = "sd_c";
 384                                 bias-disable;
 385                         };
 386                 };
 387
 388                 spi_nor_pins: nor {
 389                         mux {
 390                                 groups = "nor_d", "nor_q", "nor_c", "nor_cs";
 391                                 function = "nor";
 392                                 bias-disable;
 393                         };
 394                 };
 395
 396                 eth_pins: ethernet {
 397                         mux {
 398                                 groups = "eth_tx_clk_50m", "eth_tx_en",
 399                                          "eth_txd1", "eth_txd0",
 400                                          "eth_rx_clk_in", "eth_rx_dv",
 401                                          "eth_rxd1", "eth_rxd0", "eth_mdio",
 402                                          "eth_mdc";
 403                                 function = "ethernet";
 404                                 bias-disable;
 405                         };
 406                 };
 407
 408                 pwm_e_pins: pwm-e {
 409                         mux {
 410                                 groups = "pwm_e";
 411                                 function = "pwm_e";
 412                                 bias-disable;
 413                         };
 414                 };
 415
 416                 uart_a1_pins: uart-a1 {
 417                         mux {
 418                                 groups = "uart_tx_a1",
 419                                        "uart_rx_a1";
 420                                 function = "uart_a";
 421                                 bias-disable;
 422                         };
 423                 };
 424
 425                 uart_a1_cts_rts_pins: uart-a1-cts-rts {
 426                         mux {
 427                                 groups = "uart_cts_a1",
 428                                        "uart_rts_a1";
 429                                 function = "uart_a";
 430                                 bias-disable;
 431                         };
 432                 };
 433         };
 434 };
 435
 436 &ahb_sram {
 437         smp-sram@1ff80 {
 438                 compatible = "amlogic,meson8-smp-sram";
 439                 reg = <0x1ff80 0x8>;
 440         };
 441 };
 442
 443 &efuse {
 444         compatible = "amlogic,meson8-efuse";
 445         clocks = <&clkc CLKID_EFUSE>;
 446         clock-names = "core";
 447
 448         temperature_calib: calib@1f4 {
 449                 /* only the upper two bytes are relevant */
 450                 reg = <0x1f4 0x4>;
 451         };
 452 };
 453
 454 &ethmac {
 455         clocks = <&clkc CLKID_ETH>;
 456         clock-names = "stmmaceth";
 457 };
 458
 459 &gpio_intc {
 460         compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
 461         status = "okay";
 462 };
 463
 464 &hhi {
 465         clkc: clock-controller {
 466                 compatible = "amlogic,meson8-clkc";
 467                 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
 468                 clock-names = "xtal", "ddr_pll";
 469                 #clock-cells = <1>;
 470                 #reset-cells = <1>;
 471         };
 472 };
 473
 474 &hwrng {
 475         compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
 476         clocks = <&clkc CLKID_RNG0>;
 477         clock-names = "core";
 478 };
 479
 480 &i2c_AO {
 481         clocks = <&clkc CLKID_CLK81>;
 482 };
 483
 484 &i2c_A {
 485         clocks = <&clkc CLKID_CLK81>;
 486 };
 487
 488 &i2c_B {
 489         clocks = <&clkc CLKID_CLK81>;
 490 };
 491
 492 &L2 {
 493         arm,data-latency = <3 3 3>;
 494         arm,tag-latency = <2 2 2>;
 495         arm,filter-ranges = <0x100000 0xc0000000>;
 496         prefetch-data = <1>;
 497         prefetch-instr = <1>;
 498         arm,shared-override;
 499 };
 500
 501 &periph {
 502         scu@0 {
 503                 compatible = "arm,cortex-a9-scu";
 504                 reg = <0x0 0x100>;
 505         };
 506
 507         timer@200 {
 508                 compatible = "arm,cortex-a9-global-timer";
 509                 reg = <0x200 0x20>;
 510                 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 511                 clocks = <&clkc CLKID_PERIPH>;
 512
 513                 /*
 514                  * the arm_global_timer driver currently does not handle clock
 515                  * rate changes. Keep it disabled for now.
 516                  */
 517                 status = "disabled";
 518         };
 519
 520         timer@600 {
 521                 compatible = "arm,cortex-a9-twd-timer";
 522                 reg = <0x600 0x20>;
 523                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 524                 clocks = <&clkc CLKID_PERIPH>;
 525         };
 526 };
 527
 528 &pwm_ab {
 529         compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 530 };
 531
 532 &pwm_cd {
 533         compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 534 };
 535
 536 &rtc {
 537         compatible = "amlogic,meson8-rtc";
 538         resets = <&reset RESET_RTC>;
 539 };
 540
 541 &saradc {
 542         compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
 543         clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
 544         clock-names = "clkin", "core";
 545         amlogic,hhi-sysctrl = <&hhi>;
 546         nvmem-cells = <&temperature_calib>;
 547         nvmem-cell-names = "temperature_calib";
 548 };
 549
 550 &sdio {
 551         compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
 552         clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
 553         clock-names = "core", "clkin";
 554 };
 555
 556 &spifc {
 557         clocks = <&clkc CLKID_CLK81>;
 558 };
 559
 560 &timer_abcde {
 561         clocks = <&xtal>, <&clkc CLKID_CLK81>;
 562         clock-names = "xtal", "pclk";
 563 };
 564
 565 &uart_AO {
 566         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 567         clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
 568         clock-names = "baud", "xtal", "pclk";
 569 };
 570
 571 &uart_A {
 572         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 573         clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
 574         clock-names = "baud", "xtal", "pclk";
 575 };
 576
 577 &uart_B {
 578         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 579         clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
 580         clock-names = "baud", "xtal", "pclk";
 581 };
 582
 583 &uart_C {
 584         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 585         clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
 586         clock-names = "baud", "xtal", "pclk";
 587 };
 588
 589 &usb0 {
 590         compatible = "amlogic,meson8-usb", "snps,dwc2";
 591         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
 592         clock-names = "otg";
 593 };
 594
 595 &usb1 {
 596         compatible = "amlogic,meson8-usb", "snps,dwc2";
 597         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
 598         clock-names = "otg";
 599 };
 600
 601 &usb0_phy {
 602         compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
 603         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
 604         clock-names = "usb_general", "usb";
 605         resets = <&reset RESET_USB_OTG>;
 606 };
 607
 608 &usb1_phy {
 609         compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
 610         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
 611         clock-names = "usb_general", "usb";
 612         resets = <&reset RESET_USB_OTG>;
 613 };