arch/arm/boot/dts/meson8.dtsi

   1 /*
   2  * Copyright 2014 Carlo Caione <carlo@caione.org>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public License
  20  *     along with this program. If not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 #include <dt-bindings/clock/meson8b-clkc.h>
  47 #include <dt-bindings/gpio/meson8-gpio.h>
  48 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
  49 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
  50 #include "meson.dtsi"
  51
  52 / {
  53         model = "Amlogic Meson8 SoC";
  54         compatible = "amlogic,meson8";
  55
  56         cpus {
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 cpu0: cpu@200 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a9";
  63                         next-level-cache = <&L2>;
  64                         reg = <0x200>;
  65                         enable-method = "amlogic,meson8-smp";
  66                         resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
  67                         operating-points-v2 = <&cpu_opp_table>;
  68                         clocks = <&clkc CLKID_CPUCLK>;
  69                 };
  70
  71                 cpu1: cpu@201 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a9";
  74                         next-level-cache = <&L2>;
  75                         reg = <0x201>;
  76                         enable-method = "amlogic,meson8-smp";
  77                         resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
  78                         operating-points-v2 = <&cpu_opp_table>;
  79                         clocks = <&clkc CLKID_CPUCLK>;
  80                 };
  81
  82                 cpu2: cpu@202 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a9";
  85                         next-level-cache = <&L2>;
  86                         reg = <0x202>;
  87                         enable-method = "amlogic,meson8-smp";
  88                         resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
  89                         operating-points-v2 = <&cpu_opp_table>;
  90                         clocks = <&clkc CLKID_CPUCLK>;
  91                 };
  92
  93                 cpu3: cpu@203 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a9";
  96                         next-level-cache = <&L2>;
  97                         reg = <0x203>;
  98                         enable-method = "amlogic,meson8-smp";
  99                         resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
 100                         operating-points-v2 = <&cpu_opp_table>;
 101                         clocks = <&clkc CLKID_CPUCLK>;
 102                 };
 103         };
 104
 105         cpu_opp_table: opp-table {
 106                 compatible = "operating-points-v2";
 107                 opp-shared;
 108
 109                 opp-96000000 {
 110                         opp-hz = /bits/ 64 <96000000>;
 111                         opp-microvolt = <825000>;
 112                 };
 113                 opp-192000000 {
 114                         opp-hz = /bits/ 64 <192000000>;
 115                         opp-microvolt = <825000>;
 116                 };
 117                 opp-312000000 {
 118                         opp-hz = /bits/ 64 <312000000>;
 119                         opp-microvolt = <825000>;
 120                 };
 121                 opp-408000000 {
 122                         opp-hz = /bits/ 64 <408000000>;
 123                         opp-microvolt = <825000>;
 124                 };
 125                 opp-504000000 {
 126                         opp-hz = /bits/ 64 <504000000>;
 127                         opp-microvolt = <825000>;
 128                 };
 129                 opp-600000000 {
 130                         opp-hz = /bits/ 64 <600000000>;
 131                         opp-microvolt = <850000>;
 132                 };
 133                 opp-720000000 {
 134                         opp-hz = /bits/ 64 <720000000>;
 135                         opp-microvolt = <850000>;
 136                 };
 137                 opp-816000000 {
 138                         opp-hz = /bits/ 64 <816000000>;
 139                         opp-microvolt = <875000>;
 140                 };
 141                 opp-1008000000 {
 142                         opp-hz = /bits/ 64 <1008000000>;
 143                         opp-microvolt = <925000>;
 144                 };
 145                 opp-1200000000 {
 146                         opp-hz = /bits/ 64 <1200000000>;
 147                         opp-microvolt = <975000>;
 148                 };
 149                 opp-1416000000 {
 150                         opp-hz = /bits/ 64 <1416000000>;
 151                         opp-microvolt = <1025000>;
 152                 };
 153                 opp-1608000000 {
 154                         opp-hz = /bits/ 64 <1608000000>;
 155                         opp-microvolt = <1100000>;
 156                 };
 157                 opp-1800000000 {
 158                         status = "disabled";
 159                         opp-hz = /bits/ 64 <1800000000>;
 160                         opp-microvolt = <1125000>;
 161                 };
 162                 opp-1992000000 {
 163                         status = "disabled";
 164                         opp-hz = /bits/ 64 <1992000000>;
 165                         opp-microvolt = <1150000>;
 166                 };
 167         };
 168
 169         gpu_opp_table: gpu-opp-table {
 170                 compatible = "operating-points-v2";
 171
 172                 opp-182150000 {
 173                         opp-hz = /bits/ 64 <182150000>;
 174                         opp-microvolt = <1150000>;
 175                 };
 176                 opp-318750000 {
 177                         opp-hz = /bits/ 64 <318750000>;
 178                         opp-microvolt = <1150000>;
 179                 };
 180                 opp-425000000 {
 181                         opp-hz = /bits/ 64 <425000000>;
 182                         opp-microvolt = <1150000>;
 183                 };
 184                 opp-510000000 {
 185                         opp-hz = /bits/ 64 <510000000>;
 186                         opp-microvolt = <1150000>;
 187                 };
 188                 opp-637500000 {
 189                         opp-hz = /bits/ 64 <637500000>;
 190                         opp-microvolt = <1150000>;
 191                         turbo-mode;
 192                 };
 193         };
 194
 195         pmu {
 196                 compatible = "arm,cortex-a9-pmu";
 197                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 201                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 202         };
 203
 204         reserved-memory {
 205                 #address-cells = <1>;
 206                 #size-cells = <1>;
 207                 ranges;
 208
 209                 /* 2 MiB reserved for Hardware ROM Firmware? */
 210                 hwrom@0 {
 211                         reg = <0x0 0x200000>;
 212                         no-map;
 213                 };
 214
 215                 /*
 216                  * 1 MiB reserved for the "ARM Power Firmware": this is ARM
 217                  * code which is responsible for system suspend. It loads a
 218                  * piece of ARC code ("arc_power" in the vendor u-boot tree)
 219                  * into SRAM, executes that and shuts down the (last) ARM core.
 220                  * The arc_power firmware then checks various wakeup sources
 221                  * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
 222                  * simply the power key) and re-starts the ARM core once it
 223                  * detects a wakeup request.
 224                  */
 225                 power-firmware@4f00000 {
 226                         reg = <0x4f00000 0x100000>;
 227                         no-map;
 228                 };
 229         };
 230
 231         apb: bus@d0000000 {
 232                 compatible = "simple-bus";
 233                 reg = <0xd0000000 0x200000>;
 234                 #address-cells = <1>;
 235                 #size-cells = <1>;
 236                 ranges = <0x0 0xd0000000 0x200000>;
 237
 238                 mali: gpu@c0000 {
 239                         compatible = "amlogic,meson8-mali", "arm,mali-450";
 240                         reg = <0xc0000 0x40000>;
 241                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 242                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 243                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 244                                      <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 245                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 247                                      <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
 248                                      <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 249                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 250                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 251                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
 252                                      <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 253                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
 254                                      <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 255                                      <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
 256                                      <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
 257                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 258                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 259                         interrupt-names = "gp", "gpmmu", "pp", "pmu",
 260                                           "pp0", "ppmmu0", "pp1", "ppmmu1",
 261                                           "pp2", "ppmmu2", "pp4", "ppmmu4",
 262                                           "pp5", "ppmmu5", "pp6", "ppmmu6";
 263                         resets = <&reset RESET_MALI>;
 264                         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
 265                         clock-names = "bus", "core";
 266                         operating-points-v2 = <&gpu_opp_table>;
 267                         switch-delay = <0xffff>;
 268                 };
 269         };
 270 }; /* end of / */
 271
 272 &aobus {
 273         pmu: pmu@e0 {
 274                 compatible = "amlogic,meson8-pmu", "syscon";
 275                 reg = <0xe0 0x8>;
 276         };
 277
 278         pinctrl_aobus: pinctrl@84 {
 279                 compatible = "amlogic,meson8-aobus-pinctrl";
 280                 reg = <0x84 0xc>;
 281                 #address-cells = <1>;
 282                 #size-cells = <1>;
 283                 ranges;
 284
 285                 gpio_ao: ao-bank@14 {
 286                         reg = <0x14 0x4>,
 287                               <0x2c 0x4>,
 288                               <0x24 0x8>;
 289                         reg-names = "mux", "pull", "gpio";
 290                         gpio-controller;
 291                         #gpio-cells = <2>;
 292                         gpio-ranges = <&pinctrl_aobus 0 0 16>;
 293                 };
 294
 295                 uart_ao_a_pins: uart_ao_a {
 296                         mux {
 297                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 298                                 function = "uart_ao";
 299                                 bias-disable;
 300                         };
 301                 };
 302
 303                 i2c_ao_pins: i2c_mst_ao {
 304                         mux {
 305                                 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
 306                                 function = "i2c_mst_ao";
 307                                 bias-disable;
 308                         };
 309                 };
 310
 311                 ir_recv_pins: remote {
 312                         mux {
 313                                 groups = "remote_input";
 314                                 function = "remote";
 315                                 bias-disable;
 316                         };
 317                 };
 318
 319                 pwm_f_ao_pins: pwm-f-ao {
 320                         mux {
 321                                 groups = "pwm_f_ao";
 322                                 function = "pwm_f_ao";
 323                                 bias-disable;
 324                         };
 325                 };
 326         };
 327 };
 328
 329 &cbus {
 330         reset: reset-controller@4404 {
 331                 compatible = "amlogic,meson8b-reset";
 332                 reg = <0x4404 0x9c>;
 333                 #reset-cells = <1>;
 334         };
 335
 336         analog_top: analog-top@81a8 {
 337                 compatible = "amlogic,meson8-analog-top", "syscon";
 338                 reg = <0x81a8 0x14>;
 339         };
 340
 341         pwm_ef: pwm@86c0 {
 342                 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 343                 reg = <0x86c0 0x10>;
 344                 #pwm-cells = <3>;
 345                 status = "disabled";
 346         };
 347
 348         clock-measure@8758 {
 349                 compatible = "amlogic,meson8-clk-measure";
 350                 reg = <0x8758 0x1c>;
 351         };
 352
 353         pinctrl_cbus: pinctrl@9880 {
 354                 compatible = "amlogic,meson8-cbus-pinctrl";
 355                 reg = <0x9880 0x10>;
 356                 #address-cells = <1>;
 357                 #size-cells = <1>;
 358                 ranges;
 359
 360                 gpio: banks@80b0 {
 361                         reg = <0x80b0 0x28>,
 362                               <0x80e8 0x18>,
 363                               <0x8120 0x18>,
 364                               <0x8030 0x30>;
 365                         reg-names = "mux", "pull", "pull-enable", "gpio";
 366                         gpio-controller;
 367                         #gpio-cells = <2>;
 368                         gpio-ranges = <&pinctrl_cbus 0 0 120>;
 369                 };
 370
 371                 sd_a_pins: sd-a {
 372                         mux {
 373                                 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
 374                                         "sd_d3_a", "sd_clk_a", "sd_cmd_a";
 375                                 function = "sd_a";
 376                                 bias-disable;
 377                         };
 378                 };
 379
 380                 sd_b_pins: sd-b {
 381                         mux {
 382                                 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
 383                                         "sd_d3_b", "sd_clk_b", "sd_cmd_b";
 384                                 function = "sd_b";
 385                                 bias-disable;
 386                         };
 387                 };
 388
 389                 sd_c_pins: sd-c {
 390                         mux {
 391                                 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
 392                                         "sd_d3_c", "sd_clk_c", "sd_cmd_c";
 393                                 function = "sd_c";
 394                                 bias-disable;
 395                         };
 396                 };
 397
 398                 spi_nor_pins: nor {
 399                         mux {
 400                                 groups = "nor_d", "nor_q", "nor_c", "nor_cs";
 401                                 function = "nor";
 402                                 bias-disable;
 403                         };
 404                 };
 405
 406                 eth_pins: ethernet {
 407                         mux {
 408                                 groups = "eth_tx_clk_50m", "eth_tx_en",
 409                                          "eth_txd1", "eth_txd0",
 410                                          "eth_rx_clk_in", "eth_rx_dv",
 411                                          "eth_rxd1", "eth_rxd0", "eth_mdio",
 412                                          "eth_mdc";
 413                                 function = "ethernet";
 414                                 bias-disable;
 415                         };
 416                 };
 417
 418                 pwm_e_pins: pwm-e {
 419                         mux {
 420                                 groups = "pwm_e";
 421                                 function = "pwm_e";
 422                                 bias-disable;
 423                         };
 424                 };
 425
 426                 uart_a1_pins: uart-a1 {
 427                         mux {
 428                                 groups = "uart_tx_a1",
 429                                        "uart_rx_a1";
 430                                 function = "uart_a";
 431                                 bias-disable;
 432                         };
 433                 };
 434
 435                 uart_a1_cts_rts_pins: uart-a1-cts-rts {
 436                         mux {
 437                                 groups = "uart_cts_a1",
 438                                        "uart_rts_a1";
 439                                 function = "uart_a";
 440                                 bias-disable;
 441                         };
 442                 };
 443         };
 444 };
 445
 446 &ahb_sram {
 447         smp-sram@1ff80 {
 448                 compatible = "amlogic,meson8-smp-sram";
 449                 reg = <0x1ff80 0x8>;
 450         };
 451 };
 452
 453 &efuse {
 454         compatible = "amlogic,meson8-efuse";
 455         clocks = <&clkc CLKID_EFUSE>;
 456         clock-names = "core";
 457
 458         temperature_calib: calib@1f4 {
 459                 /* only the upper two bytes are relevant */
 460                 reg = <0x1f4 0x4>;
 461         };
 462 };
 463
 464 &ethmac {
 465         clocks = <&clkc CLKID_ETH>;
 466         clock-names = "stmmaceth";
 467 };
 468
 469 &gpio_intc {
 470         compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
 471         status = "okay";
 472 };
 473
 474 &hhi {
 475         clkc: clock-controller {
 476                 compatible = "amlogic,meson8-clkc";
 477                 #clock-cells = <1>;
 478                 #reset-cells = <1>;
 479         };
 480 };
 481
 482 &hwrng {
 483         compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
 484         clocks = <&clkc CLKID_RNG0>;
 485         clock-names = "core";
 486 };
 487
 488 &i2c_AO {
 489         clocks = <&clkc CLKID_CLK81>;
 490 };
 491
 492 &i2c_A {
 493         clocks = <&clkc CLKID_CLK81>;
 494 };
 495
 496 &i2c_B {
 497         clocks = <&clkc CLKID_CLK81>;
 498 };
 499
 500 &L2 {
 501         arm,data-latency = <3 3 3>;
 502         arm,tag-latency = <2 2 2>;
 503         arm,filter-ranges = <0x100000 0xc0000000>;
 504         prefetch-data = <1>;
 505         prefetch-instr = <1>;
 506         arm,shared-override;
 507 };
 508
 509 &periph {
 510         scu@0 {
 511                 compatible = "arm,cortex-a9-scu";
 512                 reg = <0x0 0x100>;
 513         };
 514
 515         timer@200 {
 516                 compatible = "arm,cortex-a9-global-timer";
 517                 reg = <0x200 0x20>;
 518                 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 519                 clocks = <&clkc CLKID_PERIPH>;
 520
 521                 /*
 522                  * the arm_global_timer driver currently does not handle clock
 523                  * rate changes. Keep it disabled for now.
 524                  */
 525                 status = "disabled";
 526         };
 527
 528         timer@600 {
 529                 compatible = "arm,cortex-a9-twd-timer";
 530                 reg = <0x600 0x20>;
 531                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 532                 clocks = <&clkc CLKID_PERIPH>;
 533         };
 534 };
 535
 536 &pwm_ab {
 537         compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 538 };
 539
 540 &pwm_cd {
 541         compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 542 };
 543
 544 &rtc {
 545         compatible = "amlogic,meson8-rtc";
 546         resets = <&reset RESET_RTC>;
 547 };
 548
 549 &saradc {
 550         compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
 551         clocks = <&clkc CLKID_XTAL>,
 552                 <&clkc CLKID_SAR_ADC>;
 553         clock-names = "clkin", "core";
 554         amlogic,hhi-sysctrl = <&hhi>;
 555         nvmem-cells = <&temperature_calib>;
 556         nvmem-cell-names = "temperature_calib";
 557 };
 558
 559 &sdio {
 560         compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
 561         clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
 562         clock-names = "core", "clkin";
 563 };
 564
 565 &spifc {
 566         clocks = <&clkc CLKID_CLK81>;
 567 };
 568
 569 &timer_abcde {
 570         clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
 571         clock-names = "xtal", "pclk";
 572 };
 573
 574 &uart_AO {
 575         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 576         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
 577         clock-names = "baud", "xtal", "pclk";
 578 };
 579
 580 &uart_A {
 581         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 582         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
 583         clock-names = "baud", "xtal", "pclk";
 584 };
 585
 586 &uart_B {
 587         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 588         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
 589         clock-names = "baud", "xtal", "pclk";
 590 };
 591
 592 &uart_C {
 593         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 594         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
 595         clock-names = "baud", "xtal", "pclk";
 596 };
 597
 598 &usb0 {
 599         compatible = "amlogic,meson8-usb", "snps,dwc2";
 600         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
 601         clock-names = "otg";
 602 };
 603
 604 &usb1 {
 605         compatible = "amlogic,meson8-usb", "snps,dwc2";
 606         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
 607         clock-names = "otg";
 608 };
 609
 610 &usb0_phy {
 611         compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
 612         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
 613         clock-names = "usb_general", "usb";
 614         resets = <&reset RESET_USB_OTG>;
 615 };
 616
 617 &usb1_phy {
 618         compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
 619         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
 620         clock-names = "usb_general", "usb";
 621         resets = <&reset RESET_USB_OTG>;
 622 };