arch/arm/boot/dts/meson8.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright 2014 Carlo Caione <carlo@caione.org>
   4  */
   5
   6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
   7 #include <dt-bindings/clock/meson8b-clkc.h>
   8 #include <dt-bindings/gpio/meson8-gpio.h>
   9 #include <dt-bindings/power/meson8-power.h>
  10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
  11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
  12 #include "meson.dtsi"
  13
  14 / {
  15         model = "Amlogic Meson8 SoC";
  16         compatible = "amlogic,meson8";
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: cpu@200 {
  23                         device_type = "cpu";
  24                         compatible = "arm,cortex-a9";
  25                         next-level-cache = <&L2>;
  26                         reg = <0x200>;
  27                         enable-method = "amlogic,meson8-smp";
  28                         resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
  29                         operating-points-v2 = <&cpu_opp_table>;
  30                         clocks = <&clkc CLKID_CPUCLK>;
  31                 };
  32
  33                 cpu1: cpu@201 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a9";
  36                         next-level-cache = <&L2>;
  37                         reg = <0x201>;
  38                         enable-method = "amlogic,meson8-smp";
  39                         resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
  40                         operating-points-v2 = <&cpu_opp_table>;
  41                         clocks = <&clkc CLKID_CPUCLK>;
  42                 };
  43
  44                 cpu2: cpu@202 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a9";
  47                         next-level-cache = <&L2>;
  48                         reg = <0x202>;
  49                         enable-method = "amlogic,meson8-smp";
  50                         resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
  51                         operating-points-v2 = <&cpu_opp_table>;
  52                         clocks = <&clkc CLKID_CPUCLK>;
  53                 };
  54
  55                 cpu3: cpu@203 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a9";
  58                         next-level-cache = <&L2>;
  59                         reg = <0x203>;
  60                         enable-method = "amlogic,meson8-smp";
  61                         resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
  62                         operating-points-v2 = <&cpu_opp_table>;
  63                         clocks = <&clkc CLKID_CPUCLK>;
  64                 };
  65         };
  66
  67         cpu_opp_table: opp-table {
  68                 compatible = "operating-points-v2";
  69                 opp-shared;
  70
  71                 opp-96000000 {
  72                         opp-hz = /bits/ 64 <96000000>;
  73                         opp-microvolt = <825000>;
  74                 };
  75                 opp-192000000 {
  76                         opp-hz = /bits/ 64 <192000000>;
  77                         opp-microvolt = <825000>;
  78                 };
  79                 opp-312000000 {
  80                         opp-hz = /bits/ 64 <312000000>;
  81                         opp-microvolt = <825000>;
  82                 };
  83                 opp-408000000 {
  84                         opp-hz = /bits/ 64 <408000000>;
  85                         opp-microvolt = <825000>;
  86                 };
  87                 opp-504000000 {
  88                         opp-hz = /bits/ 64 <504000000>;
  89                         opp-microvolt = <825000>;
  90                 };
  91                 opp-600000000 {
  92                         opp-hz = /bits/ 64 <600000000>;
  93                         opp-microvolt = <850000>;
  94                 };
  95                 opp-720000000 {
  96                         opp-hz = /bits/ 64 <720000000>;
  97                         opp-microvolt = <850000>;
  98                 };
  99                 opp-816000000 {
 100                         opp-hz = /bits/ 64 <816000000>;
 101                         opp-microvolt = <875000>;
 102                 };
 103                 opp-1008000000 {
 104                         opp-hz = /bits/ 64 <1008000000>;
 105                         opp-microvolt = <925000>;
 106                 };
 107                 opp-1200000000 {
 108                         opp-hz = /bits/ 64 <1200000000>;
 109                         opp-microvolt = <975000>;
 110                 };
 111                 opp-1416000000 {
 112                         opp-hz = /bits/ 64 <1416000000>;
 113                         opp-microvolt = <1025000>;
 114                 };
 115                 opp-1608000000 {
 116                         opp-hz = /bits/ 64 <1608000000>;
 117                         opp-microvolt = <1100000>;
 118                 };
 119                 opp-1800000000 {
 120                         status = "disabled";
 121                         opp-hz = /bits/ 64 <1800000000>;
 122                         opp-microvolt = <1125000>;
 123                 };
 124                 opp-1992000000 {
 125                         status = "disabled";
 126                         opp-hz = /bits/ 64 <1992000000>;
 127                         opp-microvolt = <1150000>;
 128                 };
 129         };
 130
 131         gpu_opp_table: gpu-opp-table {
 132                 compatible = "operating-points-v2";
 133
 134                 opp-182142857 {
 135                         opp-hz = /bits/ 64 <182142857>;
 136                         opp-microvolt = <1150000>;
 137                 };
 138                 opp-318750000 {
 139                         opp-hz = /bits/ 64 <318750000>;
 140                         opp-microvolt = <1150000>;
 141                 };
 142                 opp-425000000 {
 143                         opp-hz = /bits/ 64 <425000000>;
 144                         opp-microvolt = <1150000>;
 145                 };
 146                 opp-510000000 {
 147                         opp-hz = /bits/ 64 <510000000>;
 148                         opp-microvolt = <1150000>;
 149                 };
 150                 opp-637500000 {
 151                         opp-hz = /bits/ 64 <637500000>;
 152                         opp-microvolt = <1150000>;
 153                         turbo-mode;
 154                 };
 155         };
 156
 157         pmu {
 158                 compatible = "arm,cortex-a9-pmu";
 159                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 160                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 161                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 162                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 163                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 164         };
 165
 166         reserved-memory {
 167                 #address-cells = <1>;
 168                 #size-cells = <1>;
 169                 ranges;
 170
 171                 /* 2 MiB reserved for Hardware ROM Firmware? */
 172                 hwrom@0 {
 173                         reg = <0x0 0x200000>;
 174                         no-map;
 175                 };
 176
 177                 /*
 178                  * 1 MiB reserved for the "ARM Power Firmware": this is ARM
 179                  * code which is responsible for system suspend. It loads a
 180                  * piece of ARC code ("arc_power" in the vendor u-boot tree)
 181                  * into SRAM, executes that and shuts down the (last) ARM core.
 182                  * The arc_power firmware then checks various wakeup sources
 183                  * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
 184                  * simply the power key) and re-starts the ARM core once it
 185                  * detects a wakeup request.
 186                  */
 187                 power-firmware@4f00000 {
 188                         reg = <0x4f00000 0x100000>;
 189                         no-map;
 190                 };
 191         };
 192
 193         mmcbus: bus@c8000000 {
 194                 compatible = "simple-bus";
 195                 reg = <0xc8000000 0x8000>;
 196                 #address-cells = <1>;
 197                 #size-cells = <1>;
 198                 ranges = <0x0 0xc8000000 0x8000>;
 199
 200                 ddr_clkc: clock-controller@400 {
 201                         compatible = "amlogic,meson8-ddr-clkc";
 202                         reg = <0x400 0x20>;
 203                         clocks = <&xtal>;
 204                         clock-names = "xtal";
 205                         #clock-cells = <1>;
 206                 };
 207
 208                 dmcbus: bus@6000 {
 209                         compatible = "simple-bus";
 210                         reg = <0x6000 0x400>;
 211                         #address-cells = <1>;
 212                         #size-cells = <1>;
 213                         ranges = <0x0 0x6000 0x400>;
 214
 215                         canvas: video-lut@20 {
 216                                 compatible = "amlogic,meson8-canvas",
 217                                              "amlogic,canvas";
 218                                 reg = <0x20 0x14>;
 219                         };
 220                 };
 221         };
 222
 223         apb: bus@d0000000 {
 224                 compatible = "simple-bus";
 225                 reg = <0xd0000000 0x200000>;
 226                 #address-cells = <1>;
 227                 #size-cells = <1>;
 228                 ranges = <0x0 0xd0000000 0x200000>;
 229
 230                 mali: gpu@c0000 {
 231                         compatible = "amlogic,meson8-mali", "arm,mali-450";
 232                         reg = <0xc0000 0x40000>;
 233                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 234                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 235                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 236                                      <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 237                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 238                                      <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 239                                      <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
 240                                      <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 241                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 242                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 243                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
 244                                      <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 245                                      <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
 247                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 248                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 249                         interrupt-names = "gp", "gpmmu", "pp", "pmu",
 250                                           "pp0", "ppmmu0", "pp1", "ppmmu1",
 251                                           "pp2", "ppmmu2", "pp4", "ppmmu4",
 252                                           "pp5", "ppmmu5", "pp6", "ppmmu6";
 253                         resets = <&reset RESET_MALI>;
 254                         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
 255                         clock-names = "bus", "core";
 256                         operating-points-v2 = <&gpu_opp_table>;
 257                 };
 258         };
 259 }; /* end of / */
 260
 261 &aobus {
 262         pmu: pmu@e0 {
 263                 compatible = "amlogic,meson8-pmu", "syscon";
 264                 reg = <0xe0 0x18>;
 265         };
 266
 267         pinctrl_aobus: pinctrl@84 {
 268                 compatible = "amlogic,meson8-aobus-pinctrl";
 269                 reg = <0x84 0xc>;
 270                 #address-cells = <1>;
 271                 #size-cells = <1>;
 272                 ranges;
 273
 274                 gpio_ao: ao-bank@14 {
 275                         reg = <0x14 0x4>,
 276                               <0x2c 0x4>,
 277                               <0x24 0x8>;
 278                         reg-names = "mux", "pull", "gpio";
 279                         gpio-controller;
 280                         #gpio-cells = <2>;
 281                         gpio-ranges = <&pinctrl_aobus 0 0 16>;
 282                 };
 283
 284                 uart_ao_a_pins: uart_ao_a {
 285                         mux {
 286                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 287                                 function = "uart_ao";
 288                                 bias-disable;
 289                         };
 290                 };
 291
 292                 i2c_ao_pins: i2c_mst_ao {
 293                         mux {
 294                                 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
 295                                 function = "i2c_mst_ao";
 296                                 bias-disable;
 297                         };
 298                 };
 299
 300                 ir_recv_pins: remote {
 301                         mux {
 302                                 groups = "remote_input";
 303                                 function = "remote";
 304                                 bias-disable;
 305                         };
 306                 };
 307
 308                 pwm_f_ao_pins: pwm-f-ao {
 309                         mux {
 310                                 groups = "pwm_f_ao";
 311                                 function = "pwm_f_ao";
 312                                 bias-disable;
 313                         };
 314                 };
 315         };
 316 };
 317
 318 &cbus {
 319         reset: reset-controller@4404 {
 320                 compatible = "amlogic,meson8b-reset";
 321                 reg = <0x4404 0x9c>;
 322                 #reset-cells = <1>;
 323         };
 324
 325         analog_top: analog-top@81a8 {
 326                 compatible = "amlogic,meson8-analog-top", "syscon";
 327                 reg = <0x81a8 0x14>;
 328         };
 329
 330         pwm_ef: pwm@86c0 {
 331                 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 332                 reg = <0x86c0 0x10>;
 333                 #pwm-cells = <3>;
 334                 status = "disabled";
 335         };
 336
 337         clock-measure@8758 {
 338                 compatible = "amlogic,meson8-clk-measure";
 339                 reg = <0x8758 0x1c>;
 340         };
 341
 342         pinctrl_cbus: pinctrl@9880 {
 343                 compatible = "amlogic,meson8-cbus-pinctrl";
 344                 reg = <0x9880 0x10>;
 345                 #address-cells = <1>;
 346                 #size-cells = <1>;
 347                 ranges;
 348
 349                 gpio: banks@80b0 {
 350                         reg = <0x80b0 0x28>,
 351                               <0x80e8 0x18>,
 352                               <0x8120 0x18>,
 353                               <0x8030 0x30>;
 354                         reg-names = "mux", "pull", "pull-enable", "gpio";
 355                         gpio-controller;
 356                         #gpio-cells = <2>;
 357                         gpio-ranges = <&pinctrl_cbus 0 0 120>;
 358                 };
 359
 360                 sd_a_pins: sd-a {
 361                         mux {
 362                                 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
 363                                         "sd_d3_a", "sd_clk_a", "sd_cmd_a";
 364                                 function = "sd_a";
 365                                 bias-disable;
 366                         };
 367                 };
 368
 369                 sd_b_pins: sd-b {
 370                         mux {
 371                                 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
 372                                         "sd_d3_b", "sd_clk_b", "sd_cmd_b";
 373                                 function = "sd_b";
 374                                 bias-disable;
 375                         };
 376                 };
 377
 378                 sd_c_pins: sd-c {
 379                         mux {
 380                                 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
 381                                         "sd_d3_c", "sd_clk_c", "sd_cmd_c";
 382                                 function = "sd_c";
 383                                 bias-disable;
 384                         };
 385                 };
 386
 387                 sdxc_b_pins: sdxc-b {
 388                         mux {
 389                                 groups = "sdxc_d0_b", "sdxc_d13_b",
 390                                          "sdxc_clk_b", "sdxc_cmd_b";
 391                                 function = "sdxc_b";
 392                                 bias-pull-up;
 393                         };
 394                 };
 395
 396                 spi_nor_pins: nor {
 397                         mux {
 398                                 groups = "nor_d", "nor_q", "nor_c", "nor_cs";
 399                                 function = "nor";
 400                                 bias-disable;
 401                         };
 402                 };
 403
 404                 eth_pins: ethernet {
 405                         mux {
 406                                 groups = "eth_tx_clk_50m", "eth_tx_en",
 407                                          "eth_txd1", "eth_txd0",
 408                                          "eth_rx_clk_in", "eth_rx_dv",
 409                                          "eth_rxd1", "eth_rxd0", "eth_mdio",
 410                                          "eth_mdc";
 411                                 function = "ethernet";
 412                                 bias-disable;
 413                         };
 414                 };
 415
 416                 pwm_e_pins: pwm-e {
 417                         mux {
 418                                 groups = "pwm_e";
 419                                 function = "pwm_e";
 420                                 bias-disable;
 421                         };
 422                 };
 423
 424                 uart_a1_pins: uart-a1 {
 425                         mux {
 426                                 groups = "uart_tx_a1",
 427                                        "uart_rx_a1";
 428                                 function = "uart_a";
 429                                 bias-disable;
 430                         };
 431                 };
 432
 433                 uart_a1_cts_rts_pins: uart-a1-cts-rts {
 434                         mux {
 435                                 groups = "uart_cts_a1",
 436                                        "uart_rts_a1";
 437                                 function = "uart_a";
 438                                 bias-disable;
 439                         };
 440                 };
 441         };
 442 };
 443
 444 &ahb_sram {
 445         smp-sram@1ff80 {
 446                 compatible = "amlogic,meson8-smp-sram";
 447                 reg = <0x1ff80 0x8>;
 448         };
 449 };
 450
 451 &efuse {
 452         compatible = "amlogic,meson8-efuse";
 453         clocks = <&clkc CLKID_EFUSE>;
 454         clock-names = "core";
 455
 456         temperature_calib: calib@1f4 {
 457                 /* only the upper two bytes are relevant */
 458                 reg = <0x1f4 0x4>;
 459         };
 460 };
 461
 462 &ethmac {
 463         clocks = <&clkc CLKID_ETH>;
 464         clock-names = "stmmaceth";
 465
 466         power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
 467 };
 468
 469 &gpio_intc {
 470         compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
 471         status = "okay";
 472 };
 473
 474 &hhi {
 475         clkc: clock-controller {
 476                 compatible = "amlogic,meson8-clkc";
 477                 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
 478                 clock-names = "xtal", "ddr_pll";
 479                 #clock-cells = <1>;
 480                 #reset-cells = <1>;
 481         };
 482
 483         pwrc: power-controller {
 484                 compatible = "amlogic,meson8-pwrc";
 485                 #power-domain-cells = <1>;
 486                 amlogic,ao-sysctrl = <&pmu>;
 487                 clocks = <&clkc CLKID_VPU>;
 488                 clock-names = "vpu";
 489                 assigned-clocks = <&clkc CLKID_VPU>;
 490                 assigned-clock-rates = <364285714>;
 491         };
 492 };
 493
 494 &hwrng {
 495         compatible = "amlogic,meson8-rng", "amlogic,meson-rng";
 496         clocks = <&clkc CLKID_RNG0>;
 497         clock-names = "core";
 498 };
 499
 500 &i2c_AO {
 501         clocks = <&clkc CLKID_CLK81>;
 502 };
 503
 504 &i2c_A {
 505         clocks = <&clkc CLKID_CLK81>;
 506 };
 507
 508 &i2c_B {
 509         clocks = <&clkc CLKID_CLK81>;
 510 };
 511
 512 &L2 {
 513         arm,data-latency = <3 3 3>;
 514         arm,tag-latency = <2 2 2>;
 515         arm,filter-ranges = <0x100000 0xc0000000>;
 516         prefetch-data = <1>;
 517         prefetch-instr = <1>;
 518         arm,shared-override;
 519 };
 520
 521 &periph {
 522         scu@0 {
 523                 compatible = "arm,cortex-a9-scu";
 524                 reg = <0x0 0x100>;
 525         };
 526
 527         timer@200 {
 528                 compatible = "arm,cortex-a9-global-timer";
 529                 reg = <0x200 0x20>;
 530                 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 531                 clocks = <&clkc CLKID_PERIPH>;
 532
 533                 /*
 534                  * the arm_global_timer driver currently does not handle clock
 535                  * rate changes. Keep it disabled for now.
 536                  */
 537                 status = "disabled";
 538         };
 539
 540         timer@600 {
 541                 compatible = "arm,cortex-a9-twd-timer";
 542                 reg = <0x600 0x20>;
 543                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 544                 clocks = <&clkc CLKID_PERIPH>;
 545         };
 546 };
 547
 548 &pwm_ab {
 549         compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 550 };
 551
 552 &pwm_cd {
 553         compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
 554 };
 555
 556 &rtc {
 557         compatible = "amlogic,meson8-rtc";
 558         resets = <&reset RESET_RTC>;
 559 };
 560
 561 &saradc {
 562         compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
 563         clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
 564         clock-names = "clkin", "core";
 565         amlogic,hhi-sysctrl = <&hhi>;
 566         nvmem-cells = <&temperature_calib>;
 567         nvmem-cell-names = "temperature_calib";
 568 };
 569
 570 &sdhc {
 571         compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
 572         clocks = <&xtal>,
 573                  <&clkc CLKID_FCLK_DIV4>,
 574                  <&clkc CLKID_FCLK_DIV3>,
 575                  <&clkc CLKID_FCLK_DIV5>,
 576                  <&clkc CLKID_SDHC>;
 577         clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
 578 };
 579
 580 &sdio {
 581         compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
 582         clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
 583         clock-names = "core", "clkin";
 584 };
 585
 586 &spifc {
 587         clocks = <&clkc CLKID_CLK81>;
 588 };
 589
 590 &timer_abcde {
 591         clocks = <&xtal>, <&clkc CLKID_CLK81>;
 592         clock-names = "xtal", "pclk";
 593 };
 594
 595 &uart_AO {
 596         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 597         clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
 598         clock-names = "baud", "xtal", "pclk";
 599 };
 600
 601 &uart_A {
 602         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 603         clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
 604         clock-names = "baud", "xtal", "pclk";
 605 };
 606
 607 &uart_B {
 608         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 609         clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
 610         clock-names = "baud", "xtal", "pclk";
 611 };
 612
 613 &uart_C {
 614         compatible = "amlogic,meson8-uart", "amlogic,meson-uart";
 615         clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
 616         clock-names = "baud", "xtal", "pclk";
 617 };
 618
 619 &usb0 {
 620         compatible = "amlogic,meson8-usb", "snps,dwc2";
 621         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
 622         clock-names = "otg";
 623 };
 624
 625 &usb1 {
 626         compatible = "amlogic,meson8-usb", "snps,dwc2";
 627         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
 628         clock-names = "otg";
 629 };
 630
 631 &usb0_phy {
 632         compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
 633         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
 634         clock-names = "usb_general", "usb";
 635         resets = <&reset RESET_USB_OTG>;
 636 };
 637
 638 &usb1_phy {
 639         compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
 640         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
 641         clock-names = "usb_general", "usb";
 642         resets = <&reset RESET_USB_OTG>;
 643 };