2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
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14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public
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21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
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48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/thermal/thermal.h>
54 compatible = "fsl,ls1021a";
55 interrupt-parent = <&gic>;
77 compatible = "arm,cortex-a7";
80 clocks = <&clockgen 1 0>;
85 compatible = "arm,cortex-a7";
88 clocks = <&clockgen 1 0>;
94 device_type = "memory";
95 reg = <0x0 0x0 0x0 0x0>;
99 compatible = "fixed-clock";
101 clock-frequency = <100000000>;
102 clock-output-names = "sysclk";
106 compatible = "arm,armv7-timer";
107 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
108 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
109 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
110 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
114 compatible = "arm,cortex-a7-pmu";
115 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
117 interrupt-affinity = <&cpu0>, <&cpu1>;
121 compatible = "syscon-reboot";
128 compatible = "simple-bus";
129 #address-cells = <2>;
132 interrupt-parent = <&gic>;
135 ddr: memory-controller@1080000 {
136 compatible = "fsl,qoriq-memory-controller";
137 reg = <0x0 0x1080000 0x0 0x1000>;
138 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
142 gic: interrupt-controller@1400000 {
143 compatible = "arm,gic-400", "arm,cortex-a7-gic";
144 #interrupt-cells = <3>;
145 interrupt-controller;
146 reg = <0x0 0x1401000 0x0 0x1000>,
147 <0x0 0x1402000 0x0 0x2000>,
148 <0x0 0x1404000 0x0 0x2000>,
149 <0x0 0x1406000 0x0 0x2000>;
150 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
154 msi1: msi-controller@1570e00 {
155 compatible = "fsl,ls1021a-msi";
156 reg = <0x0 0x1570e00 0x0 0x8>;
158 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
161 msi2: msi-controller@1570e08 {
162 compatible = "fsl,ls1021a-msi";
163 reg = <0x0 0x1570e08 0x0 0x8>;
165 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
169 compatible = "fsl,ifc", "simple-bus";
170 reg = <0x0 0x1530000 0x0 0x10000>;
171 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
175 compatible = "fsl,ls1021a-dcfg", "syscon";
176 reg = <0x0 0x1ee0000 0x0 0x1000>;
181 compatible = "fsl,ls1021a-qspi";
182 #address-cells = <1>;
184 reg = <0x0 0x1550000 0x0 0x10000>,
185 <0x0 0x40000000 0x0 0x20000000>;
186 reg-names = "QuadSPI", "QuadSPI-memory";
187 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
188 clock-names = "qspi_en", "qspi";
189 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
193 esdhc: esdhc@1560000 {
194 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
195 reg = <0x0 0x1560000 0x0 0x10000>;
196 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
197 clock-frequency = <0>;
198 voltage-ranges = <1800 1800 3300 3300>;
206 compatible = "fsl,ls1021a-ahci";
207 reg = <0x0 0x3200000 0x0 0x10000>,
208 <0x0 0x20220520 0x0 0x4>;
209 reg-names = "ahci", "sata-ecc";
210 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&clockgen 4 1>;
217 compatible = "fsl,ls1021a-scfg", "syscon";
218 reg = <0x0 0x1570000 0x0 0x10000>;
220 #address-cells = <1>;
222 ranges = <0x0 0x0 0x1570000 0x10000>;
224 extirq: interrupt-controller@1ac {
225 compatible = "fsl,ls1021a-extirq";
226 #interrupt-cells = <2>;
227 #address-cells = <0>;
228 interrupt-controller;
231 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
232 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
233 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
234 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
235 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
236 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
237 interrupt-map-mask = <0xffffffff 0x0>;
241 crypto: crypto@1700000 {
242 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
244 #address-cells = <1>;
246 reg = <0x0 0x1700000 0x0 0x100000>;
247 ranges = <0x0 0x0 0x1700000 0x100000>;
248 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
252 compatible = "fsl,sec-v5.0-job-ring",
253 "fsl,sec-v4.0-job-ring";
254 reg = <0x10000 0x10000>;
255 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
259 compatible = "fsl,sec-v5.0-job-ring",
260 "fsl,sec-v4.0-job-ring";
261 reg = <0x20000 0x10000>;
262 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
266 compatible = "fsl,sec-v5.0-job-ring",
267 "fsl,sec-v4.0-job-ring";
268 reg = <0x30000 0x10000>;
269 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
273 compatible = "fsl,sec-v5.0-job-ring",
274 "fsl,sec-v4.0-job-ring";
275 reg = <0x40000 0x10000>;
276 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
281 clockgen: clocking@1ee1000 {
282 compatible = "fsl,ls1021a-clockgen";
283 reg = <0x0 0x1ee1000 0x0 0x1000>;
289 compatible = "fsl,qoriq-tmu";
290 reg = <0x0 0x1f00000 0x0 0x10000>;
291 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
292 fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>;
293 fsl,tmu-calibration = <0x00000000 0x00000020
294 0x00000001 0x00000024
295 0x00000002 0x0000002a
296 0x00000003 0x00000032
297 0x00000004 0x00000038
298 0x00000005 0x0000003e
299 0x00000006 0x00000043
300 0x00000007 0x0000004a
301 0x00000008 0x00000050
302 0x00000009 0x00000059
303 0x0000000a 0x0000005f
304 0x0000000b 0x00000066
306 0x00010000 0x00000023
307 0x00010001 0x0000002b
308 0x00010002 0x00000033
309 0x00010003 0x0000003a
310 0x00010004 0x00000042
311 0x00010005 0x0000004a
312 0x00010006 0x00000054
313 0x00010007 0x0000005c
314 0x00010008 0x00000065
315 0x00010009 0x0000006f
317 0x00020000 0x00000029
318 0x00020001 0x00000033
319 0x00020002 0x0000003d
320 0x00020003 0x00000048
321 0x00020004 0x00000054
322 0x00020005 0x00000060
323 0x00020006 0x0000006c
325 0x00030000 0x00000025
326 0x00030001 0x00000033
327 0x00030002 0x00000043
328 0x00030003 0x00000055>;
329 #thermal-sensor-cells = <1>;
333 cpu_thermal: cpu-thermal {
334 polling-delay-passive = <1000>;
335 polling-delay = <5000>;
337 thermal-sensors = <&tmu 0>;
340 cpu_alert: cpu-alert {
341 temperature = <85000>;
346 temperature = <95000>;
356 <&cpu0 THERMAL_NO_LIMIT
358 <&cpu1 THERMAL_NO_LIMIT
366 compatible = "fsl,ls1021a-v1.0-dspi";
367 #address-cells = <1>;
369 reg = <0x0 0x2100000 0x0 0x10000>;
370 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
371 clock-names = "dspi";
372 clocks = <&clockgen 4 1>;
373 spi-num-chipselects = <6>;
379 compatible = "fsl,ls1021a-v1.0-dspi";
380 #address-cells = <1>;
382 reg = <0x0 0x2110000 0x0 0x10000>;
383 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
384 clock-names = "dspi";
385 clocks = <&clockgen 4 1>;
386 spi-num-chipselects = <6>;
392 compatible = "fsl,vf610-i2c";
393 #address-cells = <1>;
395 reg = <0x0 0x2180000 0x0 0x10000>;
396 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&clockgen 4 1>;
399 dma-names = "tx", "rx";
400 dmas = <&edma0 1 39>, <&edma0 1 38>;
405 compatible = "fsl,vf610-i2c";
406 #address-cells = <1>;
408 reg = <0x0 0x2190000 0x0 0x10000>;
409 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&clockgen 4 1>;
412 dma-names = "tx", "rx";
413 dmas = <&edma0 1 37>, <&edma0 1 36>;
418 compatible = "fsl,vf610-i2c";
419 #address-cells = <1>;
421 reg = <0x0 0x21a0000 0x0 0x10000>;
422 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&clockgen 4 1>;
425 dma-names = "tx", "rx";
426 dmas = <&edma0 1 35>, <&edma0 1 34>;
430 uart0: serial@21c0500 {
431 compatible = "fsl,16550-FIFO64", "ns16550a";
432 reg = <0x0 0x21c0500 0x0 0x100>;
433 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
434 clock-frequency = <0>;
439 uart1: serial@21c0600 {
440 compatible = "fsl,16550-FIFO64", "ns16550a";
441 reg = <0x0 0x21c0600 0x0 0x100>;
442 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
443 clock-frequency = <0>;
448 uart2: serial@21d0500 {
449 compatible = "fsl,16550-FIFO64", "ns16550a";
450 reg = <0x0 0x21d0500 0x0 0x100>;
451 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
452 clock-frequency = <0>;
457 uart3: serial@21d0600 {
458 compatible = "fsl,16550-FIFO64", "ns16550a";
459 reg = <0x0 0x21d0600 0x0 0x100>;
460 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
461 clock-frequency = <0>;
466 counter0: counter@29d0000 {
467 compatible = "fsl,ftm-quaddec";
468 reg = <0x0 0x29d0000 0x0 0x10000>;
473 counter1: counter@29e0000 {
474 compatible = "fsl,ftm-quaddec";
475 reg = <0x0 0x29e0000 0x0 0x10000>;
480 counter2: counter@29f0000 {
481 compatible = "fsl,ftm-quaddec";
482 reg = <0x0 0x29f0000 0x0 0x10000>;
487 counter3: counter@2a00000 {
488 compatible = "fsl,ftm-quaddec";
489 reg = <0x0 0x2a00000 0x0 0x10000>;
494 gpio0: gpio@2300000 {
495 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
496 reg = <0x0 0x2300000 0x0 0x10000>;
497 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
500 interrupt-controller;
501 #interrupt-cells = <2>;
504 gpio1: gpio@2310000 {
505 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
506 reg = <0x0 0x2310000 0x0 0x10000>;
507 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
510 interrupt-controller;
511 #interrupt-cells = <2>;
514 gpio2: gpio@2320000 {
515 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
516 reg = <0x0 0x2320000 0x0 0x10000>;
517 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
520 interrupt-controller;
521 #interrupt-cells = <2>;
524 gpio3: gpio@2330000 {
525 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
526 reg = <0x0 0x2330000 0x0 0x10000>;
527 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
530 interrupt-controller;
531 #interrupt-cells = <2>;
534 lpuart0: serial@2950000 {
535 compatible = "fsl,ls1021a-lpuart";
536 reg = <0x0 0x2950000 0x0 0x1000>;
537 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
543 lpuart1: serial@2960000 {
544 compatible = "fsl,ls1021a-lpuart";
545 reg = <0x0 0x2960000 0x0 0x1000>;
546 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&clockgen 4 1>;
552 lpuart2: serial@2970000 {
553 compatible = "fsl,ls1021a-lpuart";
554 reg = <0x0 0x2970000 0x0 0x1000>;
555 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&clockgen 4 1>;
561 lpuart3: serial@2980000 {
562 compatible = "fsl,ls1021a-lpuart";
563 reg = <0x0 0x2980000 0x0 0x1000>;
564 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&clockgen 4 1>;
570 lpuart4: serial@2990000 {
571 compatible = "fsl,ls1021a-lpuart";
572 reg = <0x0 0x2990000 0x0 0x1000>;
573 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&clockgen 4 1>;
579 lpuart5: serial@29a0000 {
580 compatible = "fsl,ls1021a-lpuart";
581 reg = <0x0 0x29a0000 0x0 0x1000>;
582 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&clockgen 4 1>;
589 compatible = "fsl,vf610-ftm-pwm";
591 reg = <0x0 0x29d0000 0x0 0x10000>;
592 clock-names = "ftm_sys", "ftm_ext",
593 "ftm_fix", "ftm_cnt_clk_en";
594 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
595 <&clockgen 4 1>, <&clockgen 4 1>;
601 compatible = "fsl,vf610-ftm-pwm";
603 reg = <0x0 0x29e0000 0x0 0x10000>;
604 clock-names = "ftm_sys", "ftm_ext",
605 "ftm_fix", "ftm_cnt_clk_en";
606 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
607 <&clockgen 4 1>, <&clockgen 4 1>;
613 compatible = "fsl,vf610-ftm-pwm";
615 reg = <0x0 0x29f0000 0x0 0x10000>;
616 clock-names = "ftm_sys", "ftm_ext",
617 "ftm_fix", "ftm_cnt_clk_en";
618 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
619 <&clockgen 4 1>, <&clockgen 4 1>;
625 compatible = "fsl,vf610-ftm-pwm";
627 reg = <0x0 0x2a00000 0x0 0x10000>;
628 clock-names = "ftm_sys", "ftm_ext",
629 "ftm_fix", "ftm_cnt_clk_en";
630 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
631 <&clockgen 4 1>, <&clockgen 4 1>;
637 compatible = "fsl,vf610-ftm-pwm";
639 reg = <0x0 0x2a10000 0x0 0x10000>;
640 clock-names = "ftm_sys", "ftm_ext",
641 "ftm_fix", "ftm_cnt_clk_en";
642 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
643 <&clockgen 4 1>, <&clockgen 4 1>;
649 compatible = "fsl,vf610-ftm-pwm";
651 reg = <0x0 0x2a20000 0x0 0x10000>;
652 clock-names = "ftm_sys", "ftm_ext",
653 "ftm_fix", "ftm_cnt_clk_en";
654 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
655 <&clockgen 4 1>, <&clockgen 4 1>;
661 compatible = "fsl,vf610-ftm-pwm";
663 reg = <0x0 0x2a30000 0x0 0x10000>;
664 clock-names = "ftm_sys", "ftm_ext",
665 "ftm_fix", "ftm_cnt_clk_en";
666 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
667 <&clockgen 4 1>, <&clockgen 4 1>;
673 compatible = "fsl,vf610-ftm-pwm";
675 reg = <0x0 0x2a40000 0x0 0x10000>;
676 clock-names = "ftm_sys", "ftm_ext",
677 "ftm_fix", "ftm_cnt_clk_en";
678 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
679 <&clockgen 4 1>, <&clockgen 4 1>;
684 wdog0: watchdog@2ad0000 {
685 compatible = "fsl,imx21-wdt";
686 reg = <0x0 0x2ad0000 0x0 0x10000>;
687 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&clockgen 4 1>;
689 clock-names = "wdog-en";
694 #sound-dai-cells = <0>;
695 compatible = "fsl,vf610-sai";
696 reg = <0x0 0x2b50000 0x0 0x10000>;
697 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
699 <&clockgen 4 1>, <&clockgen 4 1>;
700 clock-names = "bus", "mclk1", "mclk2", "mclk3";
701 dma-names = "tx", "rx";
702 dmas = <&edma0 1 47>,
708 #sound-dai-cells = <0>;
709 compatible = "fsl,vf610-sai";
710 reg = <0x0 0x2b60000 0x0 0x10000>;
711 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
713 <&clockgen 4 1>, <&clockgen 4 1>;
714 clock-names = "bus", "mclk1", "mclk2", "mclk3";
715 dma-names = "tx", "rx";
716 dmas = <&edma0 1 45>,
721 edma0: edma@2c00000 {
723 compatible = "fsl,vf610-edma";
724 reg = <0x0 0x2c00000 0x0 0x10000>,
725 <0x0 0x2c10000 0x0 0x10000>,
726 <0x0 0x2c20000 0x0 0x10000>;
727 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
728 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
729 interrupt-names = "edma-tx", "edma-err";
732 clock-names = "dmamux0", "dmamux1";
733 clocks = <&clockgen 4 1>,
738 compatible = "fsl,ls1021a-dcu";
739 reg = <0x0 0x2ce0000 0x0 0x10000>;
740 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&clockgen 4 0>,
743 clock-names = "dcu", "pix";
748 mdio0: mdio@2d24000 {
749 compatible = "gianfar";
750 device_type = "mdio";
751 #address-cells = <1>;
753 reg = <0x0 0x2d24000 0x0 0x4000>,
754 <0x0 0x2d10030 0x0 0x4>;
757 mdio1: mdio@2d64000 {
758 compatible = "gianfar";
759 device_type = "mdio";
760 #address-cells = <1>;
762 reg = <0x0 0x2d64000 0x0 0x4000>,
763 <0x0 0x2d50030 0x0 0x4>;
767 compatible = "fsl,etsec-ptp";
768 reg = <0x0 0x2d10e00 0x0 0xb0>;
769 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
770 fsl,tclk-period = <5>;
772 fsl,tmr-add = <0xaaaaaaab>;
773 fsl,tmr-fiper1 = <999999995>;
774 fsl,tmr-fiper2 = <999999995>;
775 fsl,max-adj = <499999999>;
779 enet0: ethernet@2d10000 {
780 compatible = "fsl,etsec2";
781 device_type = "network";
782 #address-cells = <2>;
784 interrupt-parent = <&gic>;
790 queue-group@2d10000 {
791 #address-cells = <2>;
793 reg = <0x0 0x2d10000 0x0 0x1000>;
794 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
795 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
796 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
799 queue-group@2d14000 {
800 #address-cells = <2>;
802 reg = <0x0 0x2d14000 0x0 0x1000>;
803 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
804 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
809 enet1: ethernet@2d50000 {
810 compatible = "fsl,etsec2";
811 device_type = "network";
812 #address-cells = <2>;
814 interrupt-parent = <&gic>;
819 queue-group@2d50000 {
820 #address-cells = <2>;
822 reg = <0x0 0x2d50000 0x0 0x1000>;
823 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
824 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
825 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
828 queue-group@2d54000 {
829 #address-cells = <2>;
831 reg = <0x0 0x2d54000 0x0 0x1000>;
832 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
833 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
838 enet2: ethernet@2d90000 {
839 compatible = "fsl,etsec2";
840 device_type = "network";
841 #address-cells = <2>;
843 interrupt-parent = <&gic>;
848 queue-group@2d90000 {
849 #address-cells = <2>;
851 reg = <0x0 0x2d90000 0x0 0x1000>;
852 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
853 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
854 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
857 queue-group@2d94000 {
858 #address-cells = <2>;
860 reg = <0x0 0x2d94000 0x0 0x1000>;
861 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
862 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
863 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
868 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
869 reg = <0x0 0x8600000 0x0 0x1000>;
870 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
876 compatible = "snps,dwc3";
877 reg = <0x0 0x3100000 0x0 0x10000>;
878 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
880 snps,quirk-frame-length-adjustment = <0x20>;
881 snps,dis_rxdet_inp3_quirk;
882 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
886 compatible = "fsl,ls1021a-pcie";
887 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
888 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
889 reg-names = "regs", "config";
890 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
891 fsl,pcie-scfg = <&scfg 0>;
892 #address-cells = <3>;
896 bus-range = <0x0 0xff>;
897 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
898 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
899 msi-parent = <&msi1>, <&msi2>;
900 #interrupt-cells = <1>;
901 interrupt-map-mask = <0 0 0 7>;
902 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
903 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
904 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
905 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
910 compatible = "fsl,ls1021a-pcie";
911 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
912 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
913 reg-names = "regs", "config";
914 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
915 fsl,pcie-scfg = <&scfg 1>;
916 #address-cells = <3>;
920 bus-range = <0x0 0xff>;
921 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
922 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
923 msi-parent = <&msi1>, <&msi2>;
924 #interrupt-cells = <1>;
925 interrupt-map-mask = <0 0 0 7>;
926 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
927 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
928 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
929 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
934 compatible = "fsl,ls1021ar2-flexcan";
935 reg = <0x0 0x2a70000 0x0 0x1000>;
936 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
937 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
938 clock-names = "ipg", "per";
943 compatible = "fsl,ls1021ar2-flexcan";
944 reg = <0x0 0x2a80000 0x0 0x1000>;
945 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
947 clock-names = "ipg", "per";
952 compatible = "fsl,ls1021ar2-flexcan";
953 reg = <0x0 0x2a90000 0x0 0x1000>;
954 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
956 clock-names = "ipg", "per";
961 compatible = "fsl,ls1021ar2-flexcan";
962 reg = <0x0 0x2aa0000 0x0 0x1000>;
963 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
964 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
965 clock-names = "ipg", "per";
969 ocram1: sram@10000000 {
970 compatible = "mmio-sram";
971 reg = <0x0 0x10000000 0x0 0x10000>;
972 #address-cells = <1>;
974 ranges = <0x0 0x0 0x10000000 0x10000>;
977 ocram2: sram@10010000 {
978 compatible = "mmio-sram";
979 reg = <0x0 0x10010000 0x0 0x10000>;
980 #address-cells = <1>;
982 ranges = <0x0 0x0 0x10010000 0x10000>;
985 qdma: dma-controller@8390000 {
986 compatible = "fsl,ls1021a-qdma";
987 reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
988 <0x0 0x8389000 0x0 0x1000>, /* Status regs */
989 <0x0 0x838a000 0x0 0x2000>; /* Block regs */
990 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
993 interrupt-names = "qdma-error",
994 "qdma-queue0", "qdma-queue1";
997 block-offset = <0x1000>;
998 fsl,dma-queues = <2>;
1000 queue-sizes = <64 64>;
1004 rcpm: power-controller@1ee2140 {
1005 compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
1006 reg = <0x0 0x1ee2140 0x0 0x8>;
1007 #fsl,rcpm-wakeup-cells = <2>;
1010 ftm_alarm0: timer0@29d0000 {
1011 compatible = "fsl,ls1021a-ftm-alarm";
1012 reg = <0x0 0x29d0000 0x0 0x10000>;
1014 fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>;
1015 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;