1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
5 * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
7 * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mfd/atmel-flexcom.h>
14 #include <dt-bindings/dma/at91.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/microchip,lan966x.h>
19 model = "Microchip LAN966 family SoC";
20 compatible = "microchip,lan966";
21 interrupt-parent = <&gic>;
31 compatible = "arm,cortex-a7";
32 clock-frequency = <600000000>;
39 compatible = "fixed-clock";
41 clock-frequency = <162500000>;
45 compatible = "fixed-clock";
47 clock-frequency = <600000000>;
51 compatible = "fixed-clock";
53 clock-frequency = <300000000>;
57 compatible = "fixed-clock";
59 clock-frequency = <200000000>;
63 clks: clock-controller@e00c00a8 {
64 compatible = "microchip,lan966x-gck";
66 clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
67 clock-names = "cpu", "ddr", "sys";
68 reg = <0xe00c00a8 0x38>;
72 compatible = "arm,armv7-timer";
73 interrupt-parent = <&gic>;
74 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
76 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
77 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
78 clock-frequency = <37500000>;
82 compatible = "simple-bus";
87 flx0: flexcom@e0040000 {
88 compatible = "atmel,sama5d2-flexcom";
89 reg = <0xe0040000 0x100>;
90 clocks = <&clks GCK_ID_FLEXCOM0>;
93 ranges = <0x0 0xe0040000 0x800>;
97 flx1: flexcom@e0044000 {
98 compatible = "atmel,sama5d2-flexcom";
99 reg = <0xe0044000 0x100>;
100 clocks = <&clks GCK_ID_FLEXCOM1>;
101 #address-cells = <1>;
103 ranges = <0x0 0xe0044000 0x800>;
108 compatible = "atmel,at91sam9g45-trng";
109 reg = <0xe0048000 0x100>;
113 aes: crypto@e004c000 {
114 compatible = "atmel,at91sam9g46-aes";
115 reg = <0xe004c000 0x100>;
116 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
117 dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>,
118 <&dma0 AT91_XDMAC_DT_PERID(12)>;
119 dma-names = "rx", "tx";
121 clock-names = "aes_clk";
124 flx2: flexcom@e0060000 {
125 compatible = "atmel,sama5d2-flexcom";
126 reg = <0xe0060000 0x100>;
127 clocks = <&clks GCK_ID_FLEXCOM2>;
128 #address-cells = <1>;
130 ranges = <0x0 0xe0060000 0x800>;
134 flx3: flexcom@e0064000 {
135 compatible = "atmel,sama5d2-flexcom";
136 reg = <0xe0064000 0x100>;
137 clocks = <&clks GCK_ID_FLEXCOM3>;
138 #address-cells = <1>;
140 ranges = <0x0 0xe0064000 0x800>;
144 compatible = "atmel,at91sam9260-usart";
146 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
148 clock-names = "usart";
149 atmel,fifo-size = <32>;
154 dma0: dma-controller@e0068000 {
155 compatible = "microchip,sama7g5-dma";
156 reg = <0xe0068000 0x1000>;
157 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
160 clock-names = "dma_clk";
163 sha: crypto@e006c000 {
164 compatible = "atmel,at91sam9g46-sha";
165 reg = <0xe006c000 0xec>;
166 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
167 dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>;
170 clock-names = "sha_clk";
173 flx4: flexcom@e0070000 {
174 compatible = "atmel,sama5d2-flexcom";
175 reg = <0xe0070000 0x100>;
176 clocks = <&clks GCK_ID_FLEXCOM4>;
177 #address-cells = <1>;
179 ranges = <0x0 0xe0070000 0x800>;
183 timer0: timer@e008c000 {
184 compatible = "snps,dw-apb-timer";
185 reg = <0xe008c000 0x400>;
187 clock-names = "timer";
188 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
191 watchdog: watchdog@e0090000 {
192 compatible = "snps,dw-wdt";
193 reg = <0xe0090000 0x1000>;
194 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
200 compatible = "bosch,m_can";
201 reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
202 reg-names = "m_can", "message_ram";
203 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
205 interrupt-names = "int0", "int1";
206 clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>;
207 clock-names = "hclk", "cclk";
208 assigned-clocks = <&clks GCK_ID_MCAN0>;
209 assigned-clock-rates = <40000000>;
210 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
214 gpio: pinctrl@e2004064 {
215 compatible = "microchip,lan966x-pinctrl";
216 reg = <0xe2004064 0xb4>,
220 gpio-ranges = <&gpio 0 0 78>;
221 interrupt-controller;
222 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
223 #interrupt-cells = <2>;
226 gic: interrupt-controller@e8c11000 {
227 compatible = "arm,gic-400", "arm,cortex-a7-gic";
228 #interrupt-cells = <3>;
229 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
230 interrupt-controller;
231 reg = <0xe8c11000 0x1000>,